From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38AC2C433E0 for ; Fri, 5 Feb 2021 13:51:21 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B582264DF6 for ; Fri, 5 Feb 2021 13:51:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B582264DF6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=P3jx1YVIoi6ym5TgQ/r7VfskPQFwiRpm+mYQQOT0C5I=; b=fTjYkT/mw7qdHGTEZ+iSkR05q 5iVrKH+2BhxlllRUxqPEwzIpYLfYFFa64NXHoAqfMmJH3ie7OwfbhBnxJ1VGqpzqlH0QjJwWlL3kF QGpE5wr58edPMQOtb2D+n2rdLkZ4oeeKiF1opl5KNm5DtqjaiWd0V5w/NOelftR2wBLIOnQgv73OF R45SuYd3VpW9PdXbpiwf8LhZWyTpZH/FxG/+d7TSb6fZ99lq8KdmYtYY2hUalqVle+o/V2SCBGr5p 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<20210205133404.esqqeokhlp4askpq@ti.com> References: <1612517808-10010-1-git-send-email-zhengxunli@mxic.com.tw> <1612517808-10010-2-git-send-email-zhengxunli@mxic.com.tw> <20210205104736.2771074c@xps13> <20210205133404.esqqeokhlp4askpq@ti.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210205_085018_195266_60BDA1E0 X-CRM114-Status: GOOD ( 35.06 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vigneshr@ti.com, Tudor Ambarus , juliensu@mxic.com.tw, ycllin@mxic.com.tw, linux-spi@vger.kernel.org, broonie@kernel.org, linux-mtd@lists.infradead.org, zhengxunli Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgUHJhdHl1c2gsCgorVHVkb3IsIEkgZG9uJ3Qga25vdyB3aHkgaGUgd2FzJ250IENjOidlZC4K ClByYXR5dXNoIFlhZGF2IDxwLnlhZGF2QHRpLmNvbT4gd3JvdGUgb24gRnJpLCA1IEZlYiAyMDIx IDE5OjA0OjA0ICswNTMwOgoKPiBPbiAwNS8wMi8yMSAxMDo0N0FNLCBNaXF1ZWwgUmF5bmFsIHdy b3RlOgo+ID4gSGVsbG8sCj4gPiAKPiA+IHpoZW5neHVubGkgPHpoZW5neHVubGlAbXhpYy5jb20u dHc+IHdyb3RlIG9uIEZyaSwgIDUgRmViIDIwMjEgMTc6MzY6NDcKPiA+ICswODAwOgo+ID4gICAK PiA+ID4gVGhlIG9jYXRmbGFzaCBpcyBhbiB4U1BJIGNvbXBsaWFudCBvY3RhbCBEVFIgZmxhc2gu IEFkZCBzdXBwb3J0Cj4gPiA+IGZvciB1c2luZyBpdCBpbiBvY3RhbCBEVFIgbW9kZS4KPiA+ID4g Cj4gPiA+IEVuYWJsZSBPY3RhbCBEVFIgbW9kZSB3aXRoIDIwIGR1bW15IGN5Y2xlcyB0byBhbGxv dyBydW5uaW5nIGF0IHRoZQo+ID4gPiBtYXhpbXVtIHN1cHBvcnRlZCBmcmVxdWVuY3kgb2YgMjAw TWh6Lgo+ID4gPiAKPiA+ID4gVHJ5IHRvIHZlcmlmeSB0aGUgZmxhc2ggSUQgdG8gY2hlY2sgd2hl dGhlciB0aGUgZmxhc2ggbWVtb3J5IGluIG9jdGFsCj4gPiA+IERUUiBtb2RlIGlzIGNvcnJlY3Qu IFdoZW4gcmVhZGluZyBJRCBpbiBPQ1RBTCBEVFIgbW9kZSwgSUQgd2lsbCBhcHBlYXIKPiA+ID4g aW4gYSByZXBlYXRlZCBtYW5uZXIuIGV4OiBJRFswXSA9IDB4YzIsIElEWzFdID0gMHhjMiwgSURb Ml0gPSAweDk0LAo+ID4gPiBJRFszXSA9IDB4OTQuLi4gUmVhcnJhbmdlIHRoZSBvcmRlciBzbyB0 aGF0IHRoZSBJRCBjYW4gcGFzcy4KPiA+ID4gCj4gPiA+IFNpZ25lZC1vZmYtYnk6IHpoZW5neHVu bGkgPHpoZW5neHVubGlAbXhpYy5jb20udHc+Cj4gPiA+IC0tLQo+ID4gPiAgZHJpdmVycy9tdGQv c3BpLW5vci9tYWNyb25peC5jIHwgMTIxICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrCj4gPiA+ICAxIGZpbGUgY2hhbmdlZCwgMTIxIGluc2VydGlvbnMoKykKPiA+ID4g Cj4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL210ZC9zcGktbm9yL21hY3Jvbml4LmMgYi9kcml2 ZXJzL210ZC9zcGktbm9yL21hY3Jvbml4LmMKPiA+ID4gaW5kZXggOTIwM2FiYS4uNzQ5ODk3OCAx MDA2NDQKPiA+ID4gLS0tIGEvZHJpdmVycy9tdGQvc3BpLW5vci9tYWNyb25peC5jCj4gPiA+ICsr KyBiL2RyaXZlcnMvbXRkL3NwaS1ub3IvbWFjcm9uaXguYwo+ID4gPiBAQCAtOCw2ICs4LDE2IEBA Cj4gPiA+ICAKPiA+ID4gICNpbmNsdWRlICJjb3JlLmgiCj4gPiA+ICAKPiA+ID4gKyNkZWZpbmUg U1BJTk9SX09QX1JEX0NSMgkJMHg3MQkJLyogUmVhZCBjb25maWd1cmF0aW9uIHJlZ2lzdGVyIDIg Ki8KPiA+ID4gKyNkZWZpbmUgU1BJTk9SX09QX1dSX0NSMgkJMHg3MgkJLyogV3JpdGUgY29uZmln dXJhdGlvbiByZWdpc3RlciAyICovCj4gPiA+ICsjZGVmaW5lIFNQSU5PUl9PUF9NWElDX0RUUl9S RAkJMHhlZQkJLyogRmFzdCBSZWFkIG9wY29kZSBpbiBEVFIgbW9kZSAqLwo+ID4gPiArI2RlZmlu ZSBTUElOT1JfUkVHX01YSUNfQ1IyX01PREUJMHgwMDAwMDAwMAkvKiBGb3Igc2V0dGluZyBvY3Rh bCBEVFIgbW9kZSAqLwo+ID4gPiArI2RlZmluZSBTUElOT1JfUkVHX01YSUNfT1BJX0RUUl9FTgkw eDIJCS8qIEVuYWJsZSBPY3RhbCBEVFIgKi8KPiA+ID4gKyNkZWZpbmUgU1BJTk9SX1JFR19NWElD X09QSV9EVFJfRElTCTB4MQkJLyogRGlzYWJsZSBPY3RhbCBEVFIgKi8KPiA+ID4gKyNkZWZpbmUg U1BJTk9SX1JFR19NWElDX0NSMl9EQwkJMHgwMDAwMDMwMAkvKiBGb3Igc2V0dGluZyBkdW1teSBj eWNsZXMgKi8KPiA+ID4gKyNkZWZpbmUgU1BJTk9SX1JFR19NWElDX0RDXzIwCQkweDAJCS8qIFNl dHRpbmcgZHVtbXkgY3ljbGVzIHRvIDIwICovCj4gPiA+ICsjZGVmaW5lIE1YSUNfTUFYX0RDCQkJ MjAJCS8qIE1heGltdW0gdmFsdWUgb2YgZHVtbXkgY3ljbGVzICovCj4gPiA+ICsKPiA+ID4gIHN0 YXRpYyBpbnQKPiA+ID4gIG14MjVsMjU2MzVfcG9zdF9iZnB0X2ZpeHVwcyhzdHJ1Y3Qgc3BpX25v ciAqbm9yLAo+ID4gPiAgCQkJICAgIGNvbnN0IHN0cnVjdCBzZmRwX3BhcmFtZXRlcl9oZWFkZXIg KmJmcHRfaGVhZGVyLAo+ID4gPiBAQCAtMzMsNiArNDMsMTEzIEBACj4gPiA+ICAJLnBvc3RfYmZw dCA9IG14MjVsMjU2MzVfcG9zdF9iZnB0X2ZpeHVwcywKPiA+ID4gIH07Cj4gPiA+ICAKPiA+ID4g Ky8qKgo+ID4gPiArICogc3BpX25vcl9tYWNyb25peF9vY3RhbF9kdHJfZW5hYmxlKCkgLSBFbmFi bGUgb2N0YWwgRFRSIG9uIE1hY3Jvbml4IGZsYXNoZXMuCj4gPiA+ICsgKiBAbm9yOgkJcG9pbnRl ciB0byBhICdzdHJ1Y3Qgc3BpX25vcicKPiA+ID4gKyAqIEBlbmFibGU6CQl3aGV0aGVyIHRvIGVu YWJsZSBvciBkaXNhYmxlIE9jdGFsIERUUgo+ID4gPiArICoKPiA+ID4gKyAqIFRoaXMgYWxzbyBz ZXRzIHRoZSBtZW1vcnkgYWNjZXNzIGR1bW15IGN5Y2xlcyB0byAyMCB0byBhbGxvdyB0aGUgZmxh c2ggdG8KPiA+ID4gKyAqIHJ1biBhdCB1cCB0byAyMDBNSHouCj4gPiA+ICsgKgo+ID4gPiArICog UmV0dXJuOiAwIG9uIHN1Y2Nlc3MsIC1lcnJubyBvdGhlcndpc2UuCj4gPiA+ICsgKi8KPiA+ID4g K3N0YXRpYyBpbnQgc3BpX25vcl9tYWNyb25peF9vY3RhbF9kdHJfZW5hYmxlKHN0cnVjdCBzcGlf bm9yICpub3IsIGJvb2wgZW5hYmxlKQo+ID4gPiArewo+ID4gPiArCXN0cnVjdCBzcGlfbWVtX29w IG9wOwo+ID4gPiArCXU4ICpidWYgPSBub3ItPmJvdW5jZWJ1ZiwgaTsKPiA+ID4gKwlpbnQgcmV0 Owo+ID4gPiArCj4gPiA+ICsJaWYgKGVuYWJsZSkgewo+ID4gPiArCQkvKiBVc2UgMjAgZHVtbXkg Y3ljbGVzIGZvciBtZW1vcnkgYXJyYXkgcmVhZHMuICovCj4gPiA+ICsJCXJldCA9IHNwaV9ub3Jf d3JpdGVfZW5hYmxlKG5vcik7Cj4gPiA+ICsJCWlmIChyZXQpCj4gPiA+ICsJCQlyZXR1cm4gcmV0 Owo+ID4gPiArCj4gPiA+ICsJCSpidWYgPSBTUElOT1JfUkVHX01YSUNfRENfMjA7Cj4gPiA+ICsJ CW9wID0gKHN0cnVjdCBzcGlfbWVtX29wKQo+ID4gPiArCQkJU1BJX01FTV9PUChTUElfTUVNX09Q X0NNRChTUElOT1JfT1BfV1JfQ1IyLCAxKSwKPiA+ID4gKwkJCQkgICBTUElfTUVNX09QX0FERFIo NCwgU1BJTk9SX1JFR19NWElDX0NSMl9EQywgMSksCj4gPiA+ICsJCQkJICAgU1BJX01FTV9PUF9O T19EVU1NWSwKPiA+ID4gKwkJCQkgICBTUElfTUVNX09QX0RBVEFfT1VUKDEsIGJ1ZiwgMSkpOwo+ ID4gPiArCj4gPiA+ICsJCXJldCA9IHNwaV9tZW1fZXhlY19vcChub3ItPnNwaW1lbSwgJm9wKTsK PiA+ID4gKwkJaWYgKHJldCkKPiA+ID4gKwkJCXJldHVybiByZXQ7Cj4gPiA+ICsKPiA+ID4gKwkJ cmV0ID0gc3BpX25vcl93YWl0X3RpbGxfcmVhZHkobm9yKTsKPiA+ID4gKwkJaWYgKHJldCkKPiA+ ID4gKwkJCXJldHVybiByZXQ7Cj4gPiA+ICsKPiA+ID4gKwkJbm9yLT5yZWFkX2R1bW15ID0gTVhJ Q19NQVhfREM7ICAKPiA+IAo+ID4gSSBhbSBzdGlsbCBub3QgY29udmluY2VkIGJ5IHRoaXMgY29u c3RhbnQgdmFsdWUuICAKPiAKPiBJIHRoaW5rIGEgY29uc3RhbnQgdmFsdWUgaXMgZmluZS4gVGhp cyBkdW1teSBjeWNsZSB2YWx1ZSByZWZsZWN0cyBob3cgCj4gbWFueSBjeWNsZXMgdGhlIG1hc3Rl ciBjbG9jayB3b3VsZCBnbyB0aHJvdWdoIGJlZm9yZSB0aGUgZmxhc2ggc3RhcnRzIAo+IGVtaXR0 aW5nIHRoZSBkYXRhLiBJZiB0aGUgbWFzdGVyIChha2EgdGhlIGNvbnRyb2xsZXIpIGlzIHJ1bm5p bmcgYXQgYSAKPiBsb3dlciBmcmVxdWVuY3kgdGhlbiB0aG9zZSBjeWNsZXMgZ28gdGhyb3VnaCBz bG93ZXIsIGJ1dCB0aGUgZmxhc2ggc3RpbGwgCj4gd2FpdHMgZm9yIHRoZW0gdG8gZmluaXNoIGJl Zm9yZSBlbWl0dGluZyBkYXRhLiBBbmQgc2luY2UgdGhlIG1hc3RlciBpcyAKPiBkcml2aW5nIHRo ZSBjbG9jayBhbmQgdGhlIGZsYXNoIGlzIGp1c3QgInJlYWRpbmciIGl0LCBib3RoIHJlbWFpbiBp biAKPiBzeW5jLgo+IAo+IFRoZSBkdW1teSBjeWNsZXMgbmVlZCB0byBiZSBzZXQgZm9yIHRoZSB3 b3JzdCBjYXNlIHNjZW5hcmlvIFswXS4gVGhlIAo+IGZsYXNoIHVzdWFsbHkgbmVlZHMgYSBtaW5p bXVtIGFtb3VudCBvZiB0aW1lIGJlZm9yZSBpdCBpcyByZWFkeSB0byBlbWl0IAo+IHRoZSBkYXRh LiBTbyBmb3IgZXhhbXBsZSBpZiB0aGUgbWFzdGVyIGlzIGF0IDI1IE1IeiwgdGhlIGNsb2NrIHBl cmlvZCBpcyAKPiBsb25nZXIgc28gOCBjbG9jayBjeWNsZXMgWzFdIG1pZ2h0IGJlIGxvbmcgZW5v dWdoIHRvIGV4Y2VlZCB0aGF0IG1pbmltdW0gCj4gdGltZS4gQnV0IHdoZW4gdGhlIG1hc3RlciBp cyBydW5uaW5nIGF0IDIwMCBNSHosIHRoZSBjbG9jayBwZXJpb2QgaXMgCj4gc21hbGxlciBzbyA4 IGN5Y2xlcyBtaWdodCBub3QgZ2l2ZSB0aGUgZmxhc2ggZW5vdWdoIHRpbWUgdG8gcHJlcGFyZS4g U28gCj4gd2UgbmVlZCB0byB0byB3YWl0IGF0IGxlYXN0IDIwIGN5Y2xlcyBbMV0gYmVmb3JlIGVt aXR0aW5nIGRhdGEuCj4gCj4gVGhpcyBpcyB3aGF0IG15IHBhdGNoZXMgZG8gZm9yIHRoZSBDeXBy ZXNzIFMyOCBmbGFzaC4gSSBoYXZlIHRlc3RlZCBpdCAKPiBvbiBib3RoIDI1IE1IeiBhbmQgMTY2 IE1IeiB3aXRoIDIyIGR1bW15IGN5Y2xlcy4gSXQgaXMgbm90IHRoZSBtb3N0IAo+IGVmZmljaWVu dCBhdCAyNSBNSHogc2luY2UgNSBkdW1teSBjeWNsZXMgaXMgYWxsIHRoYXQgaXMgbmVlZGVkIGZv ciB0aGF0IAo+IHNwZWVkLCBidXQgaXRzIHRoZSBiZXN0IHdlIGNhbiBkbyByaWdodCBub3cuCj4g Cj4gWzBdIFNpbmNlIFNQSSBOT1IgaGFzIG5vIHdheSBvZiBrbm93aW5nIHdoYXQgc3BlZWQgdGhl IGNvbnRyb2xsZXIgaXMgCj4gcnVubmluZyBhdCwgYXNzdW1lIHRoZSBmYXN0ZXN0IHNwZWVkIHRo ZSBmbGFzaCBjYW4gcnVuIGF0Lgo+IFsxXSBIeXBvdGhldGljYWwgZXhhbXBsZS4gRG9uJ3Qga25v dyB0aGUgYWN0dWFsIHZhbHVlcyBmb3IgdGhpcyBmbGFzaC4KCklzbid0IHRoaXMgYSBwcmVjaW91 cyBsb3NzIG9mIHRpbWU/CgpJZiB0aGVyZSBpcyBhY3R1YWxseSBubyB3YXkgdG8gcmV0cmlldmUg dGhlIGFjdHVhbCBTUEkgc3BlZWQgSSBmdWxseQpnZXQgeW91ciBwb2ludCwgYnV0IEkgZG91YnQg aXQuIE9yIGF0IGxlYXN0LCBJIHRoaW5rIHRoaXMgc2hvdWxkIGJlCm9wdGltaXplZC4KClBlcmhh cHMgTWFyayBjYW4gc2hlZCBzb21lIGxpZ2h0IG9uIHRoaXM/CgpUaGFua3MsCk1pcXXDqGwKCl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpMaW51 eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcv bWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B558C433DB for ; Fri, 5 Feb 2021 13:53:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C802964FC8 for ; Fri, 5 Feb 2021 13:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231269AbhBENx0 convert rfc822-to-8bit (ORCPT ); Fri, 5 Feb 2021 08:53:26 -0500 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:59391 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231463AbhBENvK (ORCPT ); Fri, 5 Feb 2021 08:51:10 -0500 X-Originating-IP: 90.89.227.234 Received: from xps13 (lfbn-tou-1-1424-234.w90-89.abo.wanadoo.fr [90.89.227.234]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 059896000D; Fri, 5 Feb 2021 13:50:14 +0000 (UTC) Date: Fri, 5 Feb 2021 14:50:13 +0100 From: Miquel Raynal To: Pratyush Yadav Cc: zhengxunli , , , , , , , Tudor Ambarus Subject: Re: [PATCH v2 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash Message-ID: <20210205145013.26c90b8a@xps13> In-Reply-To: <20210205133404.esqqeokhlp4askpq@ti.com> References: <1612517808-10010-1-git-send-email-zhengxunli@mxic.com.tw> <1612517808-10010-2-git-send-email-zhengxunli@mxic.com.tw> <20210205104736.2771074c@xps13> <20210205133404.esqqeokhlp4askpq@ti.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi Pratyush, +Tudor, I don't know why he was'nt Cc:'ed. Pratyush Yadav wrote on Fri, 5 Feb 2021 19:04:04 +0530: > On 05/02/21 10:47AM, Miquel Raynal wrote: > > Hello, > > > > zhengxunli wrote on Fri, 5 Feb 2021 17:36:47 > > +0800: > > > > > The ocatflash is an xSPI compliant octal DTR flash. Add support > > > for using it in octal DTR mode. > > > > > > Enable Octal DTR mode with 20 dummy cycles to allow running at the > > > maximum supported frequency of 200Mhz. > > > > > > Try to verify the flash ID to check whether the flash memory in octal > > > DTR mode is correct. When reading ID in OCTAL DTR mode, ID will appear > > > in a repeated manner. ex: ID[0] = 0xc2, ID[1] = 0xc2, ID[2] = 0x94, > > > ID[3] = 0x94... Rearrange the order so that the ID can pass. > > > > > > Signed-off-by: zhengxunli > > > --- > > > drivers/mtd/spi-nor/macronix.c | 121 +++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 121 insertions(+) > > > > > > diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c > > > index 9203aba..7498978 100644 > > > --- a/drivers/mtd/spi-nor/macronix.c > > > +++ b/drivers/mtd/spi-nor/macronix.c > > > @@ -8,6 +8,16 @@ > > > > > > #include "core.h" > > > > > > +#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ > > > +#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ > > > +#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ > > > +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ > > > +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ > > > +#define SPINOR_REG_MXIC_OPI_DTR_DIS 0x1 /* Disable Octal DTR */ > > > +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ > > > +#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ > > > +#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */ > > > + > > > static int > > > mx25l25635_post_bfpt_fixups(struct spi_nor *nor, > > > const struct sfdp_parameter_header *bfpt_header, > > > @@ -33,6 +43,113 @@ > > > .post_bfpt = mx25l25635_post_bfpt_fixups, > > > }; > > > > > > +/** > > > + * spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes. > > > + * @nor: pointer to a 'struct spi_nor' > > > + * @enable: whether to enable or disable Octal DTR > > > + * > > > + * This also sets the memory access dummy cycles to 20 to allow the flash to > > > + * run at up to 200MHz. > > > + * > > > + * Return: 0 on success, -errno otherwise. > > > + */ > > > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable) > > > +{ > > > + struct spi_mem_op op; > > > + u8 *buf = nor->bouncebuf, i; > > > + int ret; > > > + > > > + if (enable) { > > > + /* Use 20 dummy cycles for memory array reads. */ > > > + ret = spi_nor_write_enable(nor); > > > + if (ret) > > > + return ret; > > > + > > > + *buf = SPINOR_REG_MXIC_DC_20; > > > + op = (struct spi_mem_op) > > > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), > > > + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), > > > + SPI_MEM_OP_NO_DUMMY, > > > + SPI_MEM_OP_DATA_OUT(1, buf, 1)); > > > + > > > + ret = spi_mem_exec_op(nor->spimem, &op); > > > + if (ret) > > > + return ret; > > > + > > > + ret = spi_nor_wait_till_ready(nor); > > > + if (ret) > > > + return ret; > > > + > > > + nor->read_dummy = MXIC_MAX_DC; > > > > I am still not convinced by this constant value. > > I think a constant value is fine. This dummy cycle value reflects how > many cycles the master clock would go through before the flash starts > emitting the data. If the master (aka the controller) is running at a > lower frequency then those cycles go through slower, but the flash still > waits for them to finish before emitting data. And since the master is > driving the clock and the flash is just "reading" it, both remain in > sync. > > The dummy cycles need to be set for the worst case scenario [0]. The > flash usually needs a minimum amount of time before it is ready to emit > the data. So for example if the master is at 25 MHz, the clock period is > longer so 8 clock cycles [1] might be long enough to exceed that minimum > time. But when the master is running at 200 MHz, the clock period is > smaller so 8 cycles might not give the flash enough time to prepare. So > we need to to wait at least 20 cycles [1] before emitting data. > > This is what my patches do for the Cypress S28 flash. I have tested it > on both 25 MHz and 166 MHz with 22 dummy cycles. It is not the most > efficient at 25 MHz since 5 dummy cycles is all that is needed for that > speed, but its the best we can do right now. > > [0] Since SPI NOR has no way of knowing what speed the controller is > running at, assume the fastest speed the flash can run at. > [1] Hypothetical example. Don't know the actual values for this flash. Isn't this a precious loss of time? If there is actually no way to retrieve the actual SPI speed I fully get your point, but I doubt it. Or at least, I think this should be optimized. Perhaps Mark can shed some light on this? Thanks, Miquèl