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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id t27sm369693ljo.93.2021.02.10.02.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 02:04:25 -0800 (PST) Date: Wed, 10 Feb 2021 11:04:24 +0100 From: "Edgar E. Iglesias" To: Bin Meng Subject: Re: [PATCH v2 2/2] hw/ssi: xilinx_spips: Implement basic QSPI DMA support Message-ID: <20210210100424.GJ477672@toto> References: <1612761924-68000-1-git-send-email-bmeng.cn@gmail.com> <1612761924-68000-3-git-send-email-bmeng.cn@gmail.com> <20210208124425.GI477672@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , "qemu-devel@nongnu.org Developers" , Francisco Iglesias , qemu-arm , Alistair Francis Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: EMRKhKZfThb2 On Wed, Feb 10, 2021 at 05:08:01PM +0800, Bin Meng wrote: > On Tue, Feb 9, 2021 at 10:30 AM Bin Meng wrote: > > > > Hi Edgar, > > > > On Mon, Feb 8, 2021 at 11:17 PM Edgar E. Iglesias > > wrote: > > > > > > > > > > > > On Mon, Feb 8, 2021 at 3:45 PM Bin Meng wrote: > > >> > > >> Hi Edgar, > > >> > > >> On Mon, Feb 8, 2021 at 10:34 PM Edgar E. Iglesias > > >> wrote: > > >> > > > >> > > > >> > > > >> > On Mon, 8 Feb 2021, 15:10 Bin Meng, wrote: > > >> >> > > >> >> Hi Edgar, > > >> >> > > >> >> On Mon, Feb 8, 2021 at 8:44 PM Edgar E. Iglesias > > >> >> wrote: > > >> >> > > > >> >> > On Mon, Feb 08, 2021 at 01:25:24PM +0800, Bin Meng wrote: > > >> >> > > From: Xuzhou Cheng > > >> >> > > > > >> >> > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this > > >> >> > > is unimplemented. When QSPI is programmed to use DMA mode, QEMU will > > >> >> > > crash. This is observed when testing VxWorks 7. > > >> >> > > > > >> >> > > Add a basic implementation of QSPI DMA functionality. > > >> >> > > > > >> >> > > Signed-off-by: Xuzhou Cheng > > >> >> > > Signed-off-by: Bin Meng > > >> >> > > > >> >> > + Francisco > > >> >> > > > >> >> > Hi, > > >> >> > > > >> >> > Like Peter commented on the previous version, the DMA unit is actully separate. > > >> >> > > >> >> Is it really separate? In the Xilinx ZynqMP datasheet, it's an > > >> >> integrated DMA unit dedicated for QSPI usage. IIUC, other modules on > > >> >> the ZynqMP SoC cannot use it to do any DMA transfer. To me this is no > > >> >> different like a DMA engine in a ethernet controller. > > >> > > > >> > > > >> > Yes, it's a separate module. > > >> > > > >> >> > > >> >> > This module is better modelled by pushing data through the Stream framework > > >> >> > into the DMA. The DMA model is not upstream but can be found here: > > >> >> > https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c > > >> >> > > > >> >> > > >> >> What's the benefit of modeling it using the stream framework? > > >> > > > >> > > > >> > > > >> > Because it matches real hw and this particular dma exists in various instances, not only in qspi. We don't want duplicate implementations of the same dma. > > >> > > > >> > > >> Would you please share more details, like what other peripherals are > > >> using this same DMA model? > > >> > > > > > > It's used by the Crypto blocks (SHA, AES) and by the bitstream programming blocks on the ZynqMP. > > > In Versal there's the same plus some additional uses of this DMA... > > > > Sigh, it's not obvious from the ZynqMP datasheet. Indeed the crypto > > blocks seem to be using the same IP that QSPI uses for its DMA mode. > > With that additional information, I agree modeling the DMA as a > > separate model makes sense. > > > > Will investigate the Xilinx fork, and report back. > > Unfortunately the Xilinx fork of QEMU does not boot VxWorks. It looks > like the fork has quite a lot of difference from the upstream QEMU. > For example, the fork has a new machine name for ZynqMP which does not > exist in the upstream. It seems quite a lot has not been upstreamed > yet, sigh. > > The CSU DMA model in the Xilinx fork seems to be quite complicated and > has lots of functionalities. However right now our goal is to > implement a minimum model that could be used to work with the GQSPI > model to make the QSPI DMA functionality work. > We implemented a basic CSU DMA model based on the Xilinx fork, and > will send it as v3 soon. > We've prepared a patch with the QSPI DMA support using the complete DMA model. We'll send that out soon. It's better if you base your work on that. Cheers, Edgar