From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: will@kernel.org, Rich Wiley <rwiley@nvidia.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: kernel: disable CNP on Carmel
Date: Wed, 17 Feb 2021 11:22:01 +0000 [thread overview]
Message-ID: <20210217112201.GD17184@arm.com> (raw)
In-Reply-To: <e26116ff-89e4-687e-7b5d-2e5008b04511@arm.com>
On Wed, Feb 17, 2021 at 10:43:52AM +0530, Anshuman Khandual wrote:
> On 2/17/21 7:01 AM, Rich Wiley wrote:
> > On NVIDIA Carmel cores, CNP behaves differently than it does on standard
> > ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
> > entry created by core0 for a specific ASID, a non-shareable TLBI from
> > core1 may still see the shared entry. On standard ARM cores, that TLBI
> > will invalidate the shared entry as well.
>
> Could you please explain more on "may still see the shared entry" on the
> NVIDIA Carmel core vs "invalid the shared entry" on standard ARM core.
That's about the CnP feature where more than one core can share the same
TLB.
> > This causes issues with patchsets that attempt to do local TLBIs based
>
> A new patchset ? Does it impact any existing functionality ? What sort of
> issues this create ?
>
> > on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
>
> Does it affect all existing local TLBI which iterate over cpumask or are
> there some particular situations ? The problem description here needs to
> be more clear and specific.
Local TLBI does not work as described in the ARM ARM w.r.t. CnP, so CnP
needs disabling.
--
Catalin
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next prev parent reply other threads:[~2021-02-17 11:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 1:31 [PATCH] arm64: kernel: disable CNP on Carmel Rich Wiley
2021-02-17 5:13 ` Anshuman Khandual
2021-02-17 11:22 ` Catalin Marinas [this message]
2021-02-17 11:25 ` Catalin Marinas
2021-02-17 18:06 ` Will Deacon
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