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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id k27sm1329835lfm.125.2021.02.23.01.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 01:02:21 -0800 (PST) Date: Tue, 23 Feb 2021 10:02:21 +0100 From: "Edgar E. Iglesias" To: Bin Meng Subject: Re: [PATCH v4 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Message-ID: <20210223090221.GT477672@toto> References: <20210222130514.2167-1-bmeng.cn@gmail.com> <20210222130514.2167-6-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210222130514.2167-6-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , qemu-devel@nongnu.org, Francisco Iglesias , qemu-arm@nongnu.org, Alistair Francis Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: mKVKWpmBKwfL On Mon, Feb 22, 2021 at 09:05:14PM +0800, Bin Meng wrote: > From: Xuzhou Cheng > > Now that the Xilinx CSU DMA model is implemented, the existing > DMA related dead codes in the ZynqMP QSPI are useless and should > be removed. The maximum register number is also updated to only > include the QSPI registers. > > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias > > --- > > Changes in v4: > - Modify XLNX_ZYNQMP_SPIPS_R_MAX > > Changes in v3: > - new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips > > include/hw/ssi/xilinx_spips.h | 2 +- > hw/ssi/xilinx_spips.c | 10 ---------- > 2 files changed, 1 insertion(+), 11 deletions(-) > > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h > index 3eae73480e..06bfd18312 100644 > --- a/include/hw/ssi/xilinx_spips.h > +++ b/include/hw/ssi/xilinx_spips.h > @@ -34,7 +34,7 @@ > typedef struct XilinxSPIPS XilinxSPIPS; > > #define XLNX_SPIPS_R_MAX (0x100 / 4) > -#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) > +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) > > /* Bite off 4k chunks at a time */ > #define LQSPI_CACHE_SIZE 1024 > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index 8a0cc22d42..1e9dba2039 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -195,13 +195,6 @@ > #define R_GQSPI_MOD_ID (0x1fc / 4) > #define R_GQSPI_MOD_ID_RESET (0x10a0000) > > -#define R_QSPIDMA_DST_CTRL (0x80c / 4) > -#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) > -#define R_QSPIDMA_DST_I_MASK (0x820 / 4) > -#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) > -#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) > -#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) > - > /* size of TXRX FIFOs */ > #define RXFF_A (128) > #define TXFF_A (128) > @@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) > s->regs[R_GQSPI_GPIO] = 1; > s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; > s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; > - s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; > - s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; > - s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; > s->man_start_com_g = false; > s->gqspi_irqline = 0; > xlnx_zynqmp_qspips_update_ixr(s); > -- > 2.25.1 >