From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1203DC433DB for ; Tue, 23 Feb 2021 13:15:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B85D764E57 for ; Tue, 23 Feb 2021 13:15:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B85D764E57 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=r7vC2Z6vshMDpbJsWUNhuA6wAYpZCClm+0/0lRFQyhQ=; b=d4+7MNFtBiYTjMWuEnUz+olJS OFaY0ZhO+l1dAcymuHpLzp6+K/O+6WXIcMpCpBOr2HgMTzE5qogtd3pRpHQlhlVMBwFcxGbCBfjYY ujsBBHref5UCshUTgj0RrqguEZbAJGM1HDeyZaIwfFrUJHTFDfznpd32XJvNW5D+HRYDJ0Dlh1R8g /x6+LfRniLTKZ8fbNiZrXJc/56A30njm7wgGaCFEU64vXbu0PtAfLbkZJGPZJ+DZp5zX4rw7+MMz/ e0Kh0QuSXt6HD64viAQld93OEtNSJtxCpOifLfGdmRnk533d9SIiH1z3vKDklRQxV8v7BBFj4UZL5 tkEhsvJvQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lEXVn-0005Vm-Pp; Tue, 23 Feb 2021 13:13:59 +0000 Received: from relay3-d.mail.gandi.net ([217.70.183.195]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lEXVh-0005Uh-7w for linux-mtd@lists.infradead.org; Tue, 23 Feb 2021 13:13:57 +0000 X-Originating-IP: 86.210.203.113 Received: from xps13 (lfbn-tou-1-972-113.w86-210.abo.wanadoo.fr [86.210.203.113]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 9A4A760007; Tue, 23 Feb 2021 13:13:45 +0000 (UTC) Date: Tue, 23 Feb 2021 14:13:44 +0100 From: Miquel Raynal To: Pratyush Yadav Subject: Re: [PATCH v2 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash Message-ID: <20210223141344.7ad25831@xps13> In-Reply-To: <20210205133404.esqqeokhlp4askpq@ti.com> References: <1612517808-10010-1-git-send-email-zhengxunli@mxic.com.tw> <1612517808-10010-2-git-send-email-zhengxunli@mxic.com.tw> <20210205104736.2771074c@xps13> <20210205133404.esqqeokhlp4askpq@ti.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_081353_485776_E3743F4C X-CRM114-Status: GOOD ( 36.30 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vigneshr@ti.com, juliensu@mxic.com.tw, ycllin@mxic.com.tw, linux-spi@vger.kernel.org, broonie@kernel.org, linux-mtd@lists.infradead.org, zhengxunli Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgUHJhdHl1c2gsCgpQcmF0eXVzaCBZYWRhdiA8cC55YWRhdkB0aS5jb20+IHdyb3RlIG9uIEZy aSwgNSBGZWIgMjAyMSAxOTowNDowNCArMDUzMDoKCj4gT24gMDUvMDIvMjEgMTA6NDdBTSwgTWlx dWVsIFJheW5hbCB3cm90ZToKPiA+IEhlbGxvLAo+ID4gCj4gPiB6aGVuZ3h1bmxpIDx6aGVuZ3h1 bmxpQG14aWMuY29tLnR3PiB3cm90ZSBvbiBGcmksICA1IEZlYiAyMDIxIDE3OjM2OjQ3Cj4gPiAr MDgwMDoKPiA+ICAgCj4gPiA+IFRoZSBvY2F0Zmxhc2ggaXMgYW4geFNQSSBjb21wbGlhbnQgb2N0 YWwgRFRSIGZsYXNoLiBBZGQgc3VwcG9ydAo+ID4gPiBmb3IgdXNpbmcgaXQgaW4gb2N0YWwgRFRS IG1vZGUuCj4gPiA+IAo+ID4gPiBFbmFibGUgT2N0YWwgRFRSIG1vZGUgd2l0aCAyMCBkdW1teSBj eWNsZXMgdG8gYWxsb3cgcnVubmluZyBhdCB0aGUKPiA+ID4gbWF4aW11bSBzdXBwb3J0ZWQgZnJl cXVlbmN5IG9mIDIwME1oei4KPiA+ID4gCj4gPiA+IFRyeSB0byB2ZXJpZnkgdGhlIGZsYXNoIElE IHRvIGNoZWNrIHdoZXRoZXIgdGhlIGZsYXNoIG1lbW9yeSBpbiBvY3RhbAo+ID4gPiBEVFIgbW9k ZSBpcyBjb3JyZWN0LiBXaGVuIHJlYWRpbmcgSUQgaW4gT0NUQUwgRFRSIG1vZGUsIElEIHdpbGwg YXBwZWFyCj4gPiA+IGluIGEgcmVwZWF0ZWQgbWFubmVyLiBleDogSURbMF0gPSAweGMyLCBJRFsx XSA9IDB4YzIsIElEWzJdID0gMHg5NCwKPiA+ID4gSURbM10gPSAweDk0Li4uIFJlYXJyYW5nZSB0 aGUgb3JkZXIgc28gdGhhdCB0aGUgSUQgY2FuIHBhc3MuCj4gPiA+IAo+ID4gPiBTaWduZWQtb2Zm LWJ5OiB6aGVuZ3h1bmxpIDx6aGVuZ3h1bmxpQG14aWMuY29tLnR3Pgo+ID4gPiAtLS0KPiA+ID4g IGRyaXZlcnMvbXRkL3NwaS1ub3IvbWFjcm9uaXguYyB8IDEyMSArKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKwo+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDEyMSBpbnNlcnRp b25zKCspCj4gPiA+IAo+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQvc3BpLW5vci9tYWNy b25peC5jIGIvZHJpdmVycy9tdGQvc3BpLW5vci9tYWNyb25peC5jCj4gPiA+IGluZGV4IDkyMDNh YmEuLjc0OTg5NzggMTAwNjQ0Cj4gPiA+IC0tLSBhL2RyaXZlcnMvbXRkL3NwaS1ub3IvbWFjcm9u aXguYwo+ID4gPiArKysgYi9kcml2ZXJzL210ZC9zcGktbm9yL21hY3Jvbml4LmMKPiA+ID4gQEAg LTgsNiArOCwxNiBAQAo+ID4gPiAgCj4gPiA+ICAjaW5jbHVkZSAiY29yZS5oIgo+ID4gPiAgCj4g PiA+ICsjZGVmaW5lIFNQSU5PUl9PUF9SRF9DUjIJCTB4NzEJCS8qIFJlYWQgY29uZmlndXJhdGlv biByZWdpc3RlciAyICovCj4gPiA+ICsjZGVmaW5lIFNQSU5PUl9PUF9XUl9DUjIJCTB4NzIJCS8q IFdyaXRlIGNvbmZpZ3VyYXRpb24gcmVnaXN0ZXIgMiAqLwo+ID4gPiArI2RlZmluZSBTUElOT1Jf T1BfTVhJQ19EVFJfUkQJCTB4ZWUJCS8qIEZhc3QgUmVhZCBvcGNvZGUgaW4gRFRSIG1vZGUgKi8K PiA+ID4gKyNkZWZpbmUgU1BJTk9SX1JFR19NWElDX0NSMl9NT0RFCTB4MDAwMDAwMDAJLyogRm9y IHNldHRpbmcgb2N0YWwgRFRSIG1vZGUgKi8KPiA+ID4gKyNkZWZpbmUgU1BJTk9SX1JFR19NWElD X09QSV9EVFJfRU4JMHgyCQkvKiBFbmFibGUgT2N0YWwgRFRSICovCj4gPiA+ICsjZGVmaW5lIFNQ SU5PUl9SRUdfTVhJQ19PUElfRFRSX0RJUwkweDEJCS8qIERpc2FibGUgT2N0YWwgRFRSICovCj4g PiA+ICsjZGVmaW5lIFNQSU5PUl9SRUdfTVhJQ19DUjJfREMJCTB4MDAwMDAzMDAJLyogRm9yIHNl dHRpbmcgZHVtbXkgY3ljbGVzICovCj4gPiA+ICsjZGVmaW5lIFNQSU5PUl9SRUdfTVhJQ19EQ18y MAkJMHgwCQkvKiBTZXR0aW5nIGR1bW15IGN5Y2xlcyB0byAyMCAqLwo+ID4gPiArI2RlZmluZSBN WElDX01BWF9EQwkJCTIwCQkvKiBNYXhpbXVtIHZhbHVlIG9mIGR1bW15IGN5Y2xlcyAqLwo+ID4g PiArCj4gPiA+ICBzdGF0aWMgaW50Cj4gPiA+ICBteDI1bDI1NjM1X3Bvc3RfYmZwdF9maXh1cHMo c3RydWN0IHNwaV9ub3IgKm5vciwKPiA+ID4gIAkJCSAgICBjb25zdCBzdHJ1Y3Qgc2ZkcF9wYXJh bWV0ZXJfaGVhZGVyICpiZnB0X2hlYWRlciwKPiA+ID4gQEAgLTMzLDYgKzQzLDExMyBAQAo+ID4g PiAgCS5wb3N0X2JmcHQgPSBteDI1bDI1NjM1X3Bvc3RfYmZwdF9maXh1cHMsCj4gPiA+ICB9Owo+ ID4gPiAgCj4gPiA+ICsvKioKPiA+ID4gKyAqIHNwaV9ub3JfbWFjcm9uaXhfb2N0YWxfZHRyX2Vu YWJsZSgpIC0gRW5hYmxlIG9jdGFsIERUUiBvbiBNYWNyb25peCBmbGFzaGVzLgo+ID4gPiArICog QG5vcjoJCXBvaW50ZXIgdG8gYSAnc3RydWN0IHNwaV9ub3InCj4gPiA+ICsgKiBAZW5hYmxlOgkJ d2hldGhlciB0byBlbmFibGUgb3IgZGlzYWJsZSBPY3RhbCBEVFIKPiA+ID4gKyAqCj4gPiA+ICsg KiBUaGlzIGFsc28gc2V0cyB0aGUgbWVtb3J5IGFjY2VzcyBkdW1teSBjeWNsZXMgdG8gMjAgdG8g YWxsb3cgdGhlIGZsYXNoIHRvCj4gPiA+ICsgKiBydW4gYXQgdXAgdG8gMjAwTUh6Lgo+ID4gPiAr ICoKPiA+ID4gKyAqIFJldHVybjogMCBvbiBzdWNjZXNzLCAtZXJybm8gb3RoZXJ3aXNlLgo+ID4g PiArICovCj4gPiA+ICtzdGF0aWMgaW50IHNwaV9ub3JfbWFjcm9uaXhfb2N0YWxfZHRyX2VuYWJs ZShzdHJ1Y3Qgc3BpX25vciAqbm9yLCBib29sIGVuYWJsZSkKPiA+ID4gK3sKPiA+ID4gKwlzdHJ1 Y3Qgc3BpX21lbV9vcCBvcDsKPiA+ID4gKwl1OCAqYnVmID0gbm9yLT5ib3VuY2VidWYsIGk7Cj4g PiA+ICsJaW50IHJldDsKPiA+ID4gKwo+ID4gPiArCWlmIChlbmFibGUpIHsKPiA+ID4gKwkJLyog VXNlIDIwIGR1bW15IGN5Y2xlcyBmb3IgbWVtb3J5IGFycmF5IHJlYWRzLiAqLwo+ID4gPiArCQly ZXQgPSBzcGlfbm9yX3dyaXRlX2VuYWJsZShub3IpOwo+ID4gPiArCQlpZiAocmV0KQo+ID4gPiAr CQkJcmV0dXJuIHJldDsKPiA+ID4gKwo+ID4gPiArCQkqYnVmID0gU1BJTk9SX1JFR19NWElDX0RD XzIwOwo+ID4gPiArCQlvcCA9IChzdHJ1Y3Qgc3BpX21lbV9vcCkKPiA+ID4gKwkJCVNQSV9NRU1f T1AoU1BJX01FTV9PUF9DTUQoU1BJTk9SX09QX1dSX0NSMiwgMSksCj4gPiA+ICsJCQkJICAgU1BJ X01FTV9PUF9BRERSKDQsIFNQSU5PUl9SRUdfTVhJQ19DUjJfREMsIDEpLAo+ID4gPiArCQkJCSAg IFNQSV9NRU1fT1BfTk9fRFVNTVksCj4gPiA+ICsJCQkJICAgU1BJX01FTV9PUF9EQVRBX09VVCgx LCBidWYsIDEpKTsKPiA+ID4gKwo+ID4gPiArCQlyZXQgPSBzcGlfbWVtX2V4ZWNfb3Aobm9yLT5z cGltZW0sICZvcCk7Cj4gPiA+ICsJCWlmIChyZXQpCj4gPiA+ICsJCQlyZXR1cm4gcmV0Owo+ID4g PiArCj4gPiA+ICsJCXJldCA9IHNwaV9ub3Jfd2FpdF90aWxsX3JlYWR5KG5vcik7Cj4gPiA+ICsJ CWlmIChyZXQpCj4gPiA+ICsJCQlyZXR1cm4gcmV0Owo+ID4gPiArCj4gPiA+ICsJCW5vci0+cmVh ZF9kdW1teSA9IE1YSUNfTUFYX0RDOyAgCj4gPiAKPiA+IEkgYW0gc3RpbGwgbm90IGNvbnZpbmNl ZCBieSB0aGlzIGNvbnN0YW50IHZhbHVlLiAgCj4gCj4gSSB0aGluayBhIGNvbnN0YW50IHZhbHVl IGlzIGZpbmUuIFRoaXMgZHVtbXkgY3ljbGUgdmFsdWUgcmVmbGVjdHMgaG93IAo+IG1hbnkgY3lj bGVzIHRoZSBtYXN0ZXIgY2xvY2sgd291bGQgZ28gdGhyb3VnaCBiZWZvcmUgdGhlIGZsYXNoIHN0 YXJ0cyAKPiBlbWl0dGluZyB0aGUgZGF0YS4gSWYgdGhlIG1hc3RlciAoYWthIHRoZSBjb250cm9s bGVyKSBpcyBydW5uaW5nIGF0IGEgCj4gbG93ZXIgZnJlcXVlbmN5IHRoZW4gdGhvc2UgY3ljbGVz IGdvIHRocm91Z2ggc2xvd2VyLCBidXQgdGhlIGZsYXNoIHN0aWxsIAo+IHdhaXRzIGZvciB0aGVt IHRvIGZpbmlzaCBiZWZvcmUgZW1pdHRpbmcgZGF0YS4gQW5kIHNpbmNlIHRoZSBtYXN0ZXIgaXMg Cj4gZHJpdmluZyB0aGUgY2xvY2sgYW5kIHRoZSBmbGFzaCBpcyBqdXN0ICJyZWFkaW5nIiBpdCwg Ym90aCByZW1haW4gaW4gCj4gc3luYy4KPiAKPiBUaGUgZHVtbXkgY3ljbGVzIG5lZWQgdG8gYmUg c2V0IGZvciB0aGUgd29yc3QgY2FzZSBzY2VuYXJpbyBbMF0uIFRoZSAKPiBmbGFzaCB1c3VhbGx5 IG5lZWRzIGEgbWluaW11bSBhbW91bnQgb2YgdGltZSBiZWZvcmUgaXQgaXMgcmVhZHkgdG8gZW1p dCAKPiB0aGUgZGF0YS4gU28gZm9yIGV4YW1wbGUgaWYgdGhlIG1hc3RlciBpcyBhdCAyNSBNSHos IHRoZSBjbG9jayBwZXJpb2QgaXMgCj4gbG9uZ2VyIHNvIDggY2xvY2sgY3ljbGVzIFsxXSBtaWdo dCBiZSBsb25nIGVub3VnaCB0byBleGNlZWQgdGhhdCBtaW5pbXVtIAo+IHRpbWUuIEJ1dCB3aGVu IHRoZSBtYXN0ZXIgaXMgcnVubmluZyBhdCAyMDAgTUh6LCB0aGUgY2xvY2sgcGVyaW9kIGlzIAo+ IHNtYWxsZXIgc28gOCBjeWNsZXMgbWlnaHQgbm90IGdpdmUgdGhlIGZsYXNoIGVub3VnaCB0aW1l IHRvIHByZXBhcmUuIFNvIAo+IHdlIG5lZWQgdG8gdG8gd2FpdCBhdCBsZWFzdCAyMCBjeWNsZXMg WzFdIGJlZm9yZSBlbWl0dGluZyBkYXRhLgo+IAo+IFRoaXMgaXMgd2hhdCBteSBwYXRjaGVzIGRv IGZvciB0aGUgQ3lwcmVzcyBTMjggZmxhc2guIEkgaGF2ZSB0ZXN0ZWQgaXQgCj4gb24gYm90aCAy NSBNSHogYW5kIDE2NiBNSHogd2l0aCAyMiBkdW1teSBjeWNsZXMuIEl0IGlzIG5vdCB0aGUgbW9z dCAKPiBlZmZpY2llbnQgYXQgMjUgTUh6IHNpbmNlIDUgZHVtbXkgY3ljbGVzIGlzIGFsbCB0aGF0 IGlzIG5lZWRlZCBmb3IgdGhhdCAKPiBzcGVlZCwgYnV0IGl0cyB0aGUgYmVzdCB3ZSBjYW4gZG8g cmlnaHQgbm93Lgo+IAo+IFswXSBTaW5jZSBTUEkgTk9SIGhhcyBubyB3YXkgb2Yga25vd2luZyB3 aGF0IHNwZWVkIHRoZSBjb250cm9sbGVyIGlzIAo+IHJ1bm5pbmcgYXQsIGFzc3VtZSB0aGUgZmFz dGVzdCBzcGVlZCB0aGUgZmxhc2ggY2FuIHJ1biBhdC4KCk9rLCBJIGFtIG5vdCBlbnRpcmVseSBj bGVhciBhYm91dCB3aGF0IGlzIGF2YWlsYWJsZS9ub3QgYXZhaWxhYmxlIGZyb20KdGhlIFNQSSBj b3JlLgoKSWYgdGhpcyBpcyB0cnVlIHRoZW4gSSBndWVzcyB3ZSBjYW4ndCBkbyBiZXR0ZXIgd2l0 aCB0aGUgY3VycmVudCBjb2RlCmJhc2UgYW5kIHRoaXMgY2FuIGJlIGltcHJvdmVkIGluIHRoZSBm dXR1cmUgaWYgbmVlZGVkLiBTbyBJJ20gZmluZSB3aXRoCnRoZSBjdXJyZW50IGltcGxlbWVudGF0 aW9uLgoKPiBbMV0gSHlwb3RoZXRpY2FsIGV4YW1wbGUuIERvbid0IGtub3cgdGhlIGFjdHVhbCB2 YWx1ZXMgZm9yIHRoaXMgZmxhc2guCj4gIAo+ID4gVGhlIHJlc3QgbG9va3MgZ29vZCB0byBtZS4g IAo+IAoKVGhhbmtzLApNaXF1w6hsCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX18KTGludXggTVREIGRpc2N1c3Npb24gbWFpbGluZyBsaXN0Cmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtbXRkLwo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CECACC433DB for ; Tue, 23 Feb 2021 13:14:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9437264E62 for ; Tue, 23 Feb 2021 13:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232599AbhBWNOc convert rfc822-to-8bit (ORCPT ); Tue, 23 Feb 2021 08:14:32 -0500 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:32889 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232529AbhBWNOb (ORCPT ); Tue, 23 Feb 2021 08:14:31 -0500 X-Originating-IP: 86.210.203.113 Received: from xps13 (lfbn-tou-1-972-113.w86-210.abo.wanadoo.fr [86.210.203.113]) (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 9A4A760007; Tue, 23 Feb 2021 13:13:45 +0000 (UTC) Date: Tue, 23 Feb 2021 14:13:44 +0100 From: Miquel Raynal To: Pratyush Yadav Cc: zhengxunli , , , , , , Subject: Re: [PATCH v2 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash Message-ID: <20210223141344.7ad25831@xps13> In-Reply-To: <20210205133404.esqqeokhlp4askpq@ti.com> References: <1612517808-10010-1-git-send-email-zhengxunli@mxic.com.tw> <1612517808-10010-2-git-send-email-zhengxunli@mxic.com.tw> <20210205104736.2771074c@xps13> <20210205133404.esqqeokhlp4askpq@ti.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hi Pratyush, Pratyush Yadav wrote on Fri, 5 Feb 2021 19:04:04 +0530: > On 05/02/21 10:47AM, Miquel Raynal wrote: > > Hello, > > > > zhengxunli wrote on Fri, 5 Feb 2021 17:36:47 > > +0800: > > > > > The ocatflash is an xSPI compliant octal DTR flash. Add support > > > for using it in octal DTR mode. > > > > > > Enable Octal DTR mode with 20 dummy cycles to allow running at the > > > maximum supported frequency of 200Mhz. > > > > > > Try to verify the flash ID to check whether the flash memory in octal > > > DTR mode is correct. When reading ID in OCTAL DTR mode, ID will appear > > > in a repeated manner. ex: ID[0] = 0xc2, ID[1] = 0xc2, ID[2] = 0x94, > > > ID[3] = 0x94... Rearrange the order so that the ID can pass. > > > > > > Signed-off-by: zhengxunli > > > --- > > > drivers/mtd/spi-nor/macronix.c | 121 +++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 121 insertions(+) > > > > > > diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c > > > index 9203aba..7498978 100644 > > > --- a/drivers/mtd/spi-nor/macronix.c > > > +++ b/drivers/mtd/spi-nor/macronix.c > > > @@ -8,6 +8,16 @@ > > > > > > #include "core.h" > > > > > > +#define SPINOR_OP_RD_CR2 0x71 /* Read configuration register 2 */ > > > +#define SPINOR_OP_WR_CR2 0x72 /* Write configuration register 2 */ > > > +#define SPINOR_OP_MXIC_DTR_RD 0xee /* Fast Read opcode in DTR mode */ > > > +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* For setting octal DTR mode */ > > > +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ > > > +#define SPINOR_REG_MXIC_OPI_DTR_DIS 0x1 /* Disable Octal DTR */ > > > +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* For setting dummy cycles */ > > > +#define SPINOR_REG_MXIC_DC_20 0x0 /* Setting dummy cycles to 20 */ > > > +#define MXIC_MAX_DC 20 /* Maximum value of dummy cycles */ > > > + > > > static int > > > mx25l25635_post_bfpt_fixups(struct spi_nor *nor, > > > const struct sfdp_parameter_header *bfpt_header, > > > @@ -33,6 +43,113 @@ > > > .post_bfpt = mx25l25635_post_bfpt_fixups, > > > }; > > > > > > +/** > > > + * spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes. > > > + * @nor: pointer to a 'struct spi_nor' > > > + * @enable: whether to enable or disable Octal DTR > > > + * > > > + * This also sets the memory access dummy cycles to 20 to allow the flash to > > > + * run at up to 200MHz. > > > + * > > > + * Return: 0 on success, -errno otherwise. > > > + */ > > > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable) > > > +{ > > > + struct spi_mem_op op; > > > + u8 *buf = nor->bouncebuf, i; > > > + int ret; > > > + > > > + if (enable) { > > > + /* Use 20 dummy cycles for memory array reads. */ > > > + ret = spi_nor_write_enable(nor); > > > + if (ret) > > > + return ret; > > > + > > > + *buf = SPINOR_REG_MXIC_DC_20; > > > + op = (struct spi_mem_op) > > > + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), > > > + SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), > > > + SPI_MEM_OP_NO_DUMMY, > > > + SPI_MEM_OP_DATA_OUT(1, buf, 1)); > > > + > > > + ret = spi_mem_exec_op(nor->spimem, &op); > > > + if (ret) > > > + return ret; > > > + > > > + ret = spi_nor_wait_till_ready(nor); > > > + if (ret) > > > + return ret; > > > + > > > + nor->read_dummy = MXIC_MAX_DC; > > > > I am still not convinced by this constant value. > > I think a constant value is fine. This dummy cycle value reflects how > many cycles the master clock would go through before the flash starts > emitting the data. If the master (aka the controller) is running at a > lower frequency then those cycles go through slower, but the flash still > waits for them to finish before emitting data. And since the master is > driving the clock and the flash is just "reading" it, both remain in > sync. > > The dummy cycles need to be set for the worst case scenario [0]. The > flash usually needs a minimum amount of time before it is ready to emit > the data. So for example if the master is at 25 MHz, the clock period is > longer so 8 clock cycles [1] might be long enough to exceed that minimum > time. But when the master is running at 200 MHz, the clock period is > smaller so 8 cycles might not give the flash enough time to prepare. So > we need to to wait at least 20 cycles [1] before emitting data. > > This is what my patches do for the Cypress S28 flash. I have tested it > on both 25 MHz and 166 MHz with 22 dummy cycles. It is not the most > efficient at 25 MHz since 5 dummy cycles is all that is needed for that > speed, but its the best we can do right now. > > [0] Since SPI NOR has no way of knowing what speed the controller is > running at, assume the fastest speed the flash can run at. Ok, I am not entirely clear about what is available/not available from the SPI core. If this is true then I guess we can't do better with the current code base and this can be improved in the future if needed. So I'm fine with the current implementation. > [1] Hypothetical example. Don't know the actual values for this flash. > > > The rest looks good to me. > Thanks, Miquèl