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Mon, 08 Mar 2021 10:23:59 -0800 (PST) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id n7sm6636715ile.12.2021.03.08.10.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 10:23:59 -0800 (PST) Received: (nullmailer pid 2741091 invoked by uid 1000); Mon, 08 Mar 2021 18:23:56 -0000 Date: Mon, 8 Mar 2021 11:23:56 -0700 From: Rob Herring To: Benjamin Gaignard Cc: p.zabel@pengutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com Subject: Re: [PATCH v3 1/5] dt-bindings: reset: IMX8MQ VPU reset Message-ID: <20210308182356.GB2735443@robh.at.kernel.org> References: <20210301151754.104749-1-benjamin.gaignard@collabora.com> <20210301151754.104749-2-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210301151754.104749-2-benjamin.gaignard@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_182401_120525_2C857706 X-CRM114-Status: GOOD ( 21.06 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Mon, Mar 01, 2021 at 04:17:50PM +0100, Benjamin Gaignard wrote: > Document bindings for IMX8MQ VPU reset hardware block > > Signed-off-by: Benjamin Gaignard > --- > .../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++ > include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++ > 2 files changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h > > diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > new file mode 100644 > index 000000000000..00020421c0e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MQ VPU Reset Controller > + > +maintainers: > + - Benjamin Gaignard > + > +description: | > + The VPU reset controller is used to reset the video processor > + unit peripherals. Device nodes that need access to reset lines should > + specify them as a reset phandle in their corresponding node as > + specified in reset.txt. > + > + For list of all valid reset indices see > + for i.MX8MQ. > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mq-vpu-reset > + - const: syscon Is there other functionality in the block? If so, add some details in 'description' above. > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 Need to say what each clock is. > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + vpu-reset@38320000 { reset-controller@... > + compatible = "fsl,imx8mq-vpu-reset", "syscon"; > + reg = <0x38320000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h > new file mode 100644 > index 000000000000..efcbe18177fe > --- /dev/null > +++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021, Collabora > + * > + * i.MX7 System Reset Controller (SRC) driver > + * > + * Author: Benjamin Gaignard > + */ > + > +#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ > +#define DT_BINDINGS_VPU_RESET_IMX8MQ > + > +#define IMX8MQ_RESET_VPU_RESET_G1 0 > +#define IMX8MQ_RESET_VPU_RESET_G2 1 > + > +#endif > -- > 2.25.1 > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97A20C433DB for ; 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Mon, 08 Mar 2021 18:23:56 -0000 Date: Mon, 8 Mar 2021 11:23:56 -0700 From: Rob Herring To: Benjamin Gaignard Cc: p.zabel@pengutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com Subject: Re: [PATCH v3 1/5] dt-bindings: reset: IMX8MQ VPU reset Message-ID: <20210308182356.GB2735443@robh.at.kernel.org> References: <20210301151754.104749-1-benjamin.gaignard@collabora.com> <20210301151754.104749-2-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210301151754.104749-2-benjamin.gaignard@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_182401_120525_2C857706 X-CRM114-Status: GOOD ( 21.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 01, 2021 at 04:17:50PM +0100, Benjamin Gaignard wrote: > Document bindings for IMX8MQ VPU reset hardware block > > Signed-off-by: Benjamin Gaignard > --- > .../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++ > include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++ > 2 files changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h > > diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > new file mode 100644 > index 000000000000..00020421c0e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MQ VPU Reset Controller > + > +maintainers: > + - Benjamin Gaignard > + > +description: | > + The VPU reset controller is used to reset the video processor > + unit peripherals. Device nodes that need access to reset lines should > + specify them as a reset phandle in their corresponding node as > + specified in reset.txt. > + > + For list of all valid reset indices see > + for i.MX8MQ. > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mq-vpu-reset > + - const: syscon Is there other functionality in the block? If so, add some details in 'description' above. > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 Need to say what each clock is. > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + vpu-reset@38320000 { reset-controller@... > + compatible = "fsl,imx8mq-vpu-reset", "syscon"; > + reg = <0x38320000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h > new file mode 100644 > index 000000000000..efcbe18177fe > --- /dev/null > +++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021, Collabora > + * > + * i.MX7 System Reset Controller (SRC) driver > + * > + * Author: Benjamin Gaignard > + */ > + > +#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ > +#define DT_BINDINGS_VPU_RESET_IMX8MQ > + > +#define IMX8MQ_RESET_VPU_RESET_G1 0 > +#define IMX8MQ_RESET_VPU_RESET_G2 1 > + > +#endif > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14B21C433E9 for ; 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Mon, 08 Mar 2021 10:23:59 -0800 (PST) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id n7sm6636715ile.12.2021.03.08.10.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 10:23:59 -0800 (PST) Received: (nullmailer pid 2741091 invoked by uid 1000); Mon, 08 Mar 2021 18:23:56 -0000 Date: Mon, 8 Mar 2021 11:23:56 -0700 From: Rob Herring To: Benjamin Gaignard Cc: p.zabel@pengutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com Subject: Re: [PATCH v3 1/5] dt-bindings: reset: IMX8MQ VPU reset Message-ID: <20210308182356.GB2735443@robh.at.kernel.org> References: <20210301151754.104749-1-benjamin.gaignard@collabora.com> <20210301151754.104749-2-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210301151754.104749-2-benjamin.gaignard@collabora.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 01, 2021 at 04:17:50PM +0100, Benjamin Gaignard wrote: > Document bindings for IMX8MQ VPU reset hardware block > > Signed-off-by: Benjamin Gaignard > --- > .../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++ > include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++ > 2 files changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h > > diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > new file mode 100644 > index 000000000000..00020421c0e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MQ VPU Reset Controller > + > +maintainers: > + - Benjamin Gaignard > + > +description: | > + The VPU reset controller is used to reset the video processor > + unit peripherals. Device nodes that need access to reset lines should > + specify them as a reset phandle in their corresponding node as > + specified in reset.txt. > + > + For list of all valid reset indices see > + for i.MX8MQ. > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mq-vpu-reset > + - const: syscon Is there other functionality in the block? If so, add some details in 'description' above. > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 Need to say what each clock is. > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + vpu-reset@38320000 { reset-controller@... > + compatible = "fsl,imx8mq-vpu-reset", "syscon"; > + reg = <0x38320000 0x10000>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h > new file mode 100644 > index 000000000000..efcbe18177fe > --- /dev/null > +++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021, Collabora > + * > + * i.MX7 System Reset Controller (SRC) driver > + * > + * Author: Benjamin Gaignard > + */ > + > +#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ > +#define DT_BINDINGS_VPU_RESET_IMX8MQ > + > +#define IMX8MQ_RESET_VPU_RESET_G1 0 > +#define IMX8MQ_RESET_VPU_RESET_G2 1 > + > +#endif > -- > 2.25.1 >