From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66FD8C433E0 for ; Tue, 9 Mar 2021 14:39:00 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 932FB64EEE for ; Tue, 9 Mar 2021 14:38:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 932FB64EEE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DB3D54B4B8; Tue, 9 Mar 2021 09:38:58 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CIpaKagrxD2D; Tue, 9 Mar 2021 09:38:55 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 131334B460; Tue, 9 Mar 2021 09:38:55 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D5E9E4B45A for ; Tue, 9 Mar 2021 09:38:53 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m+PkzXETH-g2 for ; Tue, 9 Mar 2021 09:38:49 -0500 (EST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 873614B44F for ; Tue, 9 Mar 2021 09:38:49 -0500 (EST) Received: by mail.kernel.org (Postfix) with ESMTPSA id 90F0464EEE; Tue, 9 Mar 2021 14:38:45 +0000 (UTC) Date: Tue, 9 Mar 2021 14:38:42 +0000 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH] KVM: arm64: Ensure I-cache isolation between vcpus of a same VM Message-ID: <20210309143841.GA32754@arm.com> References: <20210303164505.68492-1-maz@kernel.org> <20210309132645.GA28297@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210309132645.GA28297@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) Cc: kvm@vger.kernel.org, Marc Zyngier , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, Mar 09, 2021 at 01:26:46PM +0000, Will Deacon wrote: > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > It recently became apparent that the ARMv8 architecture has interesting > > rules regarding attributes being used when fetching instructions > > if the MMU is off at Stage-1. > > > > In this situation, the CPU is allowed to fetch from the PoC and > > allocate into the I-cache (unless the memory is mapped with > > the XN attribute at Stage-2). > > > > If we transpose this to vcpus sharing a single physical CPU, > > it is possible for a vcpu running with its MMU off to influence > > another vcpu running with its MMU on, as the latter is expected to > > fetch from the PoU (and self-patching code doesn't flush below that > > level). > > > > In order to solve this, reuse the vcpu-private TLB invalidation > > code to apply the same policy to the I-cache, nuking it every time > > the vcpu runs on a physical CPU that ran another vcpu of the same > > VM in the past. > > > > This involve renaming __kvm_tlb_flush_local_vmid() to > > __kvm_flush_cpu_context(), and inserting a local i-cache invalidation > > there. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_asm.h | 4 ++-- > > arch/arm64/kvm/arm.c | 7 ++++++- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 +++--- > > arch/arm64/kvm/hyp/nvhe/tlb.c | 3 ++- > > arch/arm64/kvm/hyp/vhe/tlb.c | 3 ++- > > 5 files changed, 15 insertions(+), 8 deletions(-) > > Since the FWB discussion doesn't affect the correctness of this patch: > > Acked-by: Will Deacon I agree. We can optimise it later for FWB. Acked-by: Catalin Marinas _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96F46C433DB for ; Tue, 9 Mar 2021 14:40:42 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D5BD64EEE for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 09, 2021 at 01:26:46PM +0000, Will Deacon wrote: > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > It recently became apparent that the ARMv8 architecture has interesting > > rules regarding attributes being used when fetching instructions > > if the MMU is off at Stage-1. > > > > In this situation, the CPU is allowed to fetch from the PoC and > > allocate into the I-cache (unless the memory is mapped with > > the XN attribute at Stage-2). > > > > If we transpose this to vcpus sharing a single physical CPU, > > it is possible for a vcpu running with its MMU off to influence > > another vcpu running with its MMU on, as the latter is expected to > > fetch from the PoU (and self-patching code doesn't flush below that > > level). > > > > In order to solve this, reuse the vcpu-private TLB invalidation > > code to apply the same policy to the I-cache, nuking it every time > > the vcpu runs on a physical CPU that ran another vcpu of the same > > VM in the past. > > > > This involve renaming __kvm_tlb_flush_local_vmid() to > > __kvm_flush_cpu_context(), and inserting a local i-cache invalidation > > there. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_asm.h | 4 ++-- > > arch/arm64/kvm/arm.c | 7 ++++++- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 +++--- > > arch/arm64/kvm/hyp/nvhe/tlb.c | 3 ++- > > arch/arm64/kvm/hyp/vhe/tlb.c | 3 ++- > > 5 files changed, 15 insertions(+), 8 deletions(-) > > Since the FWB discussion doesn't affect the correctness of this patch: > > Acked-by: Will Deacon I agree. We can optimise it later for FWB. Acked-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CD3C433E0 for ; Tue, 9 Mar 2021 14:39:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB01E65239 for ; Tue, 9 Mar 2021 14:39:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230118AbhCIOjD (ORCPT ); Tue, 9 Mar 2021 09:39:03 -0500 Received: from mail.kernel.org ([198.145.29.99]:48010 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbhCIOis (ORCPT ); Tue, 9 Mar 2021 09:38:48 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 90F0464EEE; Tue, 9 Mar 2021 14:38:45 +0000 (UTC) Date: Tue, 9 Mar 2021 14:38:42 +0000 From: Catalin Marinas To: Will Deacon Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com, James Morse , Julien Thierry , Suzuki K Poulose , Mark Rutland , Alexandru Elisei Subject: Re: [PATCH] KVM: arm64: Ensure I-cache isolation between vcpus of a same VM Message-ID: <20210309143841.GA32754@arm.com> References: <20210303164505.68492-1-maz@kernel.org> <20210309132645.GA28297@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210309132645.GA28297@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, Mar 09, 2021 at 01:26:46PM +0000, Will Deacon wrote: > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > It recently became apparent that the ARMv8 architecture has interesting > > rules regarding attributes being used when fetching instructions > > if the MMU is off at Stage-1. > > > > In this situation, the CPU is allowed to fetch from the PoC and > > allocate into the I-cache (unless the memory is mapped with > > the XN attribute at Stage-2). > > > > If we transpose this to vcpus sharing a single physical CPU, > > it is possible for a vcpu running with its MMU off to influence > > another vcpu running with its MMU on, as the latter is expected to > > fetch from the PoU (and self-patching code doesn't flush below that > > level). > > > > In order to solve this, reuse the vcpu-private TLB invalidation > > code to apply the same policy to the I-cache, nuking it every time > > the vcpu runs on a physical CPU that ran another vcpu of the same > > VM in the past. > > > > This involve renaming __kvm_tlb_flush_local_vmid() to > > __kvm_flush_cpu_context(), and inserting a local i-cache invalidation > > there. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_asm.h | 4 ++-- > > arch/arm64/kvm/arm.c | 7 ++++++- > > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 6 +++--- > > arch/arm64/kvm/hyp/nvhe/tlb.c | 3 ++- > > arch/arm64/kvm/hyp/vhe/tlb.c | 3 ++- > > 5 files changed, 15 insertions(+), 8 deletions(-) > > Since the FWB discussion doesn't affect the correctness of this patch: > > Acked-by: Will Deacon I agree. We can optimise it later for FWB. Acked-by: Catalin Marinas