[mripard:sunxi/h6-emmc-inline-encryption 4/9] drivers/soc/sunxi/sun50i_h6_emce.c:52:2: warning: ISO C90 forbids mixed declarations and code

[kernel test robot <lkp@intel.com>]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git sunxi/h6-emmc-inline-encryption
head:   00099e67ddf03c548afe5c1bdbf21e6d7ed7dba4
commit: ef9e2b4059e3b5fb67535f7a8152405cf605b60c [4/9] soc: sunxi: Add EMCE driver
config: parisc-randconfig-p001-20210324 (attached as .config)
compiler: hppa-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git/commit/?id=ef9e2b4059e3b5fb67535f7a8152405cf605b60c
        git remote add mripard https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git
        git fetch --no-tags mripard sunxi/h6-emmc-inline-encryption
        git checkout ef9e2b4059e3b5fb67535f7a8152405cf605b60c
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=parisc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/soc/sunxi/sun50i_h6_emce.c: In function 'sun50i_h6_emce_program_key':
>> drivers/soc/sunxi/sun50i_h6_emce.c:52:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
      52 |  u32 mode = readl(priv->base + 0x80) & ~GENMASK(11, 0);
         |  ^~~
   drivers/soc/sunxi/sun50i_h6_emce.c:102:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
     102 |  size_t idx = 0;
         |  ^~~~~~


vim +52 drivers/soc/sunxi/sun50i_h6_emce.c

    46	
    47	int sun50i_h6_emce_program_key(struct emce *emce, const struct emce_key *key)
    48	{
    49		struct emce_priv *priv = emce->priv;
    50	
    51		pr_crit("%s +%d 0x%x\n", __func__, __LINE__, readl(priv->base + 0x80));
  > 52		u32 mode = readl(priv->base + 0x80) & ~GENMASK(11, 0);
    53	
    54		pr_crit("%s +%d\n", __func__, __LINE__);
    55		switch (key->cipher) {
    56		case SUN50I_H6_EMCE_AES_ECB:
    57			mode |= EMCE_MODE_MODE(0);
    58			break;
    59		case SUN50I_H6_EMCE_AES_CBC:
    60			mode |= EMCE_MODE_MODE(1);
    61			break;
    62		case SUN50I_H6_EMCE_AES_XTS:
    63			mode |= EMCE_MODE_MODE(9);
    64			break;
    65		default:
    66			return -EINVAL;
    67		}
    68	
    69		pr_crit("%s +%d\n", __func__, __LINE__);
    70		switch (key->length) {
    71		case 128:
    72			mode |= EMCE_MODE_KEY_LEN(0);
    73			break;
    74		case 192:
    75			mode |= EMCE_MODE_KEY_LEN(1);
    76			break;
    77		case 256:
    78			mode |= EMCE_MODE_KEY_LEN(2);
    79			break;
    80		default:
    81			return -EINVAL;
    82		}
    83	
    84		pr_crit("%s +%d\n", __func__, __LINE__);
    85		switch (key->iv_length) {
    86		case 128:
    87			mode |= EMCE_MODE_IV_KEY_LEN(0);
    88			break;
    89		case 192:
    90			mode |= EMCE_MODE_IV_KEY_LEN(1);
    91			break;
    92		case 256:
    93			mode |= EMCE_MODE_IV_KEY_LEN(2);
    94			break;
    95		default:
    96			return -EINVAL;
    97		}
    98	
    99		pr_crit("%s +%d\n", __func__, __LINE__);
   100		sun50i_h6_emce_clear_key(emce);
   101	
   102		size_t idx = 0;
   103		size_t count = 0;
   104		while (count < key->length) {
   105			pr_crit("%s +%d idx %d\n", __func__, __LINE__, idx);
   106			writel(((u32*)key->key)[idx], priv->base + EMCE_MASTER_KEY_REG(idx));
   107			count += 32;
   108			idx += 1;
   109		}
   110	
   111		writel(mode, priv->base + 0x80);
   112		pr_crit("%s +%d 0x%x\n", __func__, __LINE__, readl(priv->base + 0x80));
   113	
   114		return 0;
   115	}
   116	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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