diff for duplicates of <20210329150020.13632-8-eajames@linux.ibm.com> diff --git a/a/1.txt b/N1/1.txt index 8301627..4df8af6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -176,12 +176,12 @@ index b47b7b995170..0a420170b3b4 100644 }; &ehci1 { -@@ -2218,6 +2373,96 @@ eeprom at 50 { +@@ -2218,6 +2373,96 @@ eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; + -+ pca2: pca9552 at 60 { ++ pca2: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; @@ -190,82 +190,82 @@ index b47b7b995170..0a420170b3b4 100644 + gpio-controller; + #gpio-cells = <2>; + -+ gpio at 0 { ++ gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 1 { ++ gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 2 { ++ gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 3 { ++ gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 4 { ++ gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 5 { ++ gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 6 { ++ gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 7 { ++ gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 8 { ++ gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 9 { ++ gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 10 { ++ gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 11 { ++ gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 12 { ++ gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 13 { ++ gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 14 { ++ gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 15 { ++ gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; @@ -273,12 +273,12 @@ index b47b7b995170..0a420170b3b4 100644 }; &i2c14 { -@@ -2227,6 +2472,96 @@ eeprom at 50 { +@@ -2227,6 +2472,96 @@ eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; + -+ pca3: pca9552 at 60 { ++ pca3: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; @@ -287,82 +287,82 @@ index b47b7b995170..0a420170b3b4 100644 + gpio-controller; + #gpio-cells = <2>; + -+ gpio at 0 { ++ gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 1 { ++ gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 2 { ++ gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 3 { ++ gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 4 { ++ gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 5 { ++ gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 6 { ++ gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 7 { ++ gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 8 { ++ gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 9 { ++ gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 10 { ++ gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 11 { ++ gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 12 { ++ gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 13 { ++ gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 14 { ++ gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 15 { ++ gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; @@ -370,12 +370,12 @@ index b47b7b995170..0a420170b3b4 100644 }; &i2c15 { -@@ -2236,6 +2571,96 @@ eeprom at 50 { +@@ -2236,6 +2571,96 @@ eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; + -+ pca4: pca9552 at 60 { ++ pca4: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; @@ -384,82 +384,82 @@ index b47b7b995170..0a420170b3b4 100644 + gpio-controller; + #gpio-cells = <2>; + -+ gpio at 0 { ++ gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 1 { ++ gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 2 { ++ gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 3 { ++ gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 4 { ++ gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 5 { ++ gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 6 { ++ gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 7 { ++ gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 8 { ++ gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 9 { ++ gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 10 { ++ gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 11 { ++ gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 12 { ++ gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 13 { ++ gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 14 { ++ gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + -+ gpio at 15 { ++ gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; diff --git a/a/content_digest b/N1/content_digest index af6f7df..3063575 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,13 @@ "From\0Eddie James <eajames@linux.ibm.com>\0" "Subject\0[PATCH 07/22] ARM: dts: aspeed: rainier: Add leds on optional DASD cards\0" "Date\0Mon, 29 Mar 2021 10:00:05 -0500\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0joel@jms.id.au\0" + "Cc\0andrew@aj.id.au" + robh+dt@kernel.org + devicetree@vger.kernel.org + linux-aspeed@lists.ozlabs.org + Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com> + " Eddie James <eajames@linux.ibm.com>\0" "\00:1\0" "b\0" "From: Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com>\n" @@ -183,12 +189,12 @@ " };\n" " \n" " &ehci1 {\n" - "@@ -2218,6 +2373,96 @@ eeprom at 50 {\n" + "@@ -2218,6 +2373,96 @@ eeprom@50 {\n" " \t\tcompatible = \"atmel,24c64\";\n" " \t\treg = <0x50>;\n" " \t};\n" "+\n" - "+\tpca2: pca9552 at 60 {\n" + "+\tpca2: pca9552@60 {\n" "+\t\tcompatible = \"nxp,pca9552\";\n" "+\t\treg = <0x60>;\n" "+\t\t#address-cells = <1>;\n" @@ -197,82 +203,82 @@ "+\t\tgpio-controller;\n" "+\t\t#gpio-cells = <2>;\n" "+\n" - "+\t\tgpio at 0 {\n" + "+\t\tgpio@0 {\n" "+\t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 1 {\n" + "+\t\tgpio@1 {\n" "+\t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 2 {\n" + "+\t\tgpio@2 {\n" "+\t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 3 {\n" + "+\t\tgpio@3 {\n" "+\t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 4 {\n" + "+\t\tgpio@4 {\n" "+\t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 5 {\n" + "+\t\tgpio@5 {\n" "+\t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 6 {\n" + "+\t\tgpio@6 {\n" "+\t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 7 {\n" + "+\t\tgpio@7 {\n" "+\t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 8 {\n" + "+\t\tgpio@8 {\n" "+\t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 9 {\n" + "+\t\tgpio@9 {\n" "+\t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 10 {\n" + "+\t\tgpio@10 {\n" "+\t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 11 {\n" + "+\t\tgpio@11 {\n" "+\t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 12 {\n" + "+\t\tgpio@12 {\n" "+\t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 13 {\n" + "+\t\tgpio@13 {\n" "+\t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 14 {\n" + "+\t\tgpio@14 {\n" "+\t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 15 {\n" + "+\t\tgpio@15 {\n" "+\t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" @@ -280,12 +286,12 @@ " };\n" " \n" " &i2c14 {\n" - "@@ -2227,6 +2472,96 @@ eeprom at 50 {\n" + "@@ -2227,6 +2472,96 @@ eeprom@50 {\n" " \t\tcompatible = \"atmel,24c64\";\n" " \t\treg = <0x50>;\n" " \t};\n" "+\n" - "+\tpca3: pca9552 at 60 {\n" + "+\tpca3: pca9552@60 {\n" "+\t\tcompatible = \"nxp,pca9552\";\n" "+\t\treg = <0x60>;\n" "+\t\t#address-cells = <1>;\n" @@ -294,82 +300,82 @@ "+\t\tgpio-controller;\n" "+\t\t#gpio-cells = <2>;\n" "+\n" - "+\t\tgpio at 0 {\n" + "+\t\tgpio@0 {\n" "+\t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 1 {\n" + "+\t\tgpio@1 {\n" "+\t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 2 {\n" + "+\t\tgpio@2 {\n" "+\t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 3 {\n" + "+\t\tgpio@3 {\n" "+\t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 4 {\n" + "+\t\tgpio@4 {\n" "+\t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 5 {\n" + "+\t\tgpio@5 {\n" "+\t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 6 {\n" + "+\t\tgpio@6 {\n" "+\t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 7 {\n" + "+\t\tgpio@7 {\n" "+\t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 8 {\n" + "+\t\tgpio@8 {\n" "+\t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 9 {\n" + "+\t\tgpio@9 {\n" "+\t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 10 {\n" + "+\t\tgpio@10 {\n" "+\t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 11 {\n" + "+\t\tgpio@11 {\n" "+\t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 12 {\n" + "+\t\tgpio@12 {\n" "+\t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 13 {\n" + "+\t\tgpio@13 {\n" "+\t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 14 {\n" + "+\t\tgpio@14 {\n" "+\t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 15 {\n" + "+\t\tgpio@15 {\n" "+\t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" @@ -377,12 +383,12 @@ " };\n" " \n" " &i2c15 {\n" - "@@ -2236,6 +2571,96 @@ eeprom at 50 {\n" + "@@ -2236,6 +2571,96 @@ eeprom@50 {\n" " \t\tcompatible = \"atmel,24c64\";\n" " \t\treg = <0x50>;\n" " \t};\n" "+\n" - "+\tpca4: pca9552 at 60 {\n" + "+\tpca4: pca9552@60 {\n" "+\t\tcompatible = \"nxp,pca9552\";\n" "+\t\treg = <0x60>;\n" "+\t\t#address-cells = <1>;\n" @@ -391,82 +397,82 @@ "+\t\tgpio-controller;\n" "+\t\t#gpio-cells = <2>;\n" "+\n" - "+\t\tgpio at 0 {\n" + "+\t\tgpio@0 {\n" "+\t\t\treg = <0>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 1 {\n" + "+\t\tgpio@1 {\n" "+\t\t\treg = <1>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 2 {\n" + "+\t\tgpio@2 {\n" "+\t\t\treg = <2>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 3 {\n" + "+\t\tgpio@3 {\n" "+\t\t\treg = <3>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 4 {\n" + "+\t\tgpio@4 {\n" "+\t\t\treg = <4>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 5 {\n" + "+\t\tgpio@5 {\n" "+\t\t\treg = <5>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 6 {\n" + "+\t\tgpio@6 {\n" "+\t\t\treg = <6>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 7 {\n" + "+\t\tgpio@7 {\n" "+\t\t\treg = <7>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 8 {\n" + "+\t\tgpio@8 {\n" "+\t\t\treg = <8>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 9 {\n" + "+\t\tgpio@9 {\n" "+\t\t\treg = <9>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 10 {\n" + "+\t\tgpio@10 {\n" "+\t\t\treg = <10>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 11 {\n" + "+\t\tgpio@11 {\n" "+\t\t\treg = <11>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 12 {\n" + "+\t\tgpio@12 {\n" "+\t\t\treg = <12>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 13 {\n" + "+\t\tgpio@13 {\n" "+\t\t\treg = <13>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 14 {\n" + "+\t\tgpio@14 {\n" "+\t\t\treg = <14>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" "+\n" - "+\t\tgpio at 15 {\n" + "+\t\tgpio@15 {\n" "+\t\t\treg = <15>;\n" "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n" "+\t\t};\n" @@ -477,4 +483,4 @@ "-- \n" 2.27.0 -0228abbd9c0b608db8225aa973a48d7053d37367591ebbafd728ab9cf6df3468 +0170c799f9ad13390c79f0931e0e9b423775983543d08930d72d629bb7401f7f
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