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diff for duplicates of <20210329150020.13632-9-eajames@linux.ibm.com>

diff --git a/a/1.txt b/N1/1.txt
index 30a63f6..269e7cd 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -84,12 +84,12 @@ index 0a420170b3b4..78238ffc8997 100644
  };
  
  &ehci1 {
-@@ -1544,6 +1608,56 @@ eeprom at 52 {
+@@ -1544,6 +1608,56 @@ eeprom@52 {
  		compatible = "atmel,24c64";
  		reg = <0x52>;
  	};
 +
-+	pca5: pca9551 at 60 {
++	pca5: pca9551@60 {
 +		compatible = "nxp,pca9551";
 +		reg = <0x60>;
 +		#address-cells = <1>;
@@ -98,42 +98,42 @@ index 0a420170b3b4..78238ffc8997 100644
 +		gpio-controller;
 +		#gpio-cells = <2>;
 +
-+		gpio at 0 {
++		gpio@0 {
 +			reg = <0>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 1 {
++		gpio@1 {
 +			reg = <1>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 2 {
++		gpio@2 {
 +			reg = <2>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 3 {
++		gpio@3 {
 +			reg = <3>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 4 {
++		gpio@4 {
 +			reg = <4>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 5 {
++		gpio@5 {
 +			reg = <5>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 6 {
++		gpio@6 {
 +			reg = <6>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 7 {
++		gpio@7 {
 +			reg = <7>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
@@ -141,12 +141,12 @@ index 0a420170b3b4..78238ffc8997 100644
  };
  
  &i2c5 {
-@@ -1568,6 +1682,106 @@ eeprom at 51 {
+@@ -1568,6 +1682,106 @@ eeprom@51 {
  		compatible = "atmel,24c64";
  		reg = <0x51>;
  	};
 +
-+	pca6: pca9551 at 60 {
++	pca6: pca9551@60 {
 +		compatible = "nxp,pca9551";
 +		reg = <0x60>;
 +		#address-cells = <1>;
@@ -155,48 +155,48 @@ index 0a420170b3b4..78238ffc8997 100644
 +		gpio-controller;
 +		#gpio-cells = <2>;
 +
-+		gpio at 0 {
++		gpio@0 {
 +			reg = <0>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 1 {
++		gpio@1 {
 +			reg = <1>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 2 {
++		gpio@2 {
 +			reg = <2>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 3 {
++		gpio@3 {
 +			reg = <3>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 4 {
++		gpio@4 {
 +			reg = <4>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 5 {
++		gpio@5 {
 +			reg = <5>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 6 {
++		gpio@6 {
 +			reg = <6>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 7 {
++		gpio@7 {
 +			reg = <7>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +	};
 +
-+	pca7: pca9551 at 61 {
++	pca7: pca9551@61 {
 +		compatible = "nxp,pca9551";
 +		reg = <0x61>;
 +		#address-cells = <1>;
@@ -205,42 +205,42 @@ index 0a420170b3b4..78238ffc8997 100644
 +		gpio-controller;
 +		#gpio-cells = <2>;
 +
-+		gpio at 0 {
++		gpio@0 {
 +			reg = <0>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 1 {
++		gpio@1 {
 +			reg = <1>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 2 {
++		gpio@2 {
 +			reg = <2>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 3 {
++		gpio@3 {
 +			reg = <3>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 4 {
++		gpio@4 {
 +			reg = <4>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 5 {
++		gpio@5 {
 +			reg = <5>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 6 {
++		gpio@6 {
 +			reg = <6>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 7 {
++		gpio@7 {
 +			reg = <7>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
@@ -248,12 +248,12 @@ index 0a420170b3b4..78238ffc8997 100644
  };
  
  &i2c6 {
-@@ -2360,6 +2574,56 @@ eeprom at 51 {
+@@ -2360,6 +2574,56 @@ eeprom@51 {
  		compatible = "atmel,24c64";
  		reg = <0x51>;
  	};
 +
-+	pca8: pca9551 at 60 {
++	pca8: pca9551@60 {
 +		compatible = "nxp,pca9551";
 +		reg = <0x60>;
 +		#address-cells = <1>;
@@ -262,42 +262,42 @@ index 0a420170b3b4..78238ffc8997 100644
 +		gpio-controller;
 +		#gpio-cells = <2>;
 +
-+		gpio at 0 {
++		gpio@0 {
 +			reg = <0>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 1 {
++		gpio@1 {
 +			reg = <1>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 2 {
++		gpio@2 {
 +			reg = <2>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 3 {
++		gpio@3 {
 +			reg = <3>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 4 {
++		gpio@4 {
 +			reg = <4>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 5 {
++		gpio@5 {
 +			reg = <5>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 6 {
++		gpio@6 {
 +			reg = <6>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
 +
-+		gpio at 7 {
++		gpio@7 {
 +			reg = <7>;
 +			type = <PCA955X_TYPE_GPIO>;
 +		};
diff --git a/a/content_digest b/N1/content_digest
index c67b5e5..a8133dc 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,13 @@
  "From\0Eddie James <eajames@linux.ibm.com>\0"
  "Subject\0[PATCH 08/22] ARM: dts: aspeed: rainier: Add leds on optional PCI cable cards\0"
  "Date\0Mon, 29 Mar 2021 10:00:06 -0500\0"
- "To\0linux-aspeed@lists.ozlabs.org\0"
+ "To\0joel@jms.id.au\0"
+ "Cc\0andrew@aj.id.au"
+  robh+dt@kernel.org
+  devicetree@vger.kernel.org
+  linux-aspeed@lists.ozlabs.org
+  Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com>
+ " Eddie James <eajames@linux.ibm.com>\0"
  "\00:1\0"
  "b\0"
  "From: Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com>\n"
@@ -91,12 +97,12 @@
  " };\n"
  " \n"
  " &ehci1 {\n"
- "@@ -1544,6 +1608,56 @@ eeprom at 52 {\n"
+ "@@ -1544,6 +1608,56 @@ eeprom@52 {\n"
  " \t\tcompatible = \"atmel,24c64\";\n"
  " \t\treg = <0x52>;\n"
  " \t};\n"
  "+\n"
- "+\tpca5: pca9551 at 60 {\n"
+ "+\tpca5: pca9551@60 {\n"
  "+\t\tcompatible = \"nxp,pca9551\";\n"
  "+\t\treg = <0x60>;\n"
  "+\t\t#address-cells = <1>;\n"
@@ -105,42 +111,42 @@
  "+\t\tgpio-controller;\n"
  "+\t\t#gpio-cells = <2>;\n"
  "+\n"
- "+\t\tgpio at 0 {\n"
+ "+\t\tgpio@0 {\n"
  "+\t\t\treg = <0>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 1 {\n"
+ "+\t\tgpio@1 {\n"
  "+\t\t\treg = <1>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 2 {\n"
+ "+\t\tgpio@2 {\n"
  "+\t\t\treg = <2>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 3 {\n"
+ "+\t\tgpio@3 {\n"
  "+\t\t\treg = <3>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 4 {\n"
+ "+\t\tgpio@4 {\n"
  "+\t\t\treg = <4>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 5 {\n"
+ "+\t\tgpio@5 {\n"
  "+\t\t\treg = <5>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 6 {\n"
+ "+\t\tgpio@6 {\n"
  "+\t\t\treg = <6>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 7 {\n"
+ "+\t\tgpio@7 {\n"
  "+\t\t\treg = <7>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
@@ -148,12 +154,12 @@
  " };\n"
  " \n"
  " &i2c5 {\n"
- "@@ -1568,6 +1682,106 @@ eeprom at 51 {\n"
+ "@@ -1568,6 +1682,106 @@ eeprom@51 {\n"
  " \t\tcompatible = \"atmel,24c64\";\n"
  " \t\treg = <0x51>;\n"
  " \t};\n"
  "+\n"
- "+\tpca6: pca9551 at 60 {\n"
+ "+\tpca6: pca9551@60 {\n"
  "+\t\tcompatible = \"nxp,pca9551\";\n"
  "+\t\treg = <0x60>;\n"
  "+\t\t#address-cells = <1>;\n"
@@ -162,48 +168,48 @@
  "+\t\tgpio-controller;\n"
  "+\t\t#gpio-cells = <2>;\n"
  "+\n"
- "+\t\tgpio at 0 {\n"
+ "+\t\tgpio@0 {\n"
  "+\t\t\treg = <0>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 1 {\n"
+ "+\t\tgpio@1 {\n"
  "+\t\t\treg = <1>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 2 {\n"
+ "+\t\tgpio@2 {\n"
  "+\t\t\treg = <2>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 3 {\n"
+ "+\t\tgpio@3 {\n"
  "+\t\t\treg = <3>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 4 {\n"
+ "+\t\tgpio@4 {\n"
  "+\t\t\treg = <4>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 5 {\n"
+ "+\t\tgpio@5 {\n"
  "+\t\t\treg = <5>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 6 {\n"
+ "+\t\tgpio@6 {\n"
  "+\t\t\treg = <6>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 7 {\n"
+ "+\t\tgpio@7 {\n"
  "+\t\t\treg = <7>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\t};\n"
  "+\n"
- "+\tpca7: pca9551 at 61 {\n"
+ "+\tpca7: pca9551@61 {\n"
  "+\t\tcompatible = \"nxp,pca9551\";\n"
  "+\t\treg = <0x61>;\n"
  "+\t\t#address-cells = <1>;\n"
@@ -212,42 +218,42 @@
  "+\t\tgpio-controller;\n"
  "+\t\t#gpio-cells = <2>;\n"
  "+\n"
- "+\t\tgpio at 0 {\n"
+ "+\t\tgpio@0 {\n"
  "+\t\t\treg = <0>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 1 {\n"
+ "+\t\tgpio@1 {\n"
  "+\t\t\treg = <1>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 2 {\n"
+ "+\t\tgpio@2 {\n"
  "+\t\t\treg = <2>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 3 {\n"
+ "+\t\tgpio@3 {\n"
  "+\t\t\treg = <3>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 4 {\n"
+ "+\t\tgpio@4 {\n"
  "+\t\t\treg = <4>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 5 {\n"
+ "+\t\tgpio@5 {\n"
  "+\t\t\treg = <5>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 6 {\n"
+ "+\t\tgpio@6 {\n"
  "+\t\t\treg = <6>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 7 {\n"
+ "+\t\tgpio@7 {\n"
  "+\t\t\treg = <7>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
@@ -255,12 +261,12 @@
  " };\n"
  " \n"
  " &i2c6 {\n"
- "@@ -2360,6 +2574,56 @@ eeprom at 51 {\n"
+ "@@ -2360,6 +2574,56 @@ eeprom@51 {\n"
  " \t\tcompatible = \"atmel,24c64\";\n"
  " \t\treg = <0x51>;\n"
  " \t};\n"
  "+\n"
- "+\tpca8: pca9551 at 60 {\n"
+ "+\tpca8: pca9551@60 {\n"
  "+\t\tcompatible = \"nxp,pca9551\";\n"
  "+\t\treg = <0x60>;\n"
  "+\t\t#address-cells = <1>;\n"
@@ -269,42 +275,42 @@
  "+\t\tgpio-controller;\n"
  "+\t\t#gpio-cells = <2>;\n"
  "+\n"
- "+\t\tgpio at 0 {\n"
+ "+\t\tgpio@0 {\n"
  "+\t\t\treg = <0>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 1 {\n"
+ "+\t\tgpio@1 {\n"
  "+\t\t\treg = <1>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 2 {\n"
+ "+\t\tgpio@2 {\n"
  "+\t\t\treg = <2>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 3 {\n"
+ "+\t\tgpio@3 {\n"
  "+\t\t\treg = <3>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 4 {\n"
+ "+\t\tgpio@4 {\n"
  "+\t\t\treg = <4>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 5 {\n"
+ "+\t\tgpio@5 {\n"
  "+\t\t\treg = <5>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 6 {\n"
+ "+\t\tgpio@6 {\n"
  "+\t\t\treg = <6>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
  "+\n"
- "+\t\tgpio at 7 {\n"
+ "+\t\tgpio@7 {\n"
  "+\t\t\treg = <7>;\n"
  "+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n"
  "+\t\t};\n"
@@ -315,4 +321,4 @@
  "-- \n"
  2.27.0
 
-2b3ebd7cf48a90b61245f01af903e7dbc5569f3224d44d97b8caf9077f87a2ff
+7baf524fec8054a24c84ed249f7c635aaf6ab1a0e1830d444f8afc2bec868828

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