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From: "David E. Box" <david.e.box@linux.intel.com>
To: irenic.rajneesh@gmail.com, hdegoede@redhat.com,
	david.e.box@linux.intel.com, mgross@linux.intel.com,
	gayatri.kammela@intel.com
Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P
Date: Wed, 31 Mar 2021 20:05:58 -0700	[thread overview]
Message-ID: <20210401030558.2301621-10-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20210401030558.2301621-1-david.e.box@linux.intel.com>

Alder PCH-P is based on Tiger Lake PCH.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 9168062c927e..88d582df829f 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -1440,6 +1440,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	&tgl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&icl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&tgl_reg_map),
+	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&tgl_reg_map),
 	{}
 };
 
-- 
2.25.1


  parent reply	other threads:[~2021-04-01  3:07 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01  3:05 [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support David E. Box
2021-04-01  3:05 ` [PATCH 1/9] platform/x86: intel_pmc_core: Don't use global pmcdev in quirks David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 14:58   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 2/9] platform/x86: intel_pmc_core: Remove global struct pmc_dev David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:02   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 3/9] platform/x86: intel_pmc_core: Handle sub-states generically David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:22   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 4/9] platform/x86: intel_pmc_core: Show LPM residency in microseconds David E. Box
2021-04-07 14:23   ` Hans de Goede
2021-04-07 15:24   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 5/9] platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake David E. Box
2021-04-07 14:27   ` Hans de Goede
2021-04-07 15:38   ` Rajneesh Bhardwaj
2021-04-01  3:05 ` [PATCH 6/9] platform/x86: intel_pmc_core: Add requirements file to debugfs David E. Box
2021-04-07 14:28   ` Hans de Goede
2021-04-07 15:45   ` Rajneesh Bhardwaj
2021-04-07 17:47     ` David E. Box
2021-04-01  3:05 ` [PATCH 7/9] platform/x86: intel_pmc_core: Add option to set/clear LPM mode David E. Box
2021-04-07 14:37   ` Hans de Goede
2021-04-07 17:19     ` David E. Box
2021-04-01  3:05 ` [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake David E. Box
2021-04-07 14:48   ` Hans de Goede
2021-04-07 15:48   ` Rajneesh Bhardwaj
2021-04-07 15:50     ` Rajneesh Bhardwaj
2021-04-01  3:05 ` David E. Box [this message]
2021-04-07 14:48   ` [PATCH 9/9] platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P Hans de Goede
2021-04-07 15:49   ` Rajneesh Bhardwaj
2021-04-07 14:49 ` [PATCH 0/9] intel_pmc_core: Add sub-state requirements and mode latching support Hans de Goede

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