diff for duplicates of <20210409162716.0000491c@Huawei.com> diff --git a/a/content_digest b/N1/content_digest index 47d3f2e..3680434 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,20 +4,20 @@ "Subject\0Re: [PATCH v4 cxl-2.0-doe 3/3] PCIe standard header for DOE\0" "Date\0Fri, 9 Apr 2021 16:27:16 +0100\0" "To\0Chris Browy <cbrowy@avery-design.com>\0" - "Cc\0<mst@redhat.com>" - <armbru@redhat.com> - <ben.widawsky@intel.com> - <dan.j.williams@intel.com> - <david@redhat.com> - <f4bug@amsat.org> - <hchkuo@avery-design.com.tw> - <imammedo@redhat.com> - <ira.weiny@intel.com> - <jgroves@micron.com> - <linux-cxl@vger.kernel.org> - <qemu-devel@nongnu.org> - <tyshao@avery-design.com.tw> - " <vishal.l.verma@intel.com>\0" + "Cc\0ben.widawsky@intel.com" + jgroves@micron.com + david@redhat.com + qemu-devel@nongnu.org + vishal.l.verma@intel.com + mst@redhat.com + armbru@redhat.com + linux-cxl@vger.kernel.org + f4bug@amsat.org + hchkuo@avery-design.com.tw + tyshao@avery-design.com.tw + imammedo@redhat.com + dan.j.williams@intel.com + " ira.weiny@intel.com\0" "\00:1\0" "b\0" "On Wed, 31 Mar 2021 12:37:08 -0400\n" @@ -81,4 +81,4 @@ "> #define PCI_EXT_CAP_DSN_SIZEOF\t12\n" > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 -becf866c4611221d1f3c130fdd87a73ec682a73359f7537e8e114e26dfab3dd1 +16c52ca457c136f435f04cd9ecbe9b515ce8476c71e5e184c4d7c336f7dc3b8c
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