Re: [PATCH] drm/amdgpu: Add graphics cache rinse packet for sdma

From: Huang Rui <ray.huang@amd.com>
To: "Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>
Cc: "Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Koenig, Christian" <Christian.Koenig@amd.com>,
	"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: Add graphics cache rinse packet for sdma
Date: Tue, 13 Apr 2021 14:41:57 +0800	[thread overview]
Message-ID: <20210413064157.GA80097@hr-amd> (raw)
In-Reply-To: <20210413062300.12558-1-Jinzhou.Su@amd.com>

On Tue, Apr 13, 2021 at 02:23:00PM +0800, Su, Jinzhou (Joe) wrote:
>   Add emit mem sync callback for sdma_v5_2

I suggest to describe the problem you encountered for this change, most of
persons would like to know how.

With that fixed, patch is Reviewed-by: Huang Rui <ray.huang@amd.com>

> 
> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 28 ++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 93f826a7d3f0..b1ad9e52b234 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -369,6 +369,33 @@ static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
>  	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
>  }
>  
> +/**
> + * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
> + *
> + * @ring: amdgpu ring pointer
> + * @job: job to retrieve vmid from
> + * @ib: IB object to schedule
> + *
> + * flush the IB by graphics cache rinse.
> + */
> +static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
> +{
> +    uint32_t gcr_cntl =
> +		    SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> +			SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> +			SDMA_GCR_GLI_INV(1);
> +
> +	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> +	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> +	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> +	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> +			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> +	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> +			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> +	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> +			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> +}
> +
>  /**
>   * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
>   *
> @@ -1663,6 +1690,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
>  		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
>  	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
>  	.emit_ib = sdma_v5_2_ring_emit_ib,
> +	.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
>  	.emit_fence = sdma_v5_2_ring_emit_fence,
>  	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
>  	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
> -- 
> 2.27.0
> 
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx