From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f172.google.com (mail-oi1-f172.google.com [209.85.167.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2503E72 for ; Fri, 30 Apr 2021 19:44:40 +0000 (UTC) Received: by mail-oi1-f172.google.com with SMTP id l17so39769427oil.11 for ; Fri, 30 Apr 2021 12:44:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=cbQQRQSYYNb4Hamcnl+TDiVyJMNuMwmcGfDu3YBv0tk=; b=GPUgh4iQHmylBARP3JqmzNIMAt0pF2fZ8i215g5Pqel7WdRKpJvKL6TgZRVoHnnp9A 0OppJ8QTIwVKaUT4cJF+9Pbquu1/Z70LK4FOz6WKWG8S6rXzOPiAyIDbSKr0OGyd1qGf thJ4hYdkWKWnt3cHsED7CPzu8zvGjgnjL8UgNHhq8WXu7ybPKyhaDkf19d0kGOgVlsVr ZEAWJThgzpgdpvk4qpaFSeeeDRB4fuvvLL7klyjeUqP5yittFvilhbR72DBA7Vv7mChf DiH1qEXsT4guv7wbjF2Frn58hGO720JTGm1zJZXwo8lUduOrWO6ZMhL+j1Kq4D21s4JZ oAlA== X-Gm-Message-State: AOAM532fYlVqFZfPHcPCmF0aWOvuK5ao8qQJaZvgbXVfLrirwRMNwmpt 8n6fbGdbZT0+jwCf6CeQMw== X-Google-Smtp-Source: ABdhPJztGli5TC5CkRdcCKaCbKgQsTL2TMovEyN2HfCyxTWUrWMsfyYqhHiiL7Jcxz9/GHnxaHjYLA== X-Received: by 2002:aca:c68a:: with SMTP id w132mr12284029oif.130.1619811879354; Fri, 30 Apr 2021 12:44:39 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id e22sm904031oii.58.2021.04.30.12.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 12:44:38 -0700 (PDT) Received: (nullmailer pid 3759998 invoked by uid 1000); Fri, 30 Apr 2021 19:44:37 -0000 Date: Fri, 30 Apr 2021 14:44:37 -0500 From: Rob Herring To: Samuel Holland Cc: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Felipe Balbi , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Document the Allwinner H6 DWC3 glue Message-ID: <20210430194437.GA3755541@robh.at.kernel.org> References: <20210430031912.42252-1-samuel@sholland.org> <20210430031912.42252-2-samuel@sholland.org> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210430031912.42252-2-samuel@sholland.org> On Thu, Apr 29, 2021 at 10:19:11PM -0500, Samuel Holland wrote: > The RST_BUS_XHCI reset line in the H6 affects both the DWC3 core and the > USB3 PHY. This suggests the reset line controls the USB3 IP as a whole. > Represent this by attaching the reset line to a glue layer device. Does that really mean anything more than a shared reset? Doesn't the reset code support shared resets? > > Signed-off-by: Samuel Holland > --- > .../usb/allwinner,sun50i-h6-dwc3.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > new file mode 100644 > index 000000000000..936b5c74043f > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/allwinner,sun50i-h6-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner H6 DWC3 USB controller > + > +maintainers: > + - Chen-Yu Tsai > + - Maxime Ripard > + > +properties: > + compatible: > + const: allwinner,sun50i-h6-dwc3 > + > + "#address-cells": true > + > + "#size-cells": true > + > + ranges: true > + > + resets: > + maxItems: 1 > + > +# Required child node: > + > +patternProperties: > + "^phy@[0-9a-f]+$": > + $ref: ../phy/allwinner,sun50i-h6-usb3-phy.yaml# > + > + "^usb@[0-9a-f]+$": > + $ref: snps,dwc3.yaml# > + > +required: > + - compatible > + - ranges > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + usb3: usb@5200000 { > + compatible = "allwinner,sun50i-h6-dwc3"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + resets = <&ccu RST_BUS_XHCI>; > + > + dwc3: usb@5200000 { > + compatible = "snps,dwc3"; > + reg = <0x05200000 0x10000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_XHCI>, > + <&ccu CLK_BUS_XHCI>, > + <&rtc 0>; > + clock-names = "ref", "bus_early", "suspend"; > + dr_mode = "host"; > + phys = <&usb3phy>; > + phy-names = "usb3-phy"; > + }; > + > + usb3phy: phy@5210000 { > + compatible = "allwinner,sun50i-h6-usb3-phy"; > + reg = <0x5210000 0x10000>; > + clocks = <&ccu CLK_USB_PHY1>; > + resets = <&ccu RST_USB_PHY1>; > + #phy-cells = <0>; > + }; > + }; > -- > 2.26.3 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3128FC433B4 for ; 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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id e22sm904031oii.58.2021.04.30.12.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 12:44:38 -0700 (PDT) Received: (nullmailer pid 3759998 invoked by uid 1000); Fri, 30 Apr 2021 19:44:37 -0000 Date: Fri, 30 Apr 2021 14:44:37 -0500 From: Rob Herring To: Samuel Holland Cc: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Felipe Balbi , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Document the Allwinner H6 DWC3 glue Message-ID: <20210430194437.GA3755541@robh.at.kernel.org> References: <20210430031912.42252-1-samuel@sholland.org> <20210430031912.42252-2-samuel@sholland.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210430031912.42252-2-samuel@sholland.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210430_124440_420583_5AE566E2 X-CRM114-Status: GOOD ( 19.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 29, 2021 at 10:19:11PM -0500, Samuel Holland wrote: > The RST_BUS_XHCI reset line in the H6 affects both the DWC3 core and the > USB3 PHY. This suggests the reset line controls the USB3 IP as a whole. > Represent this by attaching the reset line to a glue layer device. Does that really mean anything more than a shared reset? Doesn't the reset code support shared resets? > > Signed-off-by: Samuel Holland > --- > .../usb/allwinner,sun50i-h6-dwc3.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > > diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > new file mode 100644 > index 000000000000..936b5c74043f > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/allwinner,sun50i-h6-dwc3.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/allwinner,sun50i-h6-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner H6 DWC3 USB controller > + > +maintainers: > + - Chen-Yu Tsai > + - Maxime Ripard > + > +properties: > + compatible: > + const: allwinner,sun50i-h6-dwc3 > + > + "#address-cells": true > + > + "#size-cells": true > + > + ranges: true > + > + resets: > + maxItems: 1 > + > +# Required child node: > + > +patternProperties: > + "^phy@[0-9a-f]+$": > + $ref: ../phy/allwinner,sun50i-h6-usb3-phy.yaml# > + > + "^usb@[0-9a-f]+$": > + $ref: snps,dwc3.yaml# > + > +required: > + - compatible > + - ranges > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + usb3: usb@5200000 { > + compatible = "allwinner,sun50i-h6-dwc3"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + resets = <&ccu RST_BUS_XHCI>; > + > + dwc3: usb@5200000 { > + compatible = "snps,dwc3"; > + reg = <0x05200000 0x10000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_XHCI>, > + <&ccu CLK_BUS_XHCI>, > + <&rtc 0>; > + clock-names = "ref", "bus_early", "suspend"; > + dr_mode = "host"; > + phys = <&usb3phy>; > + phy-names = "usb3-phy"; > + }; > + > + usb3phy: phy@5210000 { > + compatible = "allwinner,sun50i-h6-usb3-phy"; > + reg = <0x5210000 0x10000>; > + clocks = <&ccu CLK_USB_PHY1>; > + resets = <&ccu RST_USB_PHY1>; > + #phy-cells = <0>; > + }; > + }; > -- > 2.26.3 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel