Re: [PATCH 3/4] PCI: ixp4xx: Add device tree bindings for IXP4xx

[Rob Herring <robh@kernel.org>]

On Mon, May 03, 2021 at 11:16:48PM +0200, Linus Walleij wrote:
> This adds device tree bindings for the Intel IXP4xx
> PCI controller which can be used as both host and
> option.
> 
> Cc: devicetree@vger.kernel.org
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Imre Kaloz <kaloz@openwrt.org>
> Cc: Krzysztof Halasa <khalasa@piap.pl>
> Cc: Zoltan HERPAI <wigyori@uid0.hu>
> Cc: Raylynn Knight <rayknight@me.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> PCI maintainers: mainly looking for a review and ACK (if
> you care about DT bindings) the patch will be merged
> through ARM SoC.
> ---
>  .../bindings/pci/intel,ixp4xx-pci.yaml        | 96 +++++++++++++++++++
>  1 file changed, 96 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
> new file mode 100644
> index 000000000000..5b6af2f5c2a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel IXP4xx PCI controller
> +
> +maintainers:
> +  - Linus Walleij <linus.walleij@linaro.org>
> +
> +description: PCI host controller found in the Intel IXP4xx SoC series.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - intel,ixp42x-pci
> +          - intel,ixp43x-pci
> +    description: The two supported variants are ixp42x and ixp43x,
> +      though more variants may exist.
> +
> +  reg:
> +    items:
> +      - description: IXP4xx-specific registers
> +
> +  ranges:
> +    maxItems: 2
> +    description: Typically one memory range of 64MB and one IO
> +      space range of 64KB.
> +
> +  dma-ranges:
> +    maxItems: 1
> +    description: The DMA range tells the PCI host which addresses
> +      the RAM is at. It can map only 64MB so if the RAM is bigger
> +      than 64MB the DMA access has to be restricted to these
> +      addresses.
> +
> +  "#interrupt-cells": true
> +
> +  interrupt-map: true
> +
> +  interrupt-map-mask:
> +    items:
> +      - const: 0xf800
> +      - const: 0
> +      - const: 0
> +      - const: 7
> +
> +required:
> +  - compatible
> +  - reg
> +  - ranges

Already required by pci-bus.yaml I think.

> +  - dma-ranges
> +  - "#interrupt-cells"
> +  - interrupt-map
> +  - interrupt-map-mask
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    pci@c0000000 {
> +      compatible = "intel,ixp43x-pci";
> +      reg = <0xc0000000 0x1000>;
> +      #address-cells = <3>;
> +      #size-cells = <2>;
> +      device_type = "pci";
> +      bus-range = <0x00 0xff>;
> +      status = "disabled";

Don't show status in examples. 

I've really got to come up with an examples only schema to check this.

Rob