From: Om Prakash Singh <omp@nvidia.com>
To: <vidyas@nvidia.com>, <lorenzo.pieralisi@arm.com>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, Om Prakash Singh <omp@nvidia.com>
Subject: [PATCH V1 2/5] PCI: tegra: Fix MSI-X programming
Date: Thu, 27 May 2021 13:16:11 +0530 [thread overview]
Message-ID: <20210527074614.49149-5-omp@nvidia.com> (raw)
In-Reply-To: <20210527074614.49149-1-omp@nvidia.com>
Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF
DBI register instead of higher order address. This patch fixes this
programming mistake.
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index c51d666c9d87..58fc2615014d 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1863,7 +1863,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
- val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
+ val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
ret = dw_pcie_ep_init_complete(ep);
--
2.17.1
next prev parent reply other threads:[~2021-05-27 7:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-27 7:46 [PATCH V1 0/6] Update pcie-tegra194 driver Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 0/5] " Om Prakash Singh
2021-05-27 7:46 ` [PATCH] PCI: tegra: Cleanup unused code Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 1/5] PCI: tegra: Fix handling BME_CHGED event Om Prakash Singh
2021-05-27 7:46 ` Om Prakash Singh [this message]
2021-05-27 7:46 ` [PATCH V1 3/5] PCI: tegra: Disable interrupts before entering L2 Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode Om Prakash Singh
2021-05-27 7:46 ` [PATCH V1 5/5] PCI: tegra: Cleanup unused code Om Prakash Singh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210527074614.49149-5-omp@nvidia.com \
--to=omp@nvidia.com \
--cc=bhelgaas@google.com \
--cc=jonathanh@nvidia.com \
--cc=kthota@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mmaddireddy@nvidia.com \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.