Re: [EXT] Re: pci mvebu issue (memory controller)

["Marek Behún" <kabel@kernel.org>]

On Wed, 2 Jun 2021 23:13:35 +0200
Pali Rohár <pali@kernel.org> wrote:

> > If the NICs are ordinary PCIe endpoints there must be *something* to
> > terminate the other end of the link.  Maybe it has some sort of
> > non-standard programming interface, but from a PCIe topology point of
> > view, it's a root port.
> > 
> > I don't think I can contribute anything to the stuff below.  It sounds
> > like there's some confusion about how to handle these root ports that
> > aren't exactly root ports.  That's really up to uboot and the mvebu
> > driver to figure out.  
> 
> Yes, I understand, it is non-standard and since beginning I'm also
> confused how this stuff work at all... And this is also reason why
> kernel emulates those root ports (via virtual PCIe bridge devices) to
> present "standard" topology.
> 
> Remaining question is: should really kernel filter that "memory
> controller" device and do not show it in linux PCIe device hierarchy?
> 

Bjorn,

this discussion has gone a little too complex.

The basic issue which Pali tries to solve can be recapitulated:
- there is a "memory controller" device on the "virtual" bus
- Linux' pci-mvebu driver hides this device
- we don't know what is the purpose of this device; it is visible even
  if there is no PCIe device connected
- Pali wants to know what is the purpose of this "memory controller"
  and whether this device should be hidden by Linux and U-Boot, as it
  currently is, or if the controller driver should expose this device

Marek