Re: [PATCH] cxl/component_regs: Fix offset

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Thu, 10 Jun 2021 22:11:13 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:

> The CXL.cache and CXL.mem registers begin after the CXL.io registers
> which occupy the first 0x1000 bytes. The current code wasn't setting
> this up properly for future users of the component registers. It was
> correct for the probing code however.
> 
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>

I guess we could have assumed that this offset was always form CXL_CM_OFFSET
but as that's a bit odd, this change makes sense.

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c
> index 92db02fe7aa8..c7f956fa3ada 100644
> --- a/drivers/cxl/core.c
> +++ b/drivers/cxl/core.c
> @@ -671,7 +671,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>  			length = 0x20 * decoder_cnt + 0x10;
>  
>  			map->hdm_decoder.valid = true;
> -			map->hdm_decoder.offset = offset;
> +			map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
>  			map->hdm_decoder.size = length;
>  			break;
>  		default: