From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE532C2B9F4 for ; Mon, 14 Jun 2021 17:39:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B4FE61350 for ; Mon, 14 Jun 2021 17:39:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B4FE61350 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pY4/atZKGCe8n6UQa7dd67onAsWq5ryqREUjToERkU4=; b=oSZOLeoRGvuZDd 17z11k4LRWrplmb5qjhKoJkeuAt5+imIFMtT7V2xJQPvgHxbEHgIBpA9IChm2JPk30WAlfFiyMJVQ GHDAfKifGR9rW+2X+jqYzr3mMf5k6S3GEzBLNKjyXVAfR36Hqk/6HAzF73bznamIH97FaSlOzhbqG gsweJUsSSNQ52B3cKw3JBWCV5uBaDQqwFy2KwZg5OVTQr4bn7UVZ/35FxnBEP+Fqo7u9LH8z18uPC FM5RyAa1b1UbZGh9b+yuEJXH8keDcxMn1EB50FBi6IVJVYRKcdt2ICu9EIRJbTaTXWhbH3retmGis +dsZlp4pHhWzyvo1mW3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqX7-00FSaa-P9; Mon, 14 Jun 2021 17:37:57 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lsqX2-00FSYp-BF for linux-arm-kernel@lists.infradead.org; Mon, 14 Jun 2021 17:37:53 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id EFF1261356; Mon, 14 Jun 2021 17:37:50 +0000 (UTC) Date: Mon, 14 Jun 2021 18:37:48 +0100 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Evgenii Stepanov , Linux ARM Subject: Re: [PATCH v2] arm64: mte: allow async MTE to be upgraded to sync on a per-CPU basis Message-ID: <20210614173748.GH30667@arm.com> References: <20210610021229.3605241-1-pcc@google.com> <20210611144915.GE8132@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210614_103752_444772_CCDEF7C4 X-CRM114-Status: GOOD ( 39.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 11, 2021 at 02:50:03PM -0700, Peter Collingbourne wrote: > On Fri, Jun 11, 2021 at 7:49 AM Catalin Marinas wrote: > > On Wed, Jun 09, 2021 at 07:12:29PM -0700, Peter Collingbourne wrote: > > > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > > > index 9df3feeee890..545ef900e7ce 100644 > > > --- a/arch/arm64/include/asm/processor.h > > > +++ b/arch/arm64/include/asm/processor.h > > > @@ -159,6 +159,7 @@ struct thread_struct { > > > #define SCTLR_USER_MASK \ > > > (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ > > > SCTLR_EL1_TCF0_MASK) > > > +#define SCTLR_USER_DYNAMIC_TCF (1ULL << 63) > > > > Even if you called it "USER", it still gives the impression that it's > > some real hardware bit. Who knows, in a few years time it may be > > allocated to a real feature. > > If bit 63 ends up being allocated to a bit that we want to allow > userspace control over then we can always just move this to another > bit. There are plenty to choose from that I don't think we will ever > allow user control over, e.g. EIS. > > > I also don't think this logic should be added to processor.[ch], just > > keep it within mte.c. > > > > So while it's convenient to add something to this field, given that it's > > shared with ptrauth, it's pretty fragile long term. I'd add the > > information about the dynamic mode to a different field. We could rename > > gcr_user_excl to mte_ctrl or something and store a few bits in there in > > addition to GCR_EL1.Excl (with corresponding masks etc.) > > I do take your point that it's somewhat awkward to commingle the SCTLR > bits and the dynamic TCF setting here, but I'm not sure that it's > overall better to move the bits to a renamed gcr_user_excl field. The > consequence would be that we need two copies of the TCF setting in > thread_struct and they will need to be kept in sync and leads to an > implicit ordering dependency between the code dealing with the two > fields on context switch. I haven't checked v3 yet but I don't understand what the ordering problem is. gcr_user_excl is also part of thread_struct and it shouldn't change while the thread is in the middle of a context switch. > We can make this more maintainable by adding a static_assert that > SCTLR_USER_DYNAMIC_TCF doesn't overlap with any of the bits in > SCTLR_USER_MASK, as I've done in v3. > > Let me know what you think and if you still disagree then I can try to > make this look more like you suggested. I just don't like adding software bits to the sctlr field. Who knows, we may need to add some more for MTE, maybe other features would do something similar and it's not maintainable. > > > +static ssize_t mte_upgrade_async_store(struct device *dev, > > > + struct device_attribute *attr, > > > + const char *buf, size_t count) > > > +{ > > > + ssize_t ret; > > > + u32 val; > > > + u64 tcf; > > > + > > > + ret = kstrtou32(buf, 0, &val); > > > + if (ret < 0) > > > + return ret; > > > + > > > + tcf = ((u64)val) << SCTLR_EL1_TCF0_SHIFT; > > > + if (tcf != SCTLR_EL1_TCF0_NONE && tcf != SCTLR_EL1_TCF0_SYNC && > > > + tcf != SCTLR_EL1_TCF0_ASYNC) > > > + return -EINVAL; > > > + > > > + device_lock(dev); > > > + per_cpu(mte_upgrade_async, dev->id) = tcf; > > > + > > > + ret = stop_machine(sync_sctlr, 0, cpumask_of(dev->id)); > > > > Do we really need a stop_machine() here? That's really heavy and we > > don't need such synchronisation. An smp_call_function() should do or > > just leave it until the next context switch on the corresponding CPUs. > > Looks like smp_call_function_single() should work here; done in v3. Why "single"? Don't you want this executed on all CPUs? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel