From: Leo Liang <ycliang@andestech.com>
To: Tom Rini <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>, <rick@andestech.com>, <bmeng.cn@gmail.com>
Subject: [PULL v3] u-boot-riscv/next
Date: Thu, 17 Jun 2021 11:27:58 +0800 [thread overview]
Message-ID: <20210617032758.GC16800@andestech.com> (raw)
Hi Tom,
Please pull u-boot-riscv/next into -next.
The following changes since commit 173c3bcd7dca47f1a8f7371a229681d20c7821cc:
Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next (2021-06-13 07:48:22 -0400)
are available in the Git repository at:
git@source.denx.de:u-boot/custodians/u-boot-riscv.git next
for you to fetch changes up to 446b4f346e006e2f87cebc9665c0139c7e17c905:
test: Add K210 PLL tests to sandbox defconfigs (2021-06-17 09:40:58 +0800)
CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7865
----------------------------------------------------------------
Sean Anderson (11):
clk: Allow force setting clock defaults before relocation
clk: k210: Rewrite to remove CCF
clk: k210: Move pll into the rest of the driver
clk: k210: Implement soc_clk_dump
clk: k210: Re-add support for setting rate
clk: k210: Don't set PLL rates if we are already at the correct rate
clk: k210: Remove bypass driver
clk: k210: Move k210 clock out of its own subdirectory
k210: dts: Set PLL1 to the same rate as PLL0
k210: Don't imply CCF
test: Add K210 PLL tests to sandbox defconfigs
MAINTAINERS | 4 +-
arch/riscv/dts/k210.dtsi | 2 +
board/sipeed/maix/Kconfig | 2 -
configs/sandbox64_defconfig | 2 +
configs/sandbox_defconfig | 2 +
configs/sandbox_flattree_defconfig | 2 +
configs/sipeed_maix_bitm_defconfig | 2 +-
drivers/clk/Kconfig | 14 +-
drivers/clk/Makefile | 2 +-
drivers/clk/clk-uclass.c | 27 +-
drivers/clk/clk_kendryte.c | 1320 +++++++++++++++++++++++++++++++
drivers/clk/kendryte/Kconfig | 12 -
drivers/clk/kendryte/Makefile | 1 -
drivers/clk/kendryte/bypass.c | 273 -------
drivers/clk/kendryte/clk.c | 668 ----------------
drivers/clk/kendryte/pll.c | 585 --------------
drivers/clk/rockchip/clk_rk3308.c | 2 +-
drivers/core/device.c | 2 +-
drivers/net/gmac_rockchip.c | 2 +-
include/clk.h | 30 +-
include/dt-bindings/clock/k210-sysctl.h | 94 ++-
include/kendryte/bypass.h | 31 -
include/kendryte/clk.h | 35 -
include/kendryte/pll.h | 34 -
24 files changed, 1437 insertions(+), 1711 deletions(-)
create mode 100644 drivers/clk/clk_kendryte.c
delete mode 100644 drivers/clk/kendryte/Kconfig
delete mode 100644 drivers/clk/kendryte/Makefile
delete mode 100644 drivers/clk/kendryte/bypass.c
delete mode 100644 drivers/clk/kendryte/clk.c
delete mode 100644 drivers/clk/kendryte/pll.c
delete mode 100644 include/kendryte/bypass.h
delete mode 100644 include/kendryte/clk.h
Best regards,
Leo
next reply other threads:[~2021-06-17 3:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 3:27 Leo Liang [this message]
2021-06-17 22:07 ` [PULL v3] u-boot-riscv/next Tom Rini
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