Re: [RFC PATH 2/2] gpio: starfive-jh7100: Add StarFive JH7100 GPIO driver

[kernel test robot <lkp@intel.com>]

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Hi Drew,

[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on robh/for-next]
[also build test ERROR on linux/master linus/master gpio/for-next v5.13 next-20210701]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Drew-Fustini/gpio-starfive-jh7100-Add-StarFive-JH7100-GPIO-bindings-and-driver/20210701-082306
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/450f9ef6a9c037df8e9d8b7e57d0de7b6bfd553e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Drew-Fustini/gpio-starfive-jh7100-Add-StarFive-JH7100-GPIO-bindings-and-driver/20210701-082306
        git checkout 450f9ef6a9c037df8e9d8b7e57d0de7b6bfd553e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpio/gpio-starfive-jh7100.c: In function 'starfive_gpio_probe':
>> drivers/gpio/gpio-starfive-jh7100.c:384:8: error: implicit declaration of function 'devm_request_irq'; did you mean 'can_request_irq'? [-Werror=implicit-function-declaration]
     384 |  ret = devm_request_irq(dev, irq, starfive_irq_handler, IRQF_SHARED,
         |        ^~~~~~~~~~~~~~~~
         |        can_request_irq
>> drivers/gpio/gpio-starfive-jh7100.c:384:57: error: 'IRQF_SHARED' undeclared (first use in this function)
     384 |  ret = devm_request_irq(dev, irq, starfive_irq_handler, IRQF_SHARED,
         |                                                         ^~~~~~~~~~~
   drivers/gpio/gpio-starfive-jh7100.c:384:57: note: each undeclared identifier is reported only once for each function it appears in
   cc1: some warnings being treated as errors


vim +384 drivers/gpio/gpio-starfive-jh7100.c

   327	
   328	static int starfive_gpio_probe(struct platform_device *pdev)
   329	{
   330		struct device *dev = &pdev->dev;
   331		struct starfive_gpio *chip;
   332		struct gpio_irq_chip *girq;
   333		struct resource *res;
   334		int irq, ret, ngpio;
   335	
   336		chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
   337		if (!chip)
   338			return -ENOMEM;
   339	
   340		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   341		chip->base = devm_ioremap_resource(dev, res);
   342		if (IS_ERR(chip->base)) {
   343			dev_err(dev, "failed to allocate device memory\n");
   344			return PTR_ERR(chip->base);
   345		}
   346	
   347		irq = platform_get_irq(pdev, 0);
   348		if (irq < 0) {
   349			dev_err(dev, "Cannot get IRQ resource\n");
   350			return irq;
   351		}
   352	
   353		raw_spin_lock_init(&chip->lock);
   354		chip->gc.direction_input = starfive_direction_input;
   355		chip->gc.direction_output = starfive_direction_output;
   356		chip->gc.get_direction = starfive_get_direction;
   357		chip->gc.get = starfive_get_value;
   358		chip->gc.set = starfive_set_value;
   359		chip->gc.base = 0;
   360		chip->gc.ngpio = MAX_GPIO;
   361		chip->gc.label = dev_name(dev);
   362		chip->gc.parent = dev;
   363		chip->gc.owner = THIS_MODULE;
   364	
   365		girq = &chip->gc.irq;
   366		girq->chip = &starfive_irqchip;
   367		girq->parent_handler = NULL;
   368		girq->num_parents = 0;
   369		girq->parents = NULL;
   370		girq->default_type = IRQ_TYPE_NONE;
   371		girq->handler = handle_simple_irq;
   372	
   373		ret = gpiochip_add_data(&chip->gc, chip);
   374		if (ret) {
   375			dev_err(dev, "gpiochip_add_data ret=%d!\n", ret);
   376			return ret;
   377		}
   378	
   379		/* Disable all GPIO interrupts before enabling parent interrupts */
   380		iowrite32(0, chip->base + GPIO_IE_HIGH);
   381		iowrite32(0, chip->base + GPIO_IE_LOW);
   382		chip->enabled = 0;
   383	
 > 384		ret = devm_request_irq(dev, irq, starfive_irq_handler, IRQF_SHARED,
   385				       dev_name(dev), chip);
   386		if (ret) {
   387			dev_err(dev, "IRQ handler registering failed (%d)\n", ret);
   388			return ret;
   389		}
   390	
   391		writel_relaxed(1, chip->base + GPIO_EN);
   392	
   393		dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", ngpio);
   394	
   395		return 0;
   396	}
   397	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

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