From: kernel test robot <lkp@intel.com>
To: kbuild@lists.01.org
Subject: drivers/gpu/drm/msm/adreno/a6xx_gmu.c:619 a6xx_gmu_rpmh_init() error: uninitialized symbol 'seqptr'.
Date: Fri, 02 Jul 2021 11:24:58 +0800 [thread overview]
Message-ID: <202107021153.rgaWRsql-lkp@intel.com> (raw)
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CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Jonathan Marek <jonathan@marek.ca>
CC: Rob Clark <robdclark@chromium.org>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 3dbdb38e286903ec220aaf1fb29a8d94297da246
commit: 64245fc55172a0083814c5be193bf4891b9096e2 drm/msm/a6xx: use AOP-initialized PDC for a650
date: 9 days ago
:::::: branch date: 3 hours ago
:::::: commit date: 9 days ago
config: arm-randconfig-m031-20210630 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/gpu/drm/msm/adreno/a6xx_gmu.c:619 a6xx_gmu_rpmh_init() error: uninitialized symbol 'seqptr'.
Old smatch warnings:
drivers/gpu/drm/msm/adreno/a6xx_gmu.c:1540 a6xx_gmu_init() warn: passing a valid pointer to 'PTR_ERR'
vim +/seqptr +619 drivers/gpu/drm/msm/adreno/a6xx_gmu.c
f8fc924e088ef4 Jordan Crouse 2018-08-08 505
f8fc924e088ef4 Jordan Crouse 2018-08-08 506 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
f8fc924e088ef4 Jordan Crouse 2018-08-08 507 const char *name);
f8fc924e088ef4 Jordan Crouse 2018-08-08 508
4b565ca5a2cbbb Jordan Crouse 2018-08-06 509 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
4b565ca5a2cbbb Jordan Crouse 2018-08-06 510 {
e812744c5f953c Sharat Masetty 2019-12-03 511 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
e812744c5f953c Sharat Masetty 2019-12-03 512 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
f8fc924e088ef4 Jordan Crouse 2018-08-08 513 struct platform_device *pdev = to_platform_device(gmu->dev);
f8fc924e088ef4 Jordan Crouse 2018-08-08 514 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
64245fc55172a0 Jonathan Marek 2021-06-08 515 void __iomem *seqptr;
02ef80c54e7cd7 Jonathan Marek 2020-04-23 516 uint32_t pdc_address_offset;
64245fc55172a0 Jonathan Marek 2021-06-08 517 bool pdc_in_aop = false;
f8fc924e088ef4 Jordan Crouse 2018-08-08 518
64245fc55172a0 Jonathan Marek 2021-06-08 519 if (!pdcptr)
f8fc924e088ef4 Jordan Crouse 2018-08-08 520 goto err;
f8fc924e088ef4 Jordan Crouse 2018-08-08 521
64245fc55172a0 Jonathan Marek 2021-06-08 522 if (adreno_is_a650(adreno_gpu))
64245fc55172a0 Jonathan Marek 2021-06-08 523 pdc_in_aop = true;
64245fc55172a0 Jonathan Marek 2021-06-08 524 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
02ef80c54e7cd7 Jonathan Marek 2020-04-23 525 pdc_address_offset = 0x30090;
02ef80c54e7cd7 Jonathan Marek 2020-04-23 526 else
02ef80c54e7cd7 Jonathan Marek 2020-04-23 527 pdc_address_offset = 0x30080;
02ef80c54e7cd7 Jonathan Marek 2020-04-23 528
64245fc55172a0 Jonathan Marek 2021-06-08 529 if (!pdc_in_aop) {
64245fc55172a0 Jonathan Marek 2021-06-08 530 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
64245fc55172a0 Jonathan Marek 2021-06-08 531 if (!seqptr)
64245fc55172a0 Jonathan Marek 2021-06-08 532 goto err;
64245fc55172a0 Jonathan Marek 2021-06-08 533 }
64245fc55172a0 Jonathan Marek 2021-06-08 534
4b565ca5a2cbbb Jordan Crouse 2018-08-06 535 /* Disable SDE clock gating */
02ef80c54e7cd7 Jonathan Marek 2020-04-23 536 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
4b565ca5a2cbbb Jordan Crouse 2018-08-06 537
4b565ca5a2cbbb Jordan Crouse 2018-08-06 538 /* Setup RSC PDC handshake for sleep and wakeup */
02ef80c54e7cd7 Jonathan Marek 2020-04-23 539 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 540 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 541 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 542 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 543 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 544 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 545 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 546 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 547 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 548 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 549 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
4b565ca5a2cbbb Jordan Crouse 2018-08-06 550
4b565ca5a2cbbb Jordan Crouse 2018-08-06 551 /* Load RSC sequencer uCode for sleep and wakeup */
02ef80c54e7cd7 Jonathan Marek 2020-04-23 552 if (adreno_is_a650(adreno_gpu)) {
02ef80c54e7cd7 Jonathan Marek 2020-04-23 553 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 554 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 555 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 556 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 557 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 558 } else {
02ef80c54e7cd7 Jonathan Marek 2020-04-23 559 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 561 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 562 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 564 }
4b565ca5a2cbbb Jordan Crouse 2018-08-06 565
64245fc55172a0 Jonathan Marek 2021-06-08 566 if (pdc_in_aop)
64245fc55172a0 Jonathan Marek 2021-06-08 567 goto setup_pdc;
64245fc55172a0 Jonathan Marek 2021-06-08 568
4b565ca5a2cbbb Jordan Crouse 2018-08-06 569 /* Load PDC sequencer uCode for power up and power down sequence */
f8fc924e088ef4 Jordan Crouse 2018-08-08 570 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
f8fc924e088ef4 Jordan Crouse 2018-08-08 571 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
f8fc924e088ef4 Jordan Crouse 2018-08-08 572 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 573 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
f8fc924e088ef4 Jordan Crouse 2018-08-08 574 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
4b565ca5a2cbbb Jordan Crouse 2018-08-06 575
4b565ca5a2cbbb Jordan Crouse 2018-08-06 576 /* Set TCS commands used by PDC sequence for low power modes */
f8fc924e088ef4 Jordan Crouse 2018-08-08 577 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
f8fc924e088ef4 Jordan Crouse 2018-08-08 578 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 579 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 580 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
f8fc924e088ef4 Jordan Crouse 2018-08-08 581 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
f8fc924e088ef4 Jordan Crouse 2018-08-08 582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
f8fc924e088ef4 Jordan Crouse 2018-08-08 583 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
f8fc924e088ef4 Jordan Crouse 2018-08-08 584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
f8fc924e088ef4 Jordan Crouse 2018-08-08 585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
e812744c5f953c Sharat Masetty 2019-12-03 586
f8fc924e088ef4 Jordan Crouse 2018-08-08 587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 588 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
f8fc924e088ef4 Jordan Crouse 2018-08-08 589 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
e812744c5f953c Sharat Masetty 2019-12-03 590
f8fc924e088ef4 Jordan Crouse 2018-08-08 591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
f8fc924e088ef4 Jordan Crouse 2018-08-08 592 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 593 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 594 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
f8fc924e088ef4 Jordan Crouse 2018-08-08 595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
f8fc924e088ef4 Jordan Crouse 2018-08-08 596 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
e812744c5f953c Sharat Masetty 2019-12-03 597
f8fc924e088ef4 Jordan Crouse 2018-08-08 598 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
f8fc924e088ef4 Jordan Crouse 2018-08-08 599 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 600 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
e812744c5f953c Sharat Masetty 2019-12-03 601 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
e812744c5f953c Sharat Masetty 2019-12-03 602 else
f8fc924e088ef4 Jordan Crouse 2018-08-08 603 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
f8fc924e088ef4 Jordan Crouse 2018-08-08 604 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
02ef80c54e7cd7 Jonathan Marek 2020-04-23 605 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
f8fc924e088ef4 Jordan Crouse 2018-08-08 606 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
4b565ca5a2cbbb Jordan Crouse 2018-08-06 607
4b565ca5a2cbbb Jordan Crouse 2018-08-06 608 /* Setup GPU PDC */
64245fc55172a0 Jonathan Marek 2021-06-08 609 setup_pdc:
f8fc924e088ef4 Jordan Crouse 2018-08-08 610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
f8fc924e088ef4 Jordan Crouse 2018-08-08 611 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
4b565ca5a2cbbb Jordan Crouse 2018-08-06 612
4b565ca5a2cbbb Jordan Crouse 2018-08-06 613 /* ensure no writes happen before the uCode is fully written */
4b565ca5a2cbbb Jordan Crouse 2018-08-06 614 wmb();
f8fc924e088ef4 Jordan Crouse 2018-08-08 615
f8fc924e088ef4 Jordan Crouse 2018-08-08 616 err:
5ca4a094ba7e13 Sean Paul 2019-05-23 617 if (!IS_ERR_OR_NULL(pdcptr))
a62fb211ad0c9e Sean Paul 2019-05-23 618 iounmap(pdcptr);
5ca4a094ba7e13 Sean Paul 2019-05-23 @619 if (!IS_ERR_OR_NULL(seqptr))
a62fb211ad0c9e Sean Paul 2019-05-23 620 iounmap(seqptr);
4b565ca5a2cbbb Jordan Crouse 2018-08-06 621 }
4b565ca5a2cbbb Jordan Crouse 2018-08-06 622
:::::: The code at line 619 was first introduced by commit
:::::: 5ca4a094ba7e1369363dcbcbde8baf06ddcdc2d1 drm/msm/a6xx: Check for ERR or NULL before iounmap
:::::: TO: Sean Paul <seanpaul@chromium.org>
:::::: CC: Sean Paul <seanpaul@chromium.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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