From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 227E5C07E99 for ; Mon, 5 Jul 2021 13:53:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D913E6144E for ; Mon, 5 Jul 2021 13:53:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D913E6144E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 54F6389BB0; Mon, 5 Jul 2021 13:53:27 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0287889BB0; Mon, 5 Jul 2021 13:53:25 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10035"; a="207154254" X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="207154254" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:25 -0700 X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="562596195" Received: from ricrossl-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.23.185]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:23 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Mon, 5 Jul 2021 14:53:06 +0100 Message-Id: <20210705135310.1502437-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: use consistent CPU mappings for pin_map users X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniel Vetter Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rm9yIGRpc2NyZXRlLCB1c2VycyBvZiBwaW5fbWFwKCkgbmVlZHMgdG8gb2JleSB0aGUgc2FtZSBy dWxlcyBhdCB0aGUgVFRNCmJhY2tlbmQsIHdoZXJlIHdlIG1hcCBzeXN0ZW0gb25seSBvYmplY3Rz IGFzIFdCLCBhbmQgZXZlcnl0aGluZyBlbHNlIGFzCldDLiBUaGUgc2ltcGxlc3QgZm9yIG5vdyBp cyB0byBqdXN0IGZvcmNlIHRoZSBjb3JyZWN0IG1hcHBpbmcgdHlwZSBhcwpwZXIgdGhlIG5ldyBy dWxlcyBmb3IgZGlzY3JldGUuCgpTdWdnZXN0ZWQtYnk6IFRob21hcyBIZWxsc3Ryw7ZtIDx0aG9t YXMuaGVsbHN0cm9tQGxpbnV4LmludGVsLmNvbT4KU2lnbmVkLW9mZi1ieTogTWF0dGhldyBBdWxk IDxtYXR0aGV3LmF1bGRAaW50ZWwuY29tPgpDYzogVGhvbWFzIEhlbGxzdHLDtm0gPHRob21hcy5o ZWxsc3Ryb21AbGludXguaW50ZWwuY29tPgpDYzogTWFhcnRlbiBMYW5raG9yc3QgPG1hYXJ0ZW4u bGFua2hvcnN0QGxpbnV4LmludGVsLmNvbT4KQ2M6IERhbmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0 ZXJAZmZ3bGwuY2g+CkNjOiBSYW1hbGluZ2FtIEMgPHJhbWFsaW5nYW0uY0BpbnRlbC5jb20+Ci0t LQogZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX29iamVjdC5jIHwgMzQgKysrKysr KysrKysrKysrKysrKysrKwogZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX29iamVj dC5oIHwgIDQgKysrCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9nZW0vaTkxNV9nZW1fcGFnZXMuYyAg fCAyMiArKysrKysrKysrKystLQogMyBmaWxlcyBjaGFuZ2VkLCA1OCBpbnNlcnRpb25zKCspLCAy IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2dlbS9pOTE1 X2dlbV9vYmplY3QuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2dlbS9pOTE1X2dlbV9vYmplY3Qu YwppbmRleCA1NDdjYzlkYWQ5MGQuLjlkYTdiMjg4YjdlZCAxMDA2NDQKLS0tIGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX29iamVjdC5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2dlbS9pOTE1X2dlbV9vYmplY3QuYwpAQCAtNjI1LDYgKzYyNSw0MCBAQCBpbnQgaTkxNV9n ZW1fb2JqZWN0X21pZ3JhdGUoc3RydWN0IGRybV9pOTE1X2dlbV9vYmplY3QgKm9iaiwKIAlyZXR1 cm4gb2JqLT5vcHMtPm1pZ3JhdGUob2JqLCBtcik7CiB9CiAKKy8qKgorICogaTkxNV9nZW1fb2Jq ZWN0X3BsYWNlbWVudF9wb3NzaWJsZSAtIENoZWNrIHdoZXRoZXIgdGhlIG9iamVjdCBjYW4gYmUK KyAqIHBsYWNlZCBhdCBjZXJ0YWluIG1lbW9yeSB0eXBlCisgKiBAb2JqOiBQb2ludGVyIHRvIHRo ZSBvYmplY3QKKyAqIEB0eXBlOiBUaGUgbWVtb3J5IHR5cGUgdG8gY2hlY2sKKyAqCisgKiBSZXR1 cm46IFRydWUgaWYgdGhlIG9iamVjdCBjYW4gYmUgcGxhY2VkIGluIEB0eXBlLiBGYWxzZSBvdGhl cndpc2UuCisgKi8KK2Jvb2wgaTkxNV9nZW1fb2JqZWN0X3BsYWNlbWVudF9wb3NzaWJsZShzdHJ1 Y3QgZHJtX2k5MTVfZ2VtX29iamVjdCAqb2JqLAorCQkJCQllbnVtIGludGVsX21lbW9yeV90eXBl IHR5cGUpCit7CisJdW5zaWduZWQgaW50IGk7CisKKwlpZiAoIW9iai0+bW0ubl9wbGFjZW1lbnRz KSB7CisJCXN3aXRjaCAodHlwZSkgeworCQljYXNlIElOVEVMX01FTU9SWV9MT0NBTDoKKwkJCXJl dHVybiBpOTE1X2dlbV9vYmplY3RfaGFzX2lvbWVtKG9iaik7CisJCWNhc2UgSU5URUxfTUVNT1JZ X1NZU1RFTToKKwkJCXJldHVybiBpOTE1X2dlbV9vYmplY3RfaGFzX3BhZ2VzKG9iaik7CisJCWRl ZmF1bHQ6CisJCQkvKiBJZ25vcmUgc3RvbGVuIGZvciBub3cgKi8KKwkJCUdFTV9CVUdfT04oMSk7 CisJCQlyZXR1cm4gZmFsc2U7CisJCX0KKwl9CisKKwlmb3IgKGkgPSAwOyBpIDwgb2JqLT5tbS5u X3BsYWNlbWVudHM7IGkrKykgeworCQlpZiAob2JqLT5tbS5wbGFjZW1lbnRzW2ldLT50eXBlID09 IHR5cGUpCisJCQlyZXR1cm4gdHJ1ZTsKKwl9CisKKwlyZXR1cm4gZmFsc2U7Cit9CisKIHZvaWQg aTkxNV9nZW1faW5pdF9fb2JqZWN0cyhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqaTkxNSkKIHsK IAlJTklUX1dPUksoJmk5MTUtPm1tLmZyZWVfd29yaywgX19pOTE1X2dlbV9mcmVlX3dvcmspOwpk aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX29iamVjdC5oIGIv ZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX29iamVjdC5oCmluZGV4IGQ0MjNkOGNh YzRmMi4uOGJlNGZhZGVlZTQ4IDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9nZW0v aTkxNV9nZW1fb2JqZWN0LmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2Vt X29iamVjdC5oCkBAIC0xMiw2ICsxMiw3IEBACiAjaW5jbHVkZSA8ZHJtL2RybV9kZXZpY2UuaD4K IAogI2luY2x1ZGUgImRpc3BsYXkvaW50ZWxfZnJvbnRidWZmZXIuaCIKKyNpbmNsdWRlICJpbnRl bF9tZW1vcnlfcmVnaW9uLmgiCiAjaW5jbHVkZSAiaTkxNV9nZW1fb2JqZWN0X3R5cGVzLmgiCiAj aW5jbHVkZSAiaTkxNV9nZW1fZ3R0LmgiCiAjaW5jbHVkZSAiaTkxNV9nZW1fd3cuaCIKQEAgLTYw Nyw2ICs2MDgsOSBAQCBib29sIGk5MTVfZ2VtX29iamVjdF9jYW5fbWlncmF0ZShzdHJ1Y3QgZHJt X2k5MTVfZ2VtX29iamVjdCAqb2JqLAogaW50IGk5MTVfZ2VtX29iamVjdF93YWl0X21pZ3JhdGlv bihzdHJ1Y3QgZHJtX2k5MTVfZ2VtX29iamVjdCAqb2JqLAogCQkJCSAgIHVuc2lnbmVkIGludCBm bGFncyk7CiAKK2Jvb2wgaTkxNV9nZW1fb2JqZWN0X3BsYWNlbWVudF9wb3NzaWJsZShzdHJ1Y3Qg ZHJtX2k5MTVfZ2VtX29iamVjdCAqb2JqLAorCQkJCQllbnVtIGludGVsX21lbW9yeV90eXBlIHR5 cGUpOworCiAjaWZkZWYgQ09ORklHX01NVV9OT1RJRklFUgogc3RhdGljIGlubGluZSBib29sCiBp OTE1X2dlbV9vYmplY3RfaXNfdXNlcnB0cihzdHJ1Y3QgZHJtX2k5MTVfZ2VtX29iamVjdCAqb2Jq KQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX3BhZ2VzLmMg Yi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9nZW0vaTkxNV9nZW1fcGFnZXMuYwppbmRleCBmMmY4NTBl MzFiOGUuLjgxMGExNTdhMThmOCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2Vt L2k5MTVfZ2VtX3BhZ2VzLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2Vt X3BhZ2VzLmMKQEAgLTMyMSw4ICszMjEsNyBAQCBzdGF0aWMgdm9pZCAqaTkxNV9nZW1fb2JqZWN0 X21hcF9wZm4oc3RydWN0IGRybV9pOTE1X2dlbV9vYmplY3QgKm9iaiwKIAlkbWFfYWRkcl90IGFk ZHI7CiAJdm9pZCAqdmFkZHI7CiAKLQlpZiAodHlwZSAhPSBJOTE1X01BUF9XQykKLQkJcmV0dXJu IEVSUl9QVFIoLUVOT0RFVik7CisJR0VNX0JVR19PTih0eXBlICE9IEk5MTVfTUFQX1dDKTsKIAog CWlmIChuX3BmbiA+IEFSUkFZX1NJWkUoc3RhY2spKSB7CiAJCS8qIFRvbyBiaWcgZm9yIHN0YWNr IC0tIGFsbG9jYXRlIHRlbXBvcmFyeSBhcnJheSBpbnN0ZWFkICovCkBAIC0zNzQsNiArMzczLDI1 IEBAIHZvaWQgKmk5MTVfZ2VtX29iamVjdF9waW5fbWFwKHN0cnVjdCBkcm1faTkxNV9nZW1fb2Jq ZWN0ICpvYmosCiAJfQogCUdFTV9CVUdfT04oIWk5MTVfZ2VtX29iamVjdF9oYXNfcGFnZXMob2Jq KSk7CiAKKwkvKgorCSAqIEZvciBkaXNjcmV0ZSBvdXIgQ1BVIG1hcHBpbmdzIG5lZWRzIHRvIGJl IGNvbnNpc3RlbnQgaW4gb3JkZXIgdG8KKwkgKiBmdW5jdGlvbiBjb3JyZWN0bHkgb24gIXg4Ni4g V2hlbiBtYXBwaW5nIHRoaW5ncyB0aHJvdWdoIFRUTSwgd2UgdXNlCisJICogdGhlIHNhbWUgcnVs ZXMgdG8gZGV0ZXJtaW5lIHRoZSBjYWNoaW5nIHR5cGUuCisJICoKKwkgKiBJbnRlcm5hbCB1c2Vy cyBvZiBsbWVtIGFyZSBhbHJlYWR5IGV4cGVjdGVkIHRvIGdldCB0aGlzIHJpZ2h0LCBzbyBubwor CSAqIGZ1ZGdpbmcgbmVlZGVkIHRoZXJlLgorCSAqLworCWlmIChpOTE1X2dlbV9vYmplY3RfcGxh Y2VtZW50X3Bvc3NpYmxlKG9iaiwgSU5URUxfTUVNT1JZX0xPQ0FMKSkgeworCQlpZiAodHlwZSAh PSBJOTE1X01BUF9XQyAmJiAhb2JqLT5tbS5uX3BsYWNlbWVudHMpIHsKKwkJCXB0ciA9IEVSUl9Q VFIoLUVOT0RFVik7CisJCQlnb3RvIGVycl91bnBpbjsKKwkJfQorCisJCXR5cGUgPSBJOTE1X01B UF9XQzsKKwl9IGVsc2UgaWYgKElTX0RHRlgodG9faTkxNShvYmotPmJhc2UuZGV2KSkpIHsKKwkJ dHlwZSA9IEk5MTVfTUFQX1dCOworCX0KKwogCXB0ciA9IHBhZ2VfdW5wYWNrX2JpdHMob2JqLT5t bS5tYXBwaW5nLCAmaGFzX3R5cGUpOwogCWlmIChwdHIgJiYgaGFzX3R5cGUgIT0gdHlwZSkgewog CQlpZiAocGlubmVkKSB7Ci0tIAoyLjI2LjMKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1B28C07E9C for ; Mon, 5 Jul 2021 13:53:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A2966144E for ; Mon, 5 Jul 2021 13:53:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A2966144E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07D6589CF8; Mon, 5 Jul 2021 13:53:28 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0287889BB0; Mon, 5 Jul 2021 13:53:25 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10035"; a="207154254" X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="207154254" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:25 -0700 X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="562596195" Received: from ricrossl-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.23.185]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:23 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 1/5] drm/i915: use consistent CPU mappings for pin_map users Date: Mon, 5 Jul 2021 14:53:06 +0100 Message-Id: <20210705135310.1502437-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Daniel Vetter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For discrete, users of pin_map() needs to obey the same rules at the TTM backend, where we map system only objects as WB, and everything else as WC. The simplest for now is to just force the correct mapping type as per the new rules for discrete. Suggested-by: Thomas Hellström Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Ramalingam C --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 34 ++++++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 +++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 22 ++++++++++++-- 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 547cc9dad90d..9da7b288b7ed 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -625,6 +625,40 @@ int i915_gem_object_migrate(struct drm_i915_gem_object *obj, return obj->ops->migrate(obj, mr); } +/** + * i915_gem_object_placement_possible - Check whether the object can be + * placed at certain memory type + * @obj: Pointer to the object + * @type: The memory type to check + * + * Return: True if the object can be placed in @type. False otherwise. + */ +bool i915_gem_object_placement_possible(struct drm_i915_gem_object *obj, + enum intel_memory_type type) +{ + unsigned int i; + + if (!obj->mm.n_placements) { + switch (type) { + case INTEL_MEMORY_LOCAL: + return i915_gem_object_has_iomem(obj); + case INTEL_MEMORY_SYSTEM: + return i915_gem_object_has_pages(obj); + default: + /* Ignore stolen for now */ + GEM_BUG_ON(1); + return false; + } + } + + for (i = 0; i < obj->mm.n_placements; i++) { + if (obj->mm.placements[i]->type == type) + return true; + } + + return false; +} + void i915_gem_init__objects(struct drm_i915_private *i915) { INIT_WORK(&i915->mm.free_work, __i915_gem_free_work); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index d423d8cac4f2..8be4fadeee48 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -12,6 +12,7 @@ #include #include "display/intel_frontbuffer.h" +#include "intel_memory_region.h" #include "i915_gem_object_types.h" #include "i915_gem_gtt.h" #include "i915_gem_ww.h" @@ -607,6 +608,9 @@ bool i915_gem_object_can_migrate(struct drm_i915_gem_object *obj, int i915_gem_object_wait_migration(struct drm_i915_gem_object *obj, unsigned int flags); +bool i915_gem_object_placement_possible(struct drm_i915_gem_object *obj, + enum intel_memory_type type); + #ifdef CONFIG_MMU_NOTIFIER static inline bool i915_gem_object_is_userptr(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index f2f850e31b8e..810a157a18f8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -321,8 +321,7 @@ static void *i915_gem_object_map_pfn(struct drm_i915_gem_object *obj, dma_addr_t addr; void *vaddr; - if (type != I915_MAP_WC) - return ERR_PTR(-ENODEV); + GEM_BUG_ON(type != I915_MAP_WC); if (n_pfn > ARRAY_SIZE(stack)) { /* Too big for stack -- allocate temporary array instead */ @@ -374,6 +373,25 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, } GEM_BUG_ON(!i915_gem_object_has_pages(obj)); + /* + * For discrete our CPU mappings needs to be consistent in order to + * function correctly on !x86. When mapping things through TTM, we use + * the same rules to determine the caching type. + * + * Internal users of lmem are already expected to get this right, so no + * fudging needed there. + */ + if (i915_gem_object_placement_possible(obj, INTEL_MEMORY_LOCAL)) { + if (type != I915_MAP_WC && !obj->mm.n_placements) { + ptr = ERR_PTR(-ENODEV); + goto err_unpin; + } + + type = I915_MAP_WC; + } else if (IS_DGFX(to_i915(obj->base.dev))) { + type = I915_MAP_WB; + } + ptr = page_unpack_bits(obj->mm.mapping, &has_type); if (ptr && has_type != type) { if (pinned) { -- 2.26.3