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header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1200988DD0; Mon, 5 Jul 2021 13:53:32 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id D73F789D4A; Mon, 5 Jul 2021 13:53:30 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10035"; a="207154278" X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="207154278" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:30 -0700 X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="562596212" Received: from ricrossl-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.23.185]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:28 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Mon, 5 Jul 2021 14:53:08 +0100 Message-Id: <20210705135310.1502437-3-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210705135310.1502437-1-matthew.auld@intel.com> References: <20210705135310.1502437-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/5] drm/i915/uapi: reject caching ioctls for discrete X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , dri-devel@lists.freedesktop.org, Kenneth Graunke , Daniel Vetter Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" SXQncyBhIG5vb3Agb24gREcxLCBhbmQgaW4gdGhlIGZ1dHVyZSB3aGVuIG5lZWQgdG8gc3VwcG9y dCBvdGhlciBkZXZpY2VzCndoaWNoIGxldCB1cyBjb250cm9sIHRoZSBjb2hlcmVuY3ksIHRoZW4g aXQgc2hvdWxkIGJlIGFuIGltbXV0YWJsZQpjcmVhdGlvbiB0aW1lIHByb3BlcnR5IGZvciB0aGUg Qk8uIFRoaXMgd2lsbCBsaWtlbHkgYmUgY29udHJvbGxlZAp0aHJvdWdoIGEgbmV3IGdlbV9jcmVh dGVfZXh0IGV4dGVuc2lvbi4KCnYyOiBhZGQgc29tZSBrZXJuZWwgZG9jIGZvciB0aGUgZGlzY3Jl dGUgY2hhbmdlcywgYW5kIGRvY3VtZW50IHRoZQogICAgaW1wbGljaXQgcnVsZXMKClN1Z2dlc3Rl ZC1ieTogRGFuaWVsIFZldHRlciA8ZGFuaWVsQGZmd2xsLmNoPgpTaWduZWQtb2ZmLWJ5OiBNYXR0 aGV3IEF1bGQgPG1hdHRoZXcuYXVsZEBpbnRlbC5jb20+CkNjOiBUaG9tYXMgSGVsbHN0csO2bSA8 dGhvbWFzLmhlbGxzdHJvbUBsaW51eC5pbnRlbC5jb20+CkNjOiBNYWFydGVuIExhbmtob3JzdCA8 bWFhcnRlbi5sYW5raG9yc3RAbGludXguaW50ZWwuY29tPgpDYzogVHZydGtvIFVyc3VsaW4gPHR2 cnRrby51cnN1bGluQGxpbnV4LmludGVsLmNvbT4KQ2M6IEpvcmRhbiBKdXN0ZW4gPGpvcmRhbi5s Lmp1c3RlbkBpbnRlbC5jb20+CkNjOiBLZW5uZXRoIEdyYXVua2UgPGtlbm5ldGhAd2hpdGVjYXBl Lm9yZz4KQ2M6IEphc29uIEVrc3RyYW5kIDxqYXNvbkBqbGVrc3RyYW5kLm5ldD4KQ2M6IERhbmll bCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+CkNjOiBSYW1hbGluZ2FtIEMgPHJhbWFs aW5nYW0uY0BpbnRlbC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2Vt X2RvbWFpbi5jIHwgIDYgKysrKysKIGluY2x1ZGUvdWFwaS9kcm0vaTkxNV9kcm0uaCAgICAgICAg ICAgICAgICB8IDI5ICsrKysrKysrKysrKysrKysrKysrKy0KIDIgZmlsZXMgY2hhbmdlZCwgMzQg aW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2dlbS9pOTE1X2dlbV9kb21haW4uYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2dlbS9p OTE1X2dlbV9kb21haW4uYwppbmRleCA3ZDE0MDBiMTM0MjkuLjQzMDA0YmVmNTVjYiAxMDA2NDQK LS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ2VtL2k5MTVfZ2VtX2RvbWFpbi5jCisrKyBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2dlbS9pOTE1X2dlbV9kb21haW4uYwpAQCAtMjY4LDYgKzI2OCw5 IEBAIGludCBpOTE1X2dlbV9nZXRfY2FjaGluZ19pb2N0bChzdHJ1Y3QgZHJtX2RldmljZSAqZGV2 LCB2b2lkICpkYXRhLAogCXN0cnVjdCBkcm1faTkxNV9nZW1fb2JqZWN0ICpvYmo7CiAJaW50IGVy ciA9IDA7CiAKKwlpZiAoSVNfREdGWCh0b19pOTE1KGRldikpKQorCQlyZXR1cm4gLUVOT0RFVjsK KwogCXJjdV9yZWFkX2xvY2soKTsKIAlvYmogPSBpOTE1X2dlbV9vYmplY3RfbG9va3VwX3JjdShm aWxlLCBhcmdzLT5oYW5kbGUpOwogCWlmICghb2JqKSB7CkBAIC0zMDMsNiArMzA2LDkgQEAgaW50 IGk5MTVfZ2VtX3NldF9jYWNoaW5nX2lvY3RsKHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIHZvaWQg KmRhdGEsCiAJZW51bSBpOTE1X2NhY2hlX2xldmVsIGxldmVsOwogCWludCByZXQgPSAwOwogCisJ aWYgKElTX0RHRlgoaTkxNSkpCisJCXJldHVybiAtRU5PREVWOworCiAJc3dpdGNoIChhcmdzLT5j YWNoaW5nKSB7CiAJY2FzZSBJOTE1X0NBQ0hJTkdfTk9ORToKIAkJbGV2ZWwgPSBJOTE1X0NBQ0hF X05PTkU7CmRpZmYgLS1naXQgYS9pbmNsdWRlL3VhcGkvZHJtL2k5MTVfZHJtLmggYi9pbmNsdWRl L3VhcGkvZHJtL2k5MTVfZHJtLmgKaW5kZXggZDEzYzZjNWZhZDA0Li5hNGZhY2VlYjhjMzIgMTAw NjQ0Ci0tLSBhL2luY2x1ZGUvdWFwaS9kcm0vaTkxNV9kcm0uaAorKysgYi9pbmNsdWRlL3VhcGkv ZHJtL2k5MTVfZHJtLmgKQEAgLTEzNzIsNyArMTM3MiwzNCBAQCBzdHJ1Y3QgZHJtX2k5MTVfZ2Vt X2J1c3kgewogICogcmVxdWlyZSB1bmJpbmRpbmcgdGhlIG9iamVjdCBmcm9tIHRoZSBHVFQgZmly c3QsIGlmIGl0cyBjdXJyZW50IGNhY2hpbmcgdmFsdWUKICAqIGRvZXNuJ3QgbWF0Y2guCiAgKgot ICoKKyAqIE5vdGUgdGhhdCB0aGlzIGFsbCBjaGFuZ2VzIG9uIGRpc2NyZXRlIHBsYXRmb3Jtcywg c3RhcnRpbmcgZnJvbSBERzEsIHRoZQorICogc2V0L2dldCBjYWNoaW5nIGlzIG5vIGxvbmdlciBz dXBwb3J0ZWQsIGFuZCBpcyBub3cgcmVqZWN0ZWQuICBJbnN0ZWFkIHRoZSBDUFUKKyAqIGNhY2hp bmcgYXR0cmlidXRlcyhXQiB2cyBXQykgd2lsbCBiZWNvbWUgYW4gaW1tdXRhYmxlIGNyZWF0aW9u IHRpbWUgcHJvcGVydHkKKyAqIGZvciB0aGUgb2JqZWN0LCBhbG9uZyB3aXRoIHRoZSBHVFQgY2Fj aGluZyBsZXZlbC4gRm9yIG5vdyB3ZSBkb24ndCBleHBvc2UgYW55CisgKiBuZXcgdUFQSSBmb3Ig dGhpcywgaW5zdGVhZCBvbiBERzEgdGhpcyBpcyBhbGwgaW1wbGljaXQsIGFsdGhvdWdoIHRoaXMg bGFyZ2VseQorICogc2hvdWxkbid0IG1hdHRlciBzaW5jZSBERzEgaXMgY29oZXJlbnQgYnkgZGVm YXVsdCh3aXRob3V0IGFueSB3YXkgb2YKKyAqIGNvbnRyb2xsaW5nIGl0KS4KKyAqCisgKiBJbXBs aWNpdCBjYWNoaW5nIHJ1bGVzLCBzdGFydGluZyBmcm9tIERHMToKKyAqCisgKiAgICAgLSBJZiBh bnkgb2YgdGhlIG9iamVjdCBwbGFjZW1lbnRzIChzZWUgJmRybV9pOTE1X2dlbV9jcmVhdGVfZXh0 X21lbW9yeV9yZWdpb25zKQorICogICAgICAgY29udGFpbiBJOTE1X01FTU9SWV9DTEFTU19ERVZJ Q0UgdGhlbiB0aGUgb2JqZWN0IHdpbGwgYmUgYWxsb2NhdGVkIGFuZAorICogICAgICAgbWFwcGVk IGFzIHdyaXRlLWNvbWJpbmVkIG9ubHkuCisgKgorICogICAgIC0gRXZlcnl0aGluZyBlbHNlIGlz IGFsd2F5cyBhbGxvY2F0ZWQgYW5kIG1hcHBlZCBhcyB3cml0ZS1iYWNrLCB3aXRoIHRoZQorICog ICAgICAgZ3VhcmFudGVlIHRoYXQgZXZlcnl0aGluZyBpcyBhbHNvIGNvaGVyZW50IHdpdGggdGhl IEdQVS4KKyAqCisgKiBOb3RlIHRoYXQgdGhpcyBpcyBsaWtlbHkgdG8gY2hhbmdlIGluIHRoZSBm dXR1cmUgYWdhaW4sIHdoZXJlIHdlIG1pZ2h0IG5lZWQKKyAqIG1vcmUgZmxleGliaWxpdHkgb24g ZnV0dXJlIGRldmljZXMsIHNvIG1ha2luZyB0aGlzIGFsbCBleHBsaWNpdCBhcyBwYXJ0IG9mIGEK KyAqIG5ldyAmZHJtX2k5MTVfZ2VtX2NyZWF0ZV9leHQgZXh0ZW5zaW9uIGlzIHByb2JhYmxlLgor ICoKKyAqIFNpZGUgbm90ZTogUGFydCBvZiB0aGUgcmVhc29uIGZvciB0aGlzIGlzIHRoYXQgY2hh bmdpbmcgdGhlIGF0LWFsbG9jYXRpb24tdGltZSBDUFUKKyAqIGNhY2hpbmcgYXR0cmlidXRlcyBm b3IgdGhlIHBhZ2VzIG1pZ2h0IGJlIHJlcXVpcmVkKGFuZCBpcyBleHBlbnNpdmUpIGlmIHdlCisg KiBuZWVkIHRvIHRoZW4gQ1BVIG1hcCB0aGUgcGFnZXMgbGF0ZXIgd2l0aCBkaWZmZXJlbnQgY2Fj aGluZyBhdHRyaWJ1dGVzLiBUaGlzCisgKiBpbmNvbnNpc3RlbnQgY2FjaGluZyBiZWhhdmlvdXIs IHdoaWxlIHN1cHBvcnRlZCBvbiB4ODYsIGlzIG5vdCB1bml2ZXJzYWxseQorICogc3VwcG9ydGVk IG9uIG90aGVyIGFyY2hpdGVjdHVyZXMuIFNvIGZvciBzaW1wbGljaXR5IHdlIG9wdCBmb3Igc2V0 dGluZworICogZXZlcnl0aGluZyBhdCBjcmVhdGlvbiB0aW1lLCB3aGlsc3QgYWxzbyBtYWtpbmcg aXQgaW1tdXRhYmxlLCBvbiBkaXNjcmV0ZQorICogcGxhdGZvcm1zLgogICovCiBzdHJ1Y3QgZHJt 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certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1364B6144E for ; Mon, 5 Jul 2021 13:53:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1364B6144E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF21D88D1E; Mon, 5 Jul 2021 13:53:31 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id D73F789D4A; Mon, 5 Jul 2021 13:53:30 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10035"; a="207154278" X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="207154278" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:30 -0700 X-IronPort-AV: E=Sophos;i="5.83,325,1616482800"; d="scan'208";a="562596212" Received: from ricrossl-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.23.185]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2021 06:53:28 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 3/5] drm/i915/uapi: reject caching ioctls for discrete Date: Mon, 5 Jul 2021 14:53:08 +0100 Message-Id: <20210705135310.1502437-3-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210705135310.1502437-1-matthew.auld@intel.com> References: <20210705135310.1502437-1-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Jason Ekstrand , Tvrtko Ursulin , Jordan Justen , dri-devel@lists.freedesktop.org, Kenneth Graunke , Daniel Vetter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It's a noop on DG1, and in the future when need to support other devices which let us control the coherency, then it should be an immutable creation time property for the BO. This will likely be controlled through a new gem_create_ext extension. v2: add some kernel doc for the discrete changes, and document the implicit rules Suggested-by: Daniel Vetter Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Maarten Lankhorst Cc: Tvrtko Ursulin Cc: Jordan Justen Cc: Kenneth Graunke Cc: Jason Ekstrand Cc: Daniel Vetter Cc: Ramalingam C --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 6 +++++ include/uapi/drm/i915_drm.h | 29 +++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 7d1400b13429..43004bef55cb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -268,6 +268,9 @@ int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, struct drm_i915_gem_object *obj; int err = 0; + if (IS_DGFX(to_i915(dev))) + return -ENODEV; + rcu_read_lock(); obj = i915_gem_object_lookup_rcu(file, args->handle); if (!obj) { @@ -303,6 +306,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, enum i915_cache_level level; int ret = 0; + if (IS_DGFX(i915)) + return -ENODEV; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index d13c6c5fad04..a4faceeb8c32 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1372,7 +1372,34 @@ struct drm_i915_gem_busy { * require unbinding the object from the GTT first, if its current caching value * doesn't match. * - * + * Note that this all changes on discrete platforms, starting from DG1, the + * set/get caching is no longer supported, and is now rejected. Instead the CPU + * caching attributes(WB vs WC) will become an immutable creation time property + * for the object, along with the GTT caching level. For now we don't expose any + * new uAPI for this, instead on DG1 this is all implicit, although this largely + * shouldn't matter since DG1 is coherent by default(without any way of + * controlling it). + * + * Implicit caching rules, starting from DG1: + * + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions) + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and + * mapped as write-combined only. + * + * - Everything else is always allocated and mapped as write-back, with the + * guarantee that everything is also coherent with the GPU. + * + * Note that this is likely to change in the future again, where we might need + * more flexibility on future devices, so making this all explicit as part of a + * new &drm_i915_gem_create_ext extension is probable. + * + * Side note: Part of the reason for this is that changing the at-allocation-time CPU + * caching attributes for the pages might be required(and is expensive) if we + * need to then CPU map the pages later with different caching attributes. This + * inconsistent caching behaviour, while supported on x86, is not universally + * supported on other architectures. So for simplicity we opt for setting + * everything at creation time, whilst also making it immutable, on discrete + * platforms. */ struct drm_i915_gem_caching { /** -- 2.26.3