From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 908BBC07E99 for ; Mon, 5 Jul 2021 14:19:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5171761416 for ; Mon, 5 Jul 2021 14:19:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5171761416 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7EstY2S6d7UyMct8w6Ssj6rMwbtHhazvFgQ4JRDB+u4=; b=UBQlVnnJb1CQNl 1rVwa9cuH1HknF/S+b4lrOY5+CzzkW5I8xefBO9bkkyCLdXXxImx0rDDBXa2M9Pu+pr90bxSWaxof VAU/xUR9KzBnIdjEy97sOTZj3o5trd2q+QIi/MzZig7l+vGhKVLj/Cnr/ZtyigZIR6KpsT3Egx1h/ ggVEdRLrmWUzmEe0+AHyECspYHHSGgBDlliNtJdGXNsLtl9GotUIQB1OMZaH2kY2m223p/mC9dHcR lQ0lo5Hka4aHDnYrK2afXCqjUXq8tGd40NSaeQn8d9yXneKDBBDfEf4VF5tPC69PP81p9s3oNmOTd 2j5KOUYc6eX/Ria3iqkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m0PPs-0095xg-IN; Mon, 05 Jul 2021 14:17:44 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m0PPo-0095xD-E7 for linux-arm-kernel@lists.infradead.org; Mon, 05 Jul 2021 14:17:41 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id B601F6193E; Mon, 5 Jul 2021 14:17:38 +0000 (UTC) Date: Mon, 5 Jul 2021 15:17:35 +0100 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Andrey Konovalov , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , Linux ARM Subject: Re: [PATCH] arm64: mte: switch GCR_EL1 on task switch rather than entry/exit Message-ID: <20210705141735.GB4799@arm.com> References: <20210702031922.1291398-1-pcc@google.com> <20210702174450.GC685@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210705_071740_545944_FE9B54A8 X-CRM114-Status: GOOD ( 19.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 02, 2021 at 11:39:33AM -0700, Peter Collingbourne wrote: > On Fri, Jul 2, 2021 at 10:44 AM Catalin Marinas wrote: > > On Thu, Jul 01, 2021 at 08:19:22PM -0700, Peter Collingbourne wrote: > > > Accessing GCR_EL1 and issuing an ISB can be expensive on some > > > microarchitectures. To avoid taking this performance hit on every > > > kernel entry/exit, switch GCR_EL1 on task switch rather than > > > entry/exit. > > > > Is it the ISB that's causing issues or the MRS/MSR as well? I think we > > can avoid the ISB when PtrAuth is enabled by shuffling the entry code a > > bit. We can also simplify the mte_set_gcr macro to avoid an MRS. > > This was the first thing that I tried on our hardware: > > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index 7312eafec946..8699ab28a924 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -204,7 +204,6 @@ alternative_else_nop_endif > ldr_l \tmp, gcr_kernel_excl > > mte_set_gcr \tmp, \tmp2 > - isb > 1: > #endif > .endm > @@ -277,13 +276,13 @@ alternative_if ARM64_HAS_ADDRESS_AUTH > orr x0, x0, SCTLR_ELx_ENIA > msr sctlr_el1, x0 > 2: > - isb > alternative_else_nop_endif > #endif > > apply_ssbd 1, x22, x23 > > mte_set_kernel_gcr x22, x23 > + isb > > scs_load tsk, x20 > .else > > However, on most of the cores this led to only around half of the > performance improvement of the patch that I sent. Which is somewhat > surprising, but it is what it is. BTW, can you also modify mte_set_kernel_gcr to only do a write to the GCR_EL1 register rather than a read-modify-write? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel