diff for duplicates of <20210729181533.GV8018@packtop> diff --git a/a/1.txt b/N1/1.txt index 4cd1ca7..1eb9e7d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -11,11 +11,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> >> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> >> > --- ->> > MAINTAINERS?????????????????????????? |?? 9 + ->> > drivers/peci/Kconfig????????????????? |?? 6 + ->> > drivers/peci/Makefile???????????????? |?? 3 + ->> > drivers/peci/controller/Kconfig?????? |? 12 + ->> > drivers/peci/controller/Makefile????? |?? 3 + +>> > MAINTAINERS | 9 + +>> > drivers/peci/Kconfig | 6 + +>> > drivers/peci/Makefile | 3 + +>> > drivers/peci/controller/Kconfig | 12 + +>> > drivers/peci/controller/Makefile | 3 + >> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++ >> > 6 files changed, 534 insertions(+) >> > create mode 100644 drivers/peci/controller/Kconfig @@ -26,30 +26,30 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > index 47411e2b6336..4ba874afa2fa 100644 >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS ->> > @@ -2865,6 +2865,15 @@ S:???????Maintained ->> > F:??????Documentation/hwmon/asc7621.rst ->> > F:??????drivers/hwmon/asc7621.c +>> > @@ -2865,6 +2865,15 @@ S: Maintained +>> > F: Documentation/hwmon/asc7621.rst +>> > F: drivers/hwmon/asc7621.c >> > >> > +ASPEED PECI CONTROLLER ->> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com> ->> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> ->> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) ->> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers) ->> > +S:?????Supported ->> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml ->> > +F:?????drivers/peci/controller/peci-aspeed.c +>> > +M: Iwona Winiarska <iwona.winiarska@intel.com> +>> > +M: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> +>> > +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +>> > +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +>> > +S: Supported +>> > +F: Documentation/devicetree/bindings/peci/peci-aspeed.yaml +>> > +F: drivers/peci/controller/peci-aspeed.c >> > + >> > ASPEED PINCTRL DRIVERS ->> > M:??????Andrew Jeffery <andrew@aj.id.au> ->> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) +>> > M: Andrew Jeffery <andrew@aj.id.au> +>> > L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) >> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig >> > index 601cc3c3c852..0d0ee8009713 100644 >> > --- a/drivers/peci/Kconfig >> > +++ b/drivers/peci/Kconfig >> > @@ -12,3 +12,9 @@ menuconfig PECI >> > ->> > ????????? This support is also available as a module. If so, the module ->> > ????????? will be called peci. +>> > This support is also available as a module. If so, the module +>> > will be called peci. >> > + >> > +if PECI >> > + @@ -77,15 +77,15 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + >> > +config PECI_ASPEED ->> > +???????tristate "ASPEED PECI support" ->> > +???????depends on ARCH_ASPEED || COMPILE_TEST ->> > +???????depends on OF ->> > +???????depends on HAS_IOMEM ->> > +???????help ->> > +???????? Enable this driver if you want to support ASPEED PECI controller. ->> > + ->> > +???????? This driver can be also build as a module. If so, the module ->> > +???????? will be called peci-aspeed. +>> > + tristate "ASPEED PECI support" +>> > + depends on ARCH_ASPEED || COMPILE_TEST +>> > + depends on OF +>> > + depends on HAS_IOMEM +>> > + help +>> > + Enable this driver if you want to support ASPEED PECI controller. +>> > + +>> > + This driver can be also build as a module. If so, the module +>> > + will be called peci-aspeed. >> > diff --git a/drivers/peci/controller/Makefile >> > b/drivers/peci/controller/Makefile >> > new file mode 100644 @@ -95,7 +95,7 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > @@ -0,0 +1,3 @@ >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + ->> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o +>> > +obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o >> > diff --git a/drivers/peci/controller/peci-aspeed.c >> > b/drivers/peci/controller/peci-aspeed.c >> > new file mode 100644 @@ -124,11 +124,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > + >> > +/* ASPEED PECI Registers */ >> > +/* Control Register */ ->> > +#define ASPEED_PECI_CTRL???????????????????????0x00 ->> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13) +>> > +#define ASPEED_PECI_CTRL 0x00 +>> > +#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_MASK GENMASK(13, 12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_COUNT BIT(12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_DBG BIT(13) >> >> Nitpick: might be nice to keep things in a consistent descending order >> here (13 then 12). @@ -136,17 +136,17 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >Sure, I'll change it in v2. > ->> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11) +>> > +#define ASPEED_PECI_CTRL_CLK_SOURCE_MASK BIT(11) >> >> _MASK suffix seems out of place on this one. > >Ack. > >> ->> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6) ->> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5) +>> > +#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8) +>> > +#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7) +>> > +#define ASPEED_PECI_CTRL_INVERT_IN BIT(6) +>> > +#define ASPEED_PECI_CTRL_BUS_CONTENT_EN BIT(5) >> >> It *is* already kind of a long macro name, but abbreviating "contention" >> to "content" seems a bit confusing; I'd suggest keeping the extra three @@ -156,29 +156,29 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >You're right - it'll be renamed properly in v2. > ->> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4) ->> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0) +>> > +#define ASPEED_PECI_CTRL_PECI_EN BIT(4) +>> > +#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0) >> > + >> > +/* Timing Negotiation Register */ ->> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04 ->> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0) +>> > +#define ASPEED_PECI_TIMING_NEGOTIATION 0x04 +>> > +#define ASPEED_PECI_TIMING_MESSAGE_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TIMING_ADDRESS_MASK GENMASK(7, 0) >> > + >> > +/* Command Register */ ->> > +#define ASPEED_PECI_CMD????????????????????????????????0x08 ->> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31) ->> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24) ->> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3 ->> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\ ->> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) ->> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0) +>> > +#define ASPEED_PECI_CMD 0x08 +>> > +#define ASPEED_PECI_CMD_PIN_MON BIT(31) +>> > +#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24) +>> > +#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3 +>> > +#define ASPEED_PECI_CMD_IDLE_MASK \ +>> > + (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) +>> > +#define ASPEED_PECI_CMD_FIRE BIT(0) >> > + >> > +/* Read/Write Length Register */ ->> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c ->> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31) ->> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0) +>> > +#define ASPEED_PECI_RW_LENGTH 0x0c +>> > +#define ASPEED_PECI_AW_FCS_EN BIT(31) +>> > +#define ASPEED_PECI_READ_LEN_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_WRITE_LEN_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TAGET_ADDR_MASK GENMASK(7, 0) >> >> s/TAGET/TARGET/ >> @@ -187,116 +187,116 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >> > + >> > +/* Expected FCS Data Register */ ->> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10 ->> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_EXP_FCS 0x10 +>> > +#define ASPEED_PECI_EXP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_EXP_AW_FCS_AUTO_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_EXP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Captured FCS Data Register */ ->> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14 ->> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_CAP_FCS 0x14 +>> > +#define ASPEED_PECI_CAP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_CAP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Interrupt Register */ ->> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18 ->> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30) ->> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0 ->> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1 ->> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2 ->> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0) ->> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4) ->> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3) +>> > +#define ASPEED_PECI_INT_CTRL 0x18 +>> > +#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30) +>> > +#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0 +>> > +#define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO 1 +>> > +#define ASPEED_PECI_MESSAGE_NEGO 2 +>> > +#define ASPEED_PECI_INT_MASK GENMASK(4, 0) +>> > +#define ASPEED_PECI_INT_BUS_TIMEOUT BIT(4) +>> > +#define ASPEED_PECI_INT_BUS_CONNECT BIT(3) >> >> s/CONNECT/CONTENTION/ > >Ack. > >> ->> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2) ->> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1) ->> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0) +>> > +#define ASPEED_PECI_INT_W_FCS_BAD BIT(2) +>> > +#define ASPEED_PECI_INT_W_FCS_ABORT BIT(1) +>> > +#define ASPEED_PECI_INT_CMD_DONE BIT(0) >> > + >> > +/* Interrupt Status Register */ ->> > +#define ASPEED_PECI_INT_STS????????????????????0x1c ->> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16) ->> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ +>> > +#define ASPEED_PECI_INT_STS 0x1c +>> > +#define ASPEED_PECI_INT_TIMING_RESULT_MASK GENMASK(29, 16) +>> > + /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ >> > + >> > +/* Rx/Tx Data Buffer Registers */ ->> > +#define ASPEED_PECI_W_DATA0????????????????????0x20 ->> > +#define ASPEED_PECI_W_DATA1????????????????????0x24 ->> > +#define ASPEED_PECI_W_DATA2????????????????????0x28 ->> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c ->> > +#define ASPEED_PECI_R_DATA0????????????????????0x30 ->> > +#define ASPEED_PECI_R_DATA1????????????????????0x34 ->> > +#define ASPEED_PECI_R_DATA2????????????????????0x38 ->> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c ->> > +#define ASPEED_PECI_W_DATA4????????????????????0x40 ->> > +#define ASPEED_PECI_W_DATA5????????????????????0x44 ->> > +#define ASPEED_PECI_W_DATA6????????????????????0x48 ->> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c ->> > +#define ASPEED_PECI_R_DATA4????????????????????0x50 ->> > +#define ASPEED_PECI_R_DATA5????????????????????0x54 ->> > +#define ASPEED_PECI_R_DATA6????????????????????0x58 ->> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c ->> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32 +>> > +#define ASPEED_PECI_W_DATA0 0x20 +>> > +#define ASPEED_PECI_W_DATA1 0x24 +>> > +#define ASPEED_PECI_W_DATA2 0x28 +>> > +#define ASPEED_PECI_W_DATA3 0x2c +>> > +#define ASPEED_PECI_R_DATA0 0x30 +>> > +#define ASPEED_PECI_R_DATA1 0x34 +>> > +#define ASPEED_PECI_R_DATA2 0x38 +>> > +#define ASPEED_PECI_R_DATA3 0x3c +>> > +#define ASPEED_PECI_W_DATA4 0x40 +>> > +#define ASPEED_PECI_W_DATA5 0x44 +>> > +#define ASPEED_PECI_W_DATA6 0x48 +>> > +#define ASPEED_PECI_W_DATA7 0x4c +>> > +#define ASPEED_PECI_R_DATA4 0x50 +>> > +#define ASPEED_PECI_R_DATA5 0x54 +>> > +#define ASPEED_PECI_R_DATA6 0x58 +>> > +#define ASPEED_PECI_R_DATA7 0x5c +>> > +#define ASPEED_PECI_DATA_BUF_SIZE_MAX 32 >> > + >> > +/* Timing Negotiation */ ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8 ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1) ->> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0 ->> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1) ->> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1 ->> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1) ->> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1 ->> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1) +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT 8 +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX (BIT(4) - 1) +>> > +#define ASPEED_PECI_CLK_DIV_DEFAULT 0 +>> > +#define ASPEED_PECI_CLK_DIV_MAX (BIT(3) - 1) +>> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_MSG_TIMING_MAX (BIT(8) - 1) +>> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_ADDR_TIMING_MAX (BIT(8) - 1) >> > + >> > +/* Timeout */ ->> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000) +>> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US (50 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US (10 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT (1000) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX (1000) >> > + >> > +struct aspeed_peci { ->> > +???????struct peci_controller controller; ->> > +???????struct device *dev; ->> > +???????void __iomem *base; ->> > +???????struct clk *clk; ->> > +???????struct reset_control *rst; ->> > +???????int irq; ->> > +???????spinlock_t lock; /* to sync completion status handling */ ->> > +???????struct completion xfer_complete; ->> > +???????u32 status; ->> > +???????u32 cmd_timeout_ms; ->> > +???????u32 msg_timing; ->> > +???????u32 addr_timing; ->> > +???????u32 rd_sampling_point; ->> > +???????u32 clk_div; +>> > + struct peci_controller controller; +>> > + struct device *dev; +>> > + void __iomem *base; +>> > + struct clk *clk; +>> > + struct reset_control *rst; +>> > + int irq; +>> > + spinlock_t lock; /* to sync completion status handling */ +>> > + struct completion xfer_complete; +>> > + u32 status; +>> > + u32 cmd_timeout_ms; +>> > + u32 msg_timing; +>> > + u32 addr_timing; +>> > + u32 rd_sampling_point; +>> > + u32 clk_div; >> > +}; >> > + >> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a) >> > +{ ->> > +???????return container_of(a, struct aspeed_peci, controller); +>> > + return container_of(a, struct aspeed_peci, controller); >> > +} >> > + >> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 val; +>> > + u32 val; >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, >> > ASPEED_PECI_CLK_DIV_DEFAULT); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); ->> > +???????/* ->> > +??????? * Timing negotiation period setting. ->> > +??????? * The unit of the programmed value is 4 times of PECI clock period. ->> > +??????? */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + /* +>> > + * Timing negotiation period setting. +>> > + * The unit of the programmed value is 4 times of PECI clock period. +>> > + */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); +>> > + val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- >> > >addr_timing); ->> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); +>> > + writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); >> > + ->> > +???????/* Clear interrupts */ ->> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) | +>> > + /* Clear interrupts */ +>> > + val = readl(priv->base + ASPEED_PECI_INT_STS) | >> > ASPEED_PECI_INT_MASK; >> >> This should be & instead of |, I'm guessing? @@ -312,66 +312,66 @@ zeros to reserved or RO bits, but I suppose re-writing whatever bit pattern they provide on a read is probably okay (I'm having trouble finding any explicit statement either way in the datasheet I've got). ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS); +>> > + writel(val, priv->base + ASPEED_PECI_INT_STS); >> > + ->> > +???????/* Set timing negotiation mode and enable interrupts */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, +>> > + /* Set timing negotiation mode and enable interrupts */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, >> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO); ->> > +???????val |= ASPEED_PECI_INT_MASK; ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL); +>> > + val |= ASPEED_PECI_INT_MASK; +>> > + writel(val, priv->base + ASPEED_PECI_INT_CTRL); >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- >> > >rd_sampling_point); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_EN; ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); +>> > + val |= ASPEED_PECI_CTRL_PECI_EN; +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); >> > +} >> > + >> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); +>> > + u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == +>> > + if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == >> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO) ->> > +???????????????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, ->> > +???????????????????????????????? cmd_sts, ->> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US, ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); +>> > + return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, +>> > + cmd_sts, +>> > + !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), +>> > + ASPEED_PECI_IDLE_CHECK_INTERVAL_US, +>> > + ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); >> > +} >> > + >> > +static int aspeed_peci_xfer(struct peci_controller *controller, ->> > +?????????????????????????? u8 addr, struct peci_request *req) +>> > + u8 addr, struct peci_request *req) >> > +{ ->> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller); ->> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv- +>> > + struct aspeed_peci *priv = to_aspeed_peci(controller); +>> > + unsigned long flags, timeout = msecs_to_jiffies(priv- >> > >cmd_timeout_ms); ->> > +???????u32 peci_head; ->> > +???????int ret; +>> > + u32 peci_head; +>> > + int ret; >> > + ->> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || ->> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) ->> > +???????????????return -EINVAL; +>> > + if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || +>> > + req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) +>> > + return -EINVAL; >> > + ->> > +???????/* Check command sts and bus idle state */ ->> > +???????ret = aspeed_peci_check_idle(priv); ->> > +???????if (ret) ->> > +???????????????return ret; /* -ETIMEDOUT */ +>> > + /* Check command sts and bus idle state */ +>> > + ret = aspeed_peci_check_idle(priv); +>> > + if (ret) +>> > + return ret; /* -ETIMEDOUT */ >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); ->> > +???????reinit_completion(&priv->xfer_complete); +>> > + spin_lock_irqsave(&priv->lock, flags); +>> > + reinit_completion(&priv->xfer_complete); >> > + ->> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); +>> > + peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | +>> > + FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | +>> > + FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); >> > + ->> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); +>> > + writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); >> > + ->> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, ->> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len); +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, +>> > + req->tx.len > 16 ? 16 : req->tx.len); >> >> min(req->tx.len, 16) for the third argument there might be a bit >> clearer. @@ -379,81 +379,81 @@ finding any explicit statement either way in the datasheet I've got). >Ack. > >> ->> > +???????if (req->tx.len > 16) ->> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + +>> > + if (req->tx.len > 16) +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + >> > 16, ->> > +?????????????????????????? req->tx.len - 16); +>> > + req->tx.len - 16); >> > + ->> > +???????dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); ->> > +???????print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- +>> > + dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); +>> > + print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- >> > >tx.len); >> > + ->> > +???????priv->status = 0; ->> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + priv->status = 0; +>> > + writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????ret = wait_for_completion_interruptible_timeout(&priv- +>> > + ret = wait_for_completion_interruptible_timeout(&priv- >> > >xfer_complete, timeout); ->> > +???????if (ret < 0) ->> > +???????????????return ret; +>> > + if (ret < 0) +>> > + return ret; >> > + ->> > +???????if (ret == 0) { ->> > +???????????????dev_dbg(priv->dev, "Timeout waiting for a response!\n"); ->> > +???????????????return -ETIMEDOUT; ->> > +???????} +>> > + if (ret == 0) { +>> > + dev_dbg(priv->dev, "Timeout waiting for a response!\n"); +>> > + return -ETIMEDOUT; +>> > + } >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); +>> > + spin_lock_irqsave(&priv->lock, flags); >> > + ->> > +???????writel(0, priv->base + ASPEED_PECI_CMD); +>> > + writel(0, priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) { ->> > +???????????????spin_unlock_irqrestore(&priv->lock, flags); ->> > +???????????????dev_dbg(priv->dev, "No valid response!\n"); ->> > +???????????????return -EIO; ->> > +???????} +>> > + if (priv->status != ASPEED_PECI_INT_CMD_DONE) { +>> > + spin_unlock_irqrestore(&priv->lock, flags); +>> > + dev_dbg(priv->dev, "No valid response!\n"); +>> > + return -EIO; +>> > + } >> > + ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, ->> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len); +>> > + memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, +>> > + req->rx.len > 16 ? 16 : req->rx.len); >> >> Likewise, min(req->rx.len, 16) here. > >Ack. > >> ->> > +???????if (req->rx.len > 16) ->> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base + +>> > + if (req->rx.len > 16) +>> > + memcpy_fromio(req->rx.buf + 16, priv->base + >> > ASPEED_PECI_R_DATA4, ->> > +???????????????????????????? req->rx.len - 16); +>> > + req->rx.len - 16); >> > + ->> > +???????print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- +>> > + print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- >> > >rx.len); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) >> > +{ ->> > +???????struct aspeed_peci *priv = arg; ->> > +???????u32 status; +>> > + struct aspeed_peci *priv = arg; +>> > + u32 status; >> > + ->> > +???????spin_lock(&priv->lock); ->> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS); ->> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS); ->> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK); +>> > + spin_lock(&priv->lock); +>> > + status = readl(priv->base + ASPEED_PECI_INT_STS); +>> > + writel(status, priv->base + ASPEED_PECI_INT_STS); +>> > + priv->status |= (status & ASPEED_PECI_INT_MASK); >> > + ->> > +???????/* ->> > +??????? * In most cases, interrupt bits will be set one by one but also +>> > + /* +>> > + * In most cases, interrupt bits will be set one by one but also >> > note ->> > +??????? * that multiple interrupt bits could be set at the same time. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + * that multiple interrupt bits could be set at the same time. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_BUS_TIMEOUT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_TIMEOUT\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_BUS_CONNECT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_CONNECT\n"); >> >> s/CONNECT/CONTENTION/ here too (in the message string). @@ -462,20 +462,20 @@ finding any explicit statement either way in the datasheet I've got). > >> >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_BAD) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_BAD\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_ABORT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_ABORT\n"); >> >> Bus contention can of course arise legitimately, and I suppose an >> offline host CPU might result in a timeout, so dbg seems fine for those >> (though as Dan suggests, making some counters available seems like a ->> good idea, especially for contention).? Are the FCS error cases +>> good idea, especially for contention). Are the FCS error cases >> significant enough to warrant something less likely to go unnoticed ->> though?? (e.g. dev_warn_ratelimited() or something?) +>> though? (e.g. dev_warn_ratelimited() or something?) > >It's similar story for FCS errors (can occur legitimately). >We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g. @@ -495,37 +495,37 @@ though, I think. >> >> > + ->> > +???????/* ->> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE +>> > + /* +>> > + * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE >> > bit ->> > +??????? * set even in an error case. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_CMD_DONE) ->> > +???????????????complete(&priv->xfer_complete); +>> > + * set even in an error case. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_CMD_DONE) +>> > + complete(&priv->xfer_complete); >> > + ->> > +???????spin_unlock(&priv->lock); +>> > + spin_unlock(&priv->lock); >> > + ->> > +???????return IRQ_HANDLED; +>> > + return IRQ_HANDLED; >> > +} >> > + >> > +static void __sanitize_clock_divider(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 clk_div; ->> > +???????int ret; +>> > + u32 clk_div; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "clock-divider", +>> > + ret = device_property_read_u32(priv->dev, "clock-divider", >> > &clk_div); ->> > +???????if (ret) { ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid clock-divider: %u, Using +>> > + if (ret) { +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { +>> > + dev_warn(priv->dev, "Invalid clock-divider: %u, Using >> > default: %u\n", ->> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); +>> > + clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); >> > + ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } >> > + ->> > +???????priv->clk_div = clk_div; +>> > + priv->clk_div = clk_div; >> > +} >> > + >> @@ -552,152 +552,152 @@ of name collisions and ensuing confusion). >> >> > +static void __sanitize_msg_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 msg_timing; ->> > +???????int ret; +>> > + u32 msg_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "msg-timing", +>> > + ret = device_property_read_u32(priv->dev, "msg-timing", >> > &msg_timing); ->> > +???????if (ret) { ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : +>> > + if (ret) { +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); +>> > + msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); >> > + ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->msg_timing = msg_timing; +>> > + priv->msg_timing = msg_timing; >> > +} >> > + >> > +static void __sanitize_addr_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 addr_timing; ->> > +???????int ret; +>> > + u32 addr_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "addr-timing", +>> > + ret = device_property_read_u32(priv->dev, "addr-timing", >> > &addr_timing); ->> > +???????if (ret) { ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : +>> > + if (ret) { +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); +>> > + addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); >> > + ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->addr_timing = addr_timing; +>> > + priv->addr_timing = addr_timing; >> > +} >> > + >> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 rd_sampling_point; ->> > +???????int ret; +>> > + u32 rd_sampling_point; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "rd-sampling-point", +>> > + ret = device_property_read_u32(priv->dev, "rd-sampling-point", >> > &rd_sampling_point); ->> > +???????if (ret) { ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use +>> > + if (ret) { +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { +>> > + dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use >> > default : %u\n", ->> > +??????????????????????? rd_sampling_point, +>> > + rd_sampling_point, >> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT); >> > + ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } >> > + ->> > +???????priv->rd_sampling_point = rd_sampling_point; +>> > + priv->rd_sampling_point = rd_sampling_point; >> > +} >> > + >> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 timeout; ->> > +???????int ret; +>> > + u32 timeout; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", +>> > + ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", >> > &timeout); ->> > +???????if (ret) { ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) +>> > + if (ret) { +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) >> > { ->> > +???????????????dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use +>> > + dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use >> > default: %u\n", ->> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); +>> > + timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); >> > + ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } >> > + ->> > +???????priv->cmd_timeout_ms = timeout; +>> > + priv->cmd_timeout_ms = timeout; >> > +} >> > + >> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv) >> > +{ ->> > +???????__sanitize_clock_divider(priv); ->> > +???????__sanitize_msg_timing(priv); ->> > +???????__sanitize_addr_timing(priv); ->> > +???????__sanitize_rd_sampling_point(priv); ->> > +???????__sanitize_cmd_timeout(priv); +>> > + __sanitize_clock_divider(priv); +>> > + __sanitize_msg_timing(priv); +>> > + __sanitize_addr_timing(priv); +>> > + __sanitize_rd_sampling_point(priv); +>> > + __sanitize_cmd_timeout(priv); >> > +} >> > + >> > +static void aspeed_peci_disable_clk(void *data) >> > +{ ->> > +???????clk_disable_unprepare(data); +>> > + clk_disable_unprepare(data); >> > +} >> > + >> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv) >> > +{ ->> > +???????int ret; +>> > + int ret; >> > + ->> > +???????priv->clk = devm_clk_get(priv->dev, NULL); ->> > +???????if (IS_ERR(priv->clk)) ->> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed +>> > + priv->clk = devm_clk_get(priv->dev, NULL); +>> > + if (IS_ERR(priv->clk)) +>> > + return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed >> > to get clk source\n"); >> > + ->> > +???????ret = clk_prepare_enable(priv->clk); ->> > +???????if (ret) { ->> > +???????????????dev_err(priv->dev, "Failed to enable clock\n"); ->> > +???????????????return ret; ->> > +???????} +>> > + ret = clk_prepare_enable(priv->clk); +>> > + if (ret) { +>> > + dev_err(priv->dev, "Failed to enable clock\n"); +>> > + return ret; +>> > + } >> > + ->> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, +>> > + ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, >> > priv->clk); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????aspeed_peci_device_property_sanitize(priv); +>> > + aspeed_peci_device_property_sanitize(priv); >> > + ->> > +???????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static int aspeed_peci_probe(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv; ->> > +???????int ret; +>> > + struct aspeed_peci *priv; +>> > + int ret; >> > + ->> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ->> > +???????if (!priv) ->> > +???????????????return -ENOMEM; +>> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); +>> > + if (!priv) +>> > + return -ENOMEM; >> > + ->> > +???????priv->dev = &pdev->dev; ->> > +???????dev_set_drvdata(priv->dev, priv); +>> > + priv->dev = &pdev->dev; +>> > + dev_set_drvdata(priv->dev, priv); >> > + ->> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0); ->> > +???????if (IS_ERR(priv->base)) ->> > +???????????????return PTR_ERR(priv->base); +>> > + priv->base = devm_platform_ioremap_resource(pdev, 0); +>> > + if (IS_ERR(priv->base)) +>> > + return PTR_ERR(priv->base); >> > + ->> > +???????priv->irq = platform_get_irq(pdev, 0); ->> > +???????if (!priv->irq) ->> > +???????????????return priv->irq; +>> > + priv->irq = platform_get_irq(pdev, 0); +>> > + if (!priv->irq) +>> > + return priv->irq; >> > + ->> > +???????ret = devm_request_irq(&pdev->dev, priv->irq, +>> > + ret = devm_request_irq(&pdev->dev, priv->irq, >> > aspeed_peci_irq_handler, ->> > +????????????????????????????? 0, "peci-aspeed-irq", priv); +>> > + 0, "peci-aspeed-irq", priv); >> ->> Might as well drop the "-irq" suffix here?? (Seems a bit redundant, and +>> Might as well drop the "-irq" suffix here? (Seems a bit redundant, and >> a quick glance through /proc/interrupts on the systems I have at hand >> doesn't show anything else following that convention.) > @@ -707,54 +707,54 @@ of name collisions and ensuing confusion). >-Iwona > >> ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????init_completion(&priv->xfer_complete); ->> > +???????spin_lock_init(&priv->lock); +>> > + init_completion(&priv->xfer_complete); +>> > + spin_lock_init(&priv->lock); >> > + ->> > +???????priv->controller.xfer = aspeed_peci_xfer; +>> > + priv->controller.xfer = aspeed_peci_xfer; >> > + ->> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL); ->> > +???????if (IS_ERR(priv->rst)) { ->> > +???????????????dev_err(&pdev->dev, "Missing or invalid reset controller +>> > + priv->rst = devm_reset_control_get(&pdev->dev, NULL); +>> > + if (IS_ERR(priv->rst)) { +>> > + dev_err(&pdev->dev, "Missing or invalid reset controller >> > entry\n"); ->> > +???????????????return PTR_ERR(priv->rst); ->> > +???????} ->> > +???????reset_control_deassert(priv->rst); +>> > + return PTR_ERR(priv->rst); +>> > + } +>> > + reset_control_deassert(priv->rst); >> > + ->> > +???????ret = aspeed_peci_init_ctrl(priv); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + ret = aspeed_peci_init_ctrl(priv); +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????return peci_controller_add(&priv->controller, priv->dev); +>> > + return peci_controller_add(&priv->controller, priv->dev); >> > +} >> > + >> > +static int aspeed_peci_remove(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); +>> > + struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); >> > + ->> > +???????peci_controller_remove(&priv->controller); ->> > +???????reset_control_assert(priv->rst); +>> > + peci_controller_remove(&priv->controller); +>> > + reset_control_assert(priv->rst); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static const struct of_device_id aspeed_peci_of_table[] = { ->> > +???????{ .compatible = "aspeed,ast2400-peci", }, ->> > +???????{ .compatible = "aspeed,ast2500-peci", }, ->> > +???????{ .compatible = "aspeed,ast2600-peci", }, ->> > +???????{ } +>> > + { .compatible = "aspeed,ast2400-peci", }, +>> > + { .compatible = "aspeed,ast2500-peci", }, +>> > + { .compatible = "aspeed,ast2600-peci", }, +>> > + { } >> > +}; >> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); >> > + >> > +static struct platform_driver aspeed_peci_driver = { ->> > +???????.probe? = aspeed_peci_probe, ->> > +???????.remove = aspeed_peci_remove, ->> > +???????.driver = { ->> > +???????????????.name?????????? = "peci-aspeed", ->> > +???????????????.of_match_table = aspeed_peci_of_table, ->> > +???????}, +>> > + .probe = aspeed_peci_probe, +>> > + .remove = aspeed_peci_remove, +>> > + .driver = { +>> > + .name = "peci-aspeed", +>> > + .of_match_table = aspeed_peci_of_table, +>> > + }, >> > +}; >> > +module_platform_driver(aspeed_peci_driver); >> > + diff --git a/a/content_digest b/N1/content_digest index 3bfd32f..c86f0ce 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,9 +3,36 @@ "ref\020210727084901.GQ8018@packtop\0" "ref\0e6b7588abe48b00b2822ab4614ec0600f9e044f0.camel@intel.com\0" "From\0Zev Weiss <zweiss@equinix.com>\0" - "Subject\0[PATCH 07/14] peci: Add peci-aspeed controller driver\0" + "Subject\0Re: [PATCH 07/14] peci: Add peci-aspeed controller driver\0" "Date\0Thu, 29 Jul 2021 18:15:33 +0000\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Winiarska" + " Iwona <iwona.winiarska@intel.com>\0" + "Cc\0corbet@lwn.net <corbet@lwn.net>" + jae.hyun.yoo@linux.intel.com <jae.hyun.yoo@linux.intel.com> + Lutomirski + Andy <luto@kernel.org> + linux-hwmon@vger.kernel.org <linux-hwmon@vger.kernel.org> + Luck + Tony <tony.luck@intel.com> + andrew@aj.id.au <andrew@aj.id.au> + mchehab@kernel.org <mchehab@kernel.org> + jdelvare@suse.com <jdelvare@suse.com> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + mingo@redhat.com <mingo@redhat.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + tglx@linutronix.de <tglx@linutronix.de> + linux@roeck-us.net <linux@roeck-us.net> + linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org> + linux-doc@vger.kernel.org <linux-doc@vger.kernel.org> + yazen.ghannam@amd.com <yazen.ghannam@amd.com> + robh+dt@kernel.org <robh+dt@kernel.org> + openbmc@lists.ozlabs.org <openbmc@lists.ozlabs.org> + bp@alien8.de <bp@alien8.de> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + pierre-louis.bossart@linux.intel.com <pierre-louis.bossart@linux.intel.com> + andriy.shevchenko@linux.intel.com <andriy.shevchenko@linux.intel.com> + x86@kernel.org <x86@kernel.org> + " gregkh@linuxfoundation.org <gregkh@linuxfoundation.org>\0" "\00:1\0" "b\0" "On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote:\n" @@ -21,11 +48,11 @@ ">> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>\n" ">> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\n" ">> > ---\n" - ">> > MAINTAINERS?????????????????????????? |?? 9 +\n" - ">> > drivers/peci/Kconfig????????????????? |?? 6 +\n" - ">> > drivers/peci/Makefile???????????????? |?? 3 +\n" - ">> > drivers/peci/controller/Kconfig?????? |? 12 +\n" - ">> > drivers/peci/controller/Makefile????? |?? 3 +\n" + ">> > MAINTAINERS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 9 +\n" + ">> > drivers/peci/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 6 +\n" + ">> > drivers/peci/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" + ">> > drivers/peci/controller/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 12 +\n" + ">> > drivers/peci/controller/Makefile\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" ">> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++\n" ">> > 6 files changed, 534 insertions(+)\n" ">> > create mode 100644 drivers/peci/controller/Kconfig\n" @@ -36,30 +63,30 @@ ">> > index 47411e2b6336..4ba874afa2fa 100644\n" ">> > --- a/MAINTAINERS\n" ">> > +++ b/MAINTAINERS\n" - ">> > @@ -2865,6 +2865,15 @@ S:???????Maintained\n" - ">> > F:??????Documentation/hwmon/asc7621.rst\n" - ">> > F:??????drivers/hwmon/asc7621.c\n" + ">> > @@ -2865,6 +2865,15 @@ S:\302\240\302\240\302\240\302\240\302\240\302\240\302\240Maintained\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240Documentation/hwmon/asc7621.rst\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240drivers/hwmon/asc7621.c\n" ">> >\n" ">> > +ASPEED PECI CONTROLLER\n" - ">> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com>\n" - ">> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" - ">> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +S:?????Supported\n" - ">> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" - ">> > +F:?????drivers/peci/controller/peci-aspeed.c\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Iwona Winiarska <iwona.winiarska@intel.com>\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240openbmc@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +S:\302\240\302\240\302\240\302\240\302\240Supported\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240drivers/peci/controller/peci-aspeed.c\n" ">> > +\n" ">> > ASPEED PINCTRL DRIVERS\n" - ">> > M:??????Andrew Jeffery <andrew@aj.id.au>\n" - ">> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" + ">> > M:\302\240\302\240\302\240\302\240\302\240\302\240Andrew Jeffery <andrew@aj.id.au>\n" + ">> > L:\302\240\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" ">> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig\n" ">> > index 601cc3c3c852..0d0ee8009713 100644\n" ">> > --- a/drivers/peci/Kconfig\n" ">> > +++ b/drivers/peci/Kconfig\n" ">> > @@ -12,3 +12,9 @@ menuconfig PECI\n" ">> >\n" - ">> > ????????? This support is also available as a module. If so, the module\n" - ">> > ????????? will be called peci.\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This support is also available as a module. If so, the module\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci.\n" ">> > +\n" ">> > +if PECI\n" ">> > +\n" @@ -87,15 +114,15 @@ ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" ">> > +config PECI_ASPEED\n" - ">> > +???????tristate \"ASPEED PECI support\"\n" - ">> > +???????depends on ARCH_ASPEED || COMPILE_TEST\n" - ">> > +???????depends on OF\n" - ">> > +???????depends on HAS_IOMEM\n" - ">> > +???????help\n" - ">> > +???????? Enable this driver if you want to support ASPEED PECI controller.\n" - ">> > +\n" - ">> > +???????? This driver can be also build as a module. If so, the module\n" - ">> > +???????? will be called peci-aspeed.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240tristate \"ASPEED PECI support\"\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on ARCH_ASPEED || COMPILE_TEST\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on OF\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on HAS_IOMEM\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240help\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 Enable this driver if you want to support ASPEED PECI controller.\n" + ">> > +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This driver can be also build as a module. If so, the module\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci-aspeed.\n" ">> > diff --git a/drivers/peci/controller/Makefile\n" ">> > b/drivers/peci/controller/Makefile\n" ">> > new file mode 100644\n" @@ -105,7 +132,7 @@ ">> > @@ -0,0 +1,3 @@\n" ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" - ">> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o\n" + ">> > +obj-$(CONFIG_PECI_ASPEED)\302\240\302\240\302\240\302\240\302\240\302\240+= peci-aspeed.o\n" ">> > diff --git a/drivers/peci/controller/peci-aspeed.c\n" ">> > b/drivers/peci/controller/peci-aspeed.c\n" ">> > new file mode 100644\n" @@ -134,11 +161,11 @@ ">> > +\n" ">> > +/* ASPEED PECI Registers */\n" ">> > +/* Control Register */\n" - ">> > +#define ASPEED_PECI_CTRL???????????????????????0x00\n" - ">> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13)\n" + ">> > +#define ASPEED_PECI_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x00\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_SAMPLING_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(19, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(13, 12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_COUNT\302\240\302\240\302\240\302\240\302\240BIT(12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_DBG\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(13)\n" ">>\n" ">> Nitpick: might be nice to keep things in a consistent descending order\n" ">> here (13 then 12).\n" @@ -146,17 +173,17 @@ ">\n" ">Sure, I'll change it in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_SOURCE_MASK\302\240\302\240\302\240\302\240\302\240BIT(11)\n" ">>\n" ">> _MASK suffix seems out of place on this one.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6)\n" - ">> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_DIV_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(10, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_OUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(7)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_IN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(6)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_BUS_CONTENT_EN\302\240\302\240\302\240\302\240\302\240\302\240BIT(5)\n" ">>\n" ">> It *is* already kind of a long macro name, but abbreviating \"contention\"\n" ">> to \"content\" seems a bit confusing; I'd suggest keeping the extra three\n" @@ -166,29 +193,29 @@ ">\n" ">You're right - it'll be renamed properly in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_CLK_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Timing Negotiation Register */\n" - ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04\n" - ">> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x04\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_MESSAGE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_ADDRESS_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Command Register */\n" - ">> > +#define ASPEED_PECI_CMD????????????????????????????????0x08\n" - ">> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24)\n" - ">> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3\n" - ">> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\\\n" - ">> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" - ">> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0)\n" + ">> > +#define ASPEED_PECI_CMD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x08\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_PIN_MON\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_STS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(27, 24)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_CMD_STS_ADDR_T_NEGO\302\240\302\240\302\240\302\2400x3\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_IDLE_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\\\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_FIRE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Read/Write Length Register */\n" - ">> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c\n" - ">> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_RW_LENGTH\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x0c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_AW_FCS_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_READ_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_WRITE_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TAGET_ADDR_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">>\n" ">> s/TAGET/TARGET/\n" ">>\n" @@ -197,116 +224,116 @@ ">\n" ">> > +\n" ">> > +/* Expected FCS Data Register */\n" - ">> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10\n" - ">> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_EXP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x10\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_AW_FCS_AUTO_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Captured FCS Data Register */\n" - ">> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14\n" - ">> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_CAP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x14\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Interrupt Register */\n" - ">> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18\n" - ">> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30)\n" - ">> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0\n" - ">> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1\n" - ">> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2\n" - ">> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3)\n" + ">> > +#define ASPEED_PECI_INT_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x18\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_NEGO_SEL_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(31, 30)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO\302\240\302\240\302\2400\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO\302\240\302\240\302\2401\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_MESSAGE_NEGO\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2402\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(4, 0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_TIMEOUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_CONNECT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(3)\n" ">>\n" ">> s/CONNECT/CONTENTION/\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2)\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1)\n" - ">> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_BAD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(2)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_ABORT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(1)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_CMD_DONE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Interrupt Status Register */\n" - ">> > +#define ASPEED_PECI_INT_STS????????????????????0x1c\n" - ">> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16)\n" - ">> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" + ">> > +#define ASPEED_PECI_INT_STS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x1c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_TIMING_RESULT_MASK\302\240\302\240\302\240GENMASK(29, 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" ">> > +\n" ">> > +/* Rx/Tx Data Buffer Registers */\n" - ">> > +#define ASPEED_PECI_W_DATA0????????????????????0x20\n" - ">> > +#define ASPEED_PECI_W_DATA1????????????????????0x24\n" - ">> > +#define ASPEED_PECI_W_DATA2????????????????????0x28\n" - ">> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c\n" - ">> > +#define ASPEED_PECI_R_DATA0????????????????????0x30\n" - ">> > +#define ASPEED_PECI_R_DATA1????????????????????0x34\n" - ">> > +#define ASPEED_PECI_R_DATA2????????????????????0x38\n" - ">> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c\n" - ">> > +#define ASPEED_PECI_W_DATA4????????????????????0x40\n" - ">> > +#define ASPEED_PECI_W_DATA5????????????????????0x44\n" - ">> > +#define ASPEED_PECI_W_DATA6????????????????????0x48\n" - ">> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c\n" - ">> > +#define ASPEED_PECI_R_DATA4????????????????????0x50\n" - ">> > +#define ASPEED_PECI_R_DATA5????????????????????0x54\n" - ">> > +#define ASPEED_PECI_R_DATA6????????????????????0x58\n" - ">> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c\n" - ">> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32\n" + ">> > +#define ASPEED_PECI_W_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x20\n" + ">> > +#define ASPEED_PECI_W_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x24\n" + ">> > +#define ASPEED_PECI_W_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x28\n" + ">> > +#define ASPEED_PECI_W_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x2c\n" + ">> > +#define ASPEED_PECI_R_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x30\n" + ">> > +#define ASPEED_PECI_R_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x34\n" + ">> > +#define ASPEED_PECI_R_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x38\n" + ">> > +#define ASPEED_PECI_R_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x3c\n" + ">> > +#define ASPEED_PECI_W_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x40\n" + ">> > +#define ASPEED_PECI_W_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x44\n" + ">> > +#define ASPEED_PECI_W_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x48\n" + ">> > +#define ASPEED_PECI_W_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x4c\n" + ">> > +#define ASPEED_PECI_R_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x50\n" + ">> > +#define ASPEED_PECI_R_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x54\n" + ">> > +#define ASPEED_PECI_R_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x58\n" + ">> > +#define ASPEED_PECI_R_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x5c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_DATA_BUF_SIZE_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\24032\n" ">> > +\n" ">> > +/* Timing Negotiation */\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1)\n" - ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0\n" - ">> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1)\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1)\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT\302\240\302\2408\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX\302\240\302\240\302\240\302\240\302\240\302\240(BIT(4) - 1)\n" + ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400\n" + ">> > +#define ASPEED_PECI_CLK_DIV_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(3) - 1)\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" ">> > +\n" ">> > +/* Timeout */\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US\302\240\302\240\302\240\302\240\302\240\302\240(50 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US\302\240\302\240\302\240\302\240\302\240(10 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT\302\240\302\240\302\240\302\240\302\240(1000)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(1000)\n" ">> > +\n" ">> > +struct aspeed_peci {\n" - ">> > +???????struct peci_controller controller;\n" - ">> > +???????struct device *dev;\n" - ">> > +???????void __iomem *base;\n" - ">> > +???????struct clk *clk;\n" - ">> > +???????struct reset_control *rst;\n" - ">> > +???????int irq;\n" - ">> > +???????spinlock_t lock; /* to sync completion status handling */\n" - ">> > +???????struct completion xfer_complete;\n" - ">> > +???????u32 status;\n" - ">> > +???????u32 cmd_timeout_ms;\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct peci_controller controller;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct device *dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240void __iomem *base;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct clk *clk;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct reset_control *rst;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spinlock_t lock; /* to sync completion status handling */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct completion xfer_complete;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_timeout_ms;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" ">> > +};\n" ">> > +\n" ">> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a)\n" ">> > +{\n" - ">> > +???????return container_of(a, struct aspeed_peci, controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return container_of(a, struct aspeed_peci, controller);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 val;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 val;\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" ">> > ASPEED_PECI_CLK_DIV_DEFAULT);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" - ">> > +???????/*\n" - ">> > +??????? * Timing negotiation period setting.\n" - ">> > +??????? * The unit of the programmed value is 4 times of PECI clock period.\n" - ">> > +??????? */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Timing negotiation period setting.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * The unit of the programmed value is 4 times of PECI clock period.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" ">> > >addr_timing);\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" ">> > +\n" - ">> > +???????/* Clear interrupts */\n" - ">> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Clear interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" ">> > ASPEED_PECI_INT_MASK;\n" ">>\n" ">> This should be & instead of |, I'm guessing?\n" @@ -322,66 +349,66 @@ "pattern they provide on a read is probably okay (I'm having trouble\n" "finding any explicit statement either way in the datasheet I've got).\n" "\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_STS);\n" ">> > +\n" - ">> > +???????/* Set timing negotiation mode and enable interrupts */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Set timing negotiation mode and enable interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" ">> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO);\n" - ">> > +???????val |= ASPEED_PECI_INT_MASK;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_INT_MASK;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" ">> > >rd_sampling_point);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_EN;\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" ">> > +}\n" ">> > +\n" ">> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" ">> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO)\n" - ">> > +???????????????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" - ">> > +???????????????????????????????? cmd_sts,\n" - ">> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 cmd_sts,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_xfer(struct peci_controller *controller,\n" - ">> > +?????????????????????????? u8 addr, struct peci_request *req)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 u8 addr, struct peci_request *req)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller);\n" - ">> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = to_aspeed_peci(controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned long flags, timeout = msecs_to_jiffies(priv-\n" ">> > >cmd_timeout_ms);\n" - ">> > +???????u32 peci_head;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 peci_head;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" - ">> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" - ">> > +???????????????return -EINVAL;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EINVAL;\n" ">> > +\n" - ">> > +???????/* Check command sts and bus idle state */\n" - ">> > +???????ret = aspeed_peci_check_idle(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret; /* -ETIMEDOUT */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Check command sts and bus idle state */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_check_idle(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret; /* -ETIMEDOUT */\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" - ">> > +???????reinit_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reinit_completion(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" ">> > +\n" - ">> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" ">> > +\n" - ">> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" - ">> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len > 16 ? 16 : req->tx.len);\n" ">>\n" ">> min(req->tx.len, 16) for the third argument there might be a bit\n" ">> clearer.\n" @@ -389,81 +416,81 @@ ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->tx.len > 16)\n" - ">> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" ">> > 16,\n" - ">> > +?????????????????????????? req->tx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len - 16);\n" ">> > +\n" - ">> > +???????dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" - ">> > +???????print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" ">> > >tx.len);\n" ">> > +\n" - ">> > +???????priv->status = 0;\n" - ">> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status = 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????ret = wait_for_completion_interruptible_timeout(&priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = wait_for_completion_interruptible_timeout(&priv-\n" ">> > >xfer_complete, timeout);\n" - ">> > +???????if (ret < 0)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret < 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????if (ret == 0) {\n" - ">> > +???????????????dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" - ">> > +???????????????return -ETIMEDOUT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret == 0) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ETIMEDOUT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????writel(0, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(0, priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" - ">> > +???????????????spin_unlock_irqrestore(&priv->lock, flags);\n" - ">> > +???????????????dev_dbg(priv->dev, \"No valid response!\\n\");\n" - ">> > +???????????????return -EIO;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"No valid response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EIO;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" - ">> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > 16 ? 16 : req->rx.len);\n" ">>\n" ">> Likewise, min(req->rx.len, 16) here.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->rx.len > 16)\n" - ">> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->rx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf + 16, priv->base +\n" ">> > ASPEED_PECI_R_DATA4,\n" - ">> > +???????????????????????????? req->rx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len - 16);\n" ">> > +\n" - ">> > +???????print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" ">> > >rx.len);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = arg;\n" - ">> > +???????u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = arg;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" ">> > +\n" - ">> > +???????spin_lock(&priv->lock);\n" - ">> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240status = readl(priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(status, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status |= (status & ASPEED_PECI_INT_MASK);\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * In most cases, interrupt bits will be set one by one but also\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * In most cases, interrupt bits will be set one by one but also\n" ">> > note\n" - ">> > +??????? * that multiple interrupt bits could be set at the same time.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * that multiple interrupt bits could be set at the same time.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_TIMEOUT\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_CONNECT\\n\");\n" ">>\n" ">> s/CONNECT/CONTENTION/ here too (in the message string).\n" @@ -472,20 +499,20 @@ ">\n" ">>\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_BAD\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_ABORT\\n\");\n" ">>\n" ">> Bus contention can of course arise legitimately, and I suppose an\n" ">> offline host CPU might result in a timeout, so dbg seems fine for those\n" ">> (though as Dan suggests, making some counters available seems like a\n" - ">> good idea, especially for contention).? Are the FCS error cases\n" + ">> good idea, especially for contention).\302\240 Are the FCS error cases\n" ">> significant enough to warrant something less likely to go unnoticed\n" - ">> though?? (e.g. dev_warn_ratelimited() or something?)\n" + ">> though?\302\240 (e.g. dev_warn_ratelimited() or something?)\n" ">\n" ">It's similar story for FCS errors (can occur legitimately).\n" ">We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g.\n" @@ -505,37 +532,37 @@ "\n" ">>\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" ">> > bit\n" - ">> > +??????? * set even in an error case.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_CMD_DONE)\n" - ">> > +???????????????complete(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * set even in an error case.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_CMD_DONE)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240complete(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????spin_unlock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock(&priv->lock);\n" ">> > +\n" - ">> > +???????return IRQ_HANDLED;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return IRQ_HANDLED;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_clock_divider(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 clk_div;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" ">> > &clk_div);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" ">> > +\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->clk_div = clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk_div = clk_div;\n" ">> > +}\n" ">> > +\n" ">>\n" @@ -562,152 +589,152 @@ ">>\n" ">> > +static void __sanitize_msg_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" ">> > &msg_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->msg_timing = msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->msg_timing = msg_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_addr_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" ">> > &addr_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->addr_timing = addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->addr_timing = addr_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" ">> > &rd_sampling_point);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" ">> > default : %u\\n\",\n" - ">> > +??????????????????????? rd_sampling_point,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 rd_sampling_point,\n" ">> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT);\n" ">> > +\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->rd_sampling_point = rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rd_sampling_point = rd_sampling_point;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 timeout;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" ">> > &timeout);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" ">> > {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" ">> > +\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->cmd_timeout_ms = timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->cmd_timeout_ms = timeout;\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????__sanitize_clock_divider(priv);\n" - ">> > +???????__sanitize_msg_timing(priv);\n" - ">> > +???????__sanitize_addr_timing(priv);\n" - ">> > +???????__sanitize_rd_sampling_point(priv);\n" - ">> > +???????__sanitize_cmd_timeout(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_clock_divider(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_msg_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_addr_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_rd_sampling_point(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_cmd_timeout(priv);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_disable_clk(void *data)\n" ">> > +{\n" - ">> > +???????clk_disable_unprepare(data);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_disable_unprepare(data);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv->clk = devm_clk_get(priv->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->clk))\n" - ">> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk = devm_clk_get(priv->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->clk))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" ">> > to get clk source\\n\");\n" ">> > +\n" - ">> > +???????ret = clk_prepare_enable(priv->clk);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????dev_err(priv->dev, \"Failed to enable clock\\n\");\n" - ">> > +???????????????return ret;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = clk_prepare_enable(priv->clk);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(priv->dev, \"Failed to enable clock\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" ">> > priv->clk);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????aspeed_peci_device_property_sanitize(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_device_property_sanitize(priv);\n" ">> > +\n" - ">> > +???????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_probe(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" - ">> > +???????if (!priv)\n" - ">> > +???????????????return -ENOMEM;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ENOMEM;\n" ">> > +\n" - ">> > +???????priv->dev = &pdev->dev;\n" - ">> > +???????dev_set_drvdata(priv->dev, priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->dev = &pdev->dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_set_drvdata(priv->dev, priv);\n" ">> > +\n" - ">> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0);\n" - ">> > +???????if (IS_ERR(priv->base))\n" - ">> > +???????????????return PTR_ERR(priv->base);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->base = devm_platform_ioremap_resource(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->base))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->base);\n" ">> > +\n" - ">> > +???????priv->irq = platform_get_irq(pdev, 0);\n" - ">> > +???????if (!priv->irq)\n" - ">> > +???????????????return priv->irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->irq = platform_get_irq(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv->irq)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return priv->irq;\n" ">> > +\n" - ">> > +???????ret = devm_request_irq(&pdev->dev, priv->irq,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_request_irq(&pdev->dev, priv->irq,\n" ">> > aspeed_peci_irq_handler,\n" - ">> > +????????????????????????????? 0, \"peci-aspeed-irq\", priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 0, \"peci-aspeed-irq\", priv);\n" ">>\n" - ">> Might as well drop the \"-irq\" suffix here?? (Seems a bit redundant, and\n" + ">> Might as well drop the \"-irq\" suffix here?\302\240 (Seems a bit redundant, and\n" ">> a quick glance through /proc/interrupts on the systems I have at hand\n" ">> doesn't show anything else following that convention.)\n" ">\n" @@ -717,54 +744,54 @@ ">-Iwona\n" ">\n" ">>\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????init_completion(&priv->xfer_complete);\n" - ">> > +???????spin_lock_init(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240init_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_init(&priv->lock);\n" ">> > +\n" - ">> > +???????priv->controller.xfer = aspeed_peci_xfer;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->controller.xfer = aspeed_peci_xfer;\n" ">> > +\n" - ">> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->rst)) {\n" - ">> > +???????????????dev_err(&pdev->dev, \"Missing or invalid reset controller\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->rst)) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(&pdev->dev, \"Missing or invalid reset controller\n" ">> > entry\\n\");\n" - ">> > +???????????????return PTR_ERR(priv->rst);\n" - ">> > +???????}\n" - ">> > +???????reset_control_deassert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_deassert(priv->rst);\n" ">> > +\n" - ">> > +???????ret = aspeed_peci_init_ctrl(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_init_ctrl(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????return peci_controller_add(&priv->controller, priv->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return peci_controller_add(&priv->controller, priv->dev);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_remove(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" ">> > +\n" - ">> > +???????peci_controller_remove(&priv->controller);\n" - ">> > +???????reset_control_assert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_controller_remove(&priv->controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_assert(priv->rst);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static const struct of_device_id aspeed_peci_of_table[] = {\n" - ">> > +???????{ .compatible = \"aspeed,ast2400-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2500-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2600-peci\", },\n" - ">> > +???????{ }\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2400-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2500-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2600-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ }\n" ">> > +};\n" ">> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table);\n" ">> > +\n" ">> > +static struct platform_driver aspeed_peci_driver = {\n" - ">> > +???????.probe? = aspeed_peci_probe,\n" - ">> > +???????.remove = aspeed_peci_remove,\n" - ">> > +???????.driver = {\n" - ">> > +???????????????.name?????????? = \"peci-aspeed\",\n" - ">> > +???????????????.of_match_table = aspeed_peci_of_table,\n" - ">> > +???????},\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.probe\302\240 = aspeed_peci_probe,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.remove = aspeed_peci_remove,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.driver = {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.name\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 = \"peci-aspeed\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.of_match_table = aspeed_peci_of_table,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240},\n" ">> > +};\n" ">> > +module_platform_driver(aspeed_peci_driver);\n" ">> > +\n" @@ -777,4 +804,4 @@ ">> > 2.31.1\n" > -4fcca7229ab842a56ccc7dac79d6a2bb35c1843d0d5ce7298682d7796c5ddef7 +448804dee02003783f9959f309f05d551f9b02b93a0279fda5f785be68434732
diff --git a/a/1.txt b/N2/1.txt index 4cd1ca7..1eb9e7d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -11,11 +11,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> >> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> >> > --- ->> > MAINTAINERS?????????????????????????? |?? 9 + ->> > drivers/peci/Kconfig????????????????? |?? 6 + ->> > drivers/peci/Makefile???????????????? |?? 3 + ->> > drivers/peci/controller/Kconfig?????? |? 12 + ->> > drivers/peci/controller/Makefile????? |?? 3 + +>> > MAINTAINERS | 9 + +>> > drivers/peci/Kconfig | 6 + +>> > drivers/peci/Makefile | 3 + +>> > drivers/peci/controller/Kconfig | 12 + +>> > drivers/peci/controller/Makefile | 3 + >> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++ >> > 6 files changed, 534 insertions(+) >> > create mode 100644 drivers/peci/controller/Kconfig @@ -26,30 +26,30 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > index 47411e2b6336..4ba874afa2fa 100644 >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS ->> > @@ -2865,6 +2865,15 @@ S:???????Maintained ->> > F:??????Documentation/hwmon/asc7621.rst ->> > F:??????drivers/hwmon/asc7621.c +>> > @@ -2865,6 +2865,15 @@ S: Maintained +>> > F: Documentation/hwmon/asc7621.rst +>> > F: drivers/hwmon/asc7621.c >> > >> > +ASPEED PECI CONTROLLER ->> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com> ->> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> ->> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) ->> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers) ->> > +S:?????Supported ->> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml ->> > +F:?????drivers/peci/controller/peci-aspeed.c +>> > +M: Iwona Winiarska <iwona.winiarska@intel.com> +>> > +M: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> +>> > +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +>> > +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +>> > +S: Supported +>> > +F: Documentation/devicetree/bindings/peci/peci-aspeed.yaml +>> > +F: drivers/peci/controller/peci-aspeed.c >> > + >> > ASPEED PINCTRL DRIVERS ->> > M:??????Andrew Jeffery <andrew@aj.id.au> ->> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) +>> > M: Andrew Jeffery <andrew@aj.id.au> +>> > L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) >> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig >> > index 601cc3c3c852..0d0ee8009713 100644 >> > --- a/drivers/peci/Kconfig >> > +++ b/drivers/peci/Kconfig >> > @@ -12,3 +12,9 @@ menuconfig PECI >> > ->> > ????????? This support is also available as a module. If so, the module ->> > ????????? will be called peci. +>> > This support is also available as a module. If so, the module +>> > will be called peci. >> > + >> > +if PECI >> > + @@ -77,15 +77,15 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + >> > +config PECI_ASPEED ->> > +???????tristate "ASPEED PECI support" ->> > +???????depends on ARCH_ASPEED || COMPILE_TEST ->> > +???????depends on OF ->> > +???????depends on HAS_IOMEM ->> > +???????help ->> > +???????? Enable this driver if you want to support ASPEED PECI controller. ->> > + ->> > +???????? This driver can be also build as a module. If so, the module ->> > +???????? will be called peci-aspeed. +>> > + tristate "ASPEED PECI support" +>> > + depends on ARCH_ASPEED || COMPILE_TEST +>> > + depends on OF +>> > + depends on HAS_IOMEM +>> > + help +>> > + Enable this driver if you want to support ASPEED PECI controller. +>> > + +>> > + This driver can be also build as a module. If so, the module +>> > + will be called peci-aspeed. >> > diff --git a/drivers/peci/controller/Makefile >> > b/drivers/peci/controller/Makefile >> > new file mode 100644 @@ -95,7 +95,7 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > @@ -0,0 +1,3 @@ >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + ->> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o +>> > +obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o >> > diff --git a/drivers/peci/controller/peci-aspeed.c >> > b/drivers/peci/controller/peci-aspeed.c >> > new file mode 100644 @@ -124,11 +124,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > + >> > +/* ASPEED PECI Registers */ >> > +/* Control Register */ ->> > +#define ASPEED_PECI_CTRL???????????????????????0x00 ->> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13) +>> > +#define ASPEED_PECI_CTRL 0x00 +>> > +#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_MASK GENMASK(13, 12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_COUNT BIT(12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_DBG BIT(13) >> >> Nitpick: might be nice to keep things in a consistent descending order >> here (13 then 12). @@ -136,17 +136,17 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >Sure, I'll change it in v2. > ->> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11) +>> > +#define ASPEED_PECI_CTRL_CLK_SOURCE_MASK BIT(11) >> >> _MASK suffix seems out of place on this one. > >Ack. > >> ->> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6) ->> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5) +>> > +#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8) +>> > +#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7) +>> > +#define ASPEED_PECI_CTRL_INVERT_IN BIT(6) +>> > +#define ASPEED_PECI_CTRL_BUS_CONTENT_EN BIT(5) >> >> It *is* already kind of a long macro name, but abbreviating "contention" >> to "content" seems a bit confusing; I'd suggest keeping the extra three @@ -156,29 +156,29 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >You're right - it'll be renamed properly in v2. > ->> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4) ->> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0) +>> > +#define ASPEED_PECI_CTRL_PECI_EN BIT(4) +>> > +#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0) >> > + >> > +/* Timing Negotiation Register */ ->> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04 ->> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0) +>> > +#define ASPEED_PECI_TIMING_NEGOTIATION 0x04 +>> > +#define ASPEED_PECI_TIMING_MESSAGE_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TIMING_ADDRESS_MASK GENMASK(7, 0) >> > + >> > +/* Command Register */ ->> > +#define ASPEED_PECI_CMD????????????????????????????????0x08 ->> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31) ->> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24) ->> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3 ->> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\ ->> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) ->> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0) +>> > +#define ASPEED_PECI_CMD 0x08 +>> > +#define ASPEED_PECI_CMD_PIN_MON BIT(31) +>> > +#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24) +>> > +#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3 +>> > +#define ASPEED_PECI_CMD_IDLE_MASK \ +>> > + (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) +>> > +#define ASPEED_PECI_CMD_FIRE BIT(0) >> > + >> > +/* Read/Write Length Register */ ->> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c ->> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31) ->> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0) +>> > +#define ASPEED_PECI_RW_LENGTH 0x0c +>> > +#define ASPEED_PECI_AW_FCS_EN BIT(31) +>> > +#define ASPEED_PECI_READ_LEN_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_WRITE_LEN_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TAGET_ADDR_MASK GENMASK(7, 0) >> >> s/TAGET/TARGET/ >> @@ -187,116 +187,116 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >> > + >> > +/* Expected FCS Data Register */ ->> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10 ->> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_EXP_FCS 0x10 +>> > +#define ASPEED_PECI_EXP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_EXP_AW_FCS_AUTO_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_EXP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Captured FCS Data Register */ ->> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14 ->> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_CAP_FCS 0x14 +>> > +#define ASPEED_PECI_CAP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_CAP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Interrupt Register */ ->> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18 ->> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30) ->> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0 ->> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1 ->> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2 ->> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0) ->> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4) ->> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3) +>> > +#define ASPEED_PECI_INT_CTRL 0x18 +>> > +#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30) +>> > +#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0 +>> > +#define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO 1 +>> > +#define ASPEED_PECI_MESSAGE_NEGO 2 +>> > +#define ASPEED_PECI_INT_MASK GENMASK(4, 0) +>> > +#define ASPEED_PECI_INT_BUS_TIMEOUT BIT(4) +>> > +#define ASPEED_PECI_INT_BUS_CONNECT BIT(3) >> >> s/CONNECT/CONTENTION/ > >Ack. > >> ->> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2) ->> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1) ->> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0) +>> > +#define ASPEED_PECI_INT_W_FCS_BAD BIT(2) +>> > +#define ASPEED_PECI_INT_W_FCS_ABORT BIT(1) +>> > +#define ASPEED_PECI_INT_CMD_DONE BIT(0) >> > + >> > +/* Interrupt Status Register */ ->> > +#define ASPEED_PECI_INT_STS????????????????????0x1c ->> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16) ->> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ +>> > +#define ASPEED_PECI_INT_STS 0x1c +>> > +#define ASPEED_PECI_INT_TIMING_RESULT_MASK GENMASK(29, 16) +>> > + /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ >> > + >> > +/* Rx/Tx Data Buffer Registers */ ->> > +#define ASPEED_PECI_W_DATA0????????????????????0x20 ->> > +#define ASPEED_PECI_W_DATA1????????????????????0x24 ->> > +#define ASPEED_PECI_W_DATA2????????????????????0x28 ->> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c ->> > +#define ASPEED_PECI_R_DATA0????????????????????0x30 ->> > +#define ASPEED_PECI_R_DATA1????????????????????0x34 ->> > +#define ASPEED_PECI_R_DATA2????????????????????0x38 ->> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c ->> > +#define ASPEED_PECI_W_DATA4????????????????????0x40 ->> > +#define ASPEED_PECI_W_DATA5????????????????????0x44 ->> > +#define ASPEED_PECI_W_DATA6????????????????????0x48 ->> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c ->> > +#define ASPEED_PECI_R_DATA4????????????????????0x50 ->> > +#define ASPEED_PECI_R_DATA5????????????????????0x54 ->> > +#define ASPEED_PECI_R_DATA6????????????????????0x58 ->> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c ->> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32 +>> > +#define ASPEED_PECI_W_DATA0 0x20 +>> > +#define ASPEED_PECI_W_DATA1 0x24 +>> > +#define ASPEED_PECI_W_DATA2 0x28 +>> > +#define ASPEED_PECI_W_DATA3 0x2c +>> > +#define ASPEED_PECI_R_DATA0 0x30 +>> > +#define ASPEED_PECI_R_DATA1 0x34 +>> > +#define ASPEED_PECI_R_DATA2 0x38 +>> > +#define ASPEED_PECI_R_DATA3 0x3c +>> > +#define ASPEED_PECI_W_DATA4 0x40 +>> > +#define ASPEED_PECI_W_DATA5 0x44 +>> > +#define ASPEED_PECI_W_DATA6 0x48 +>> > +#define ASPEED_PECI_W_DATA7 0x4c +>> > +#define ASPEED_PECI_R_DATA4 0x50 +>> > +#define ASPEED_PECI_R_DATA5 0x54 +>> > +#define ASPEED_PECI_R_DATA6 0x58 +>> > +#define ASPEED_PECI_R_DATA7 0x5c +>> > +#define ASPEED_PECI_DATA_BUF_SIZE_MAX 32 >> > + >> > +/* Timing Negotiation */ ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8 ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1) ->> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0 ->> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1) ->> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1 ->> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1) ->> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1 ->> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1) +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT 8 +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX (BIT(4) - 1) +>> > +#define ASPEED_PECI_CLK_DIV_DEFAULT 0 +>> > +#define ASPEED_PECI_CLK_DIV_MAX (BIT(3) - 1) +>> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_MSG_TIMING_MAX (BIT(8) - 1) +>> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_ADDR_TIMING_MAX (BIT(8) - 1) >> > + >> > +/* Timeout */ ->> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000) +>> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US (50 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US (10 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT (1000) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX (1000) >> > + >> > +struct aspeed_peci { ->> > +???????struct peci_controller controller; ->> > +???????struct device *dev; ->> > +???????void __iomem *base; ->> > +???????struct clk *clk; ->> > +???????struct reset_control *rst; ->> > +???????int irq; ->> > +???????spinlock_t lock; /* to sync completion status handling */ ->> > +???????struct completion xfer_complete; ->> > +???????u32 status; ->> > +???????u32 cmd_timeout_ms; ->> > +???????u32 msg_timing; ->> > +???????u32 addr_timing; ->> > +???????u32 rd_sampling_point; ->> > +???????u32 clk_div; +>> > + struct peci_controller controller; +>> > + struct device *dev; +>> > + void __iomem *base; +>> > + struct clk *clk; +>> > + struct reset_control *rst; +>> > + int irq; +>> > + spinlock_t lock; /* to sync completion status handling */ +>> > + struct completion xfer_complete; +>> > + u32 status; +>> > + u32 cmd_timeout_ms; +>> > + u32 msg_timing; +>> > + u32 addr_timing; +>> > + u32 rd_sampling_point; +>> > + u32 clk_div; >> > +}; >> > + >> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a) >> > +{ ->> > +???????return container_of(a, struct aspeed_peci, controller); +>> > + return container_of(a, struct aspeed_peci, controller); >> > +} >> > + >> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 val; +>> > + u32 val; >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, >> > ASPEED_PECI_CLK_DIV_DEFAULT); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); ->> > +???????/* ->> > +??????? * Timing negotiation period setting. ->> > +??????? * The unit of the programmed value is 4 times of PECI clock period. ->> > +??????? */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + /* +>> > + * Timing negotiation period setting. +>> > + * The unit of the programmed value is 4 times of PECI clock period. +>> > + */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); +>> > + val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- >> > >addr_timing); ->> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); +>> > + writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); >> > + ->> > +???????/* Clear interrupts */ ->> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) | +>> > + /* Clear interrupts */ +>> > + val = readl(priv->base + ASPEED_PECI_INT_STS) | >> > ASPEED_PECI_INT_MASK; >> >> This should be & instead of |, I'm guessing? @@ -312,66 +312,66 @@ zeros to reserved or RO bits, but I suppose re-writing whatever bit pattern they provide on a read is probably okay (I'm having trouble finding any explicit statement either way in the datasheet I've got). ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS); +>> > + writel(val, priv->base + ASPEED_PECI_INT_STS); >> > + ->> > +???????/* Set timing negotiation mode and enable interrupts */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, +>> > + /* Set timing negotiation mode and enable interrupts */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, >> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO); ->> > +???????val |= ASPEED_PECI_INT_MASK; ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL); +>> > + val |= ASPEED_PECI_INT_MASK; +>> > + writel(val, priv->base + ASPEED_PECI_INT_CTRL); >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- >> > >rd_sampling_point); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_EN; ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); +>> > + val |= ASPEED_PECI_CTRL_PECI_EN; +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); >> > +} >> > + >> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); +>> > + u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == +>> > + if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == >> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO) ->> > +???????????????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, ->> > +???????????????????????????????? cmd_sts, ->> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US, ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); +>> > + return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, +>> > + cmd_sts, +>> > + !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), +>> > + ASPEED_PECI_IDLE_CHECK_INTERVAL_US, +>> > + ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); >> > +} >> > + >> > +static int aspeed_peci_xfer(struct peci_controller *controller, ->> > +?????????????????????????? u8 addr, struct peci_request *req) +>> > + u8 addr, struct peci_request *req) >> > +{ ->> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller); ->> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv- +>> > + struct aspeed_peci *priv = to_aspeed_peci(controller); +>> > + unsigned long flags, timeout = msecs_to_jiffies(priv- >> > >cmd_timeout_ms); ->> > +???????u32 peci_head; ->> > +???????int ret; +>> > + u32 peci_head; +>> > + int ret; >> > + ->> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || ->> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) ->> > +???????????????return -EINVAL; +>> > + if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || +>> > + req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) +>> > + return -EINVAL; >> > + ->> > +???????/* Check command sts and bus idle state */ ->> > +???????ret = aspeed_peci_check_idle(priv); ->> > +???????if (ret) ->> > +???????????????return ret; /* -ETIMEDOUT */ +>> > + /* Check command sts and bus idle state */ +>> > + ret = aspeed_peci_check_idle(priv); +>> > + if (ret) +>> > + return ret; /* -ETIMEDOUT */ >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); ->> > +???????reinit_completion(&priv->xfer_complete); +>> > + spin_lock_irqsave(&priv->lock, flags); +>> > + reinit_completion(&priv->xfer_complete); >> > + ->> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); +>> > + peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | +>> > + FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | +>> > + FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); >> > + ->> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); +>> > + writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); >> > + ->> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, ->> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len); +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, +>> > + req->tx.len > 16 ? 16 : req->tx.len); >> >> min(req->tx.len, 16) for the third argument there might be a bit >> clearer. @@ -379,81 +379,81 @@ finding any explicit statement either way in the datasheet I've got). >Ack. > >> ->> > +???????if (req->tx.len > 16) ->> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + +>> > + if (req->tx.len > 16) +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + >> > 16, ->> > +?????????????????????????? req->tx.len - 16); +>> > + req->tx.len - 16); >> > + ->> > +???????dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); ->> > +???????print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- +>> > + dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); +>> > + print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- >> > >tx.len); >> > + ->> > +???????priv->status = 0; ->> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + priv->status = 0; +>> > + writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????ret = wait_for_completion_interruptible_timeout(&priv- +>> > + ret = wait_for_completion_interruptible_timeout(&priv- >> > >xfer_complete, timeout); ->> > +???????if (ret < 0) ->> > +???????????????return ret; +>> > + if (ret < 0) +>> > + return ret; >> > + ->> > +???????if (ret == 0) { ->> > +???????????????dev_dbg(priv->dev, "Timeout waiting for a response!\n"); ->> > +???????????????return -ETIMEDOUT; ->> > +???????} +>> > + if (ret == 0) { +>> > + dev_dbg(priv->dev, "Timeout waiting for a response!\n"); +>> > + return -ETIMEDOUT; +>> > + } >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); +>> > + spin_lock_irqsave(&priv->lock, flags); >> > + ->> > +???????writel(0, priv->base + ASPEED_PECI_CMD); +>> > + writel(0, priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) { ->> > +???????????????spin_unlock_irqrestore(&priv->lock, flags); ->> > +???????????????dev_dbg(priv->dev, "No valid response!\n"); ->> > +???????????????return -EIO; ->> > +???????} +>> > + if (priv->status != ASPEED_PECI_INT_CMD_DONE) { +>> > + spin_unlock_irqrestore(&priv->lock, flags); +>> > + dev_dbg(priv->dev, "No valid response!\n"); +>> > + return -EIO; +>> > + } >> > + ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, ->> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len); +>> > + memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, +>> > + req->rx.len > 16 ? 16 : req->rx.len); >> >> Likewise, min(req->rx.len, 16) here. > >Ack. > >> ->> > +???????if (req->rx.len > 16) ->> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base + +>> > + if (req->rx.len > 16) +>> > + memcpy_fromio(req->rx.buf + 16, priv->base + >> > ASPEED_PECI_R_DATA4, ->> > +???????????????????????????? req->rx.len - 16); +>> > + req->rx.len - 16); >> > + ->> > +???????print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- +>> > + print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- >> > >rx.len); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) >> > +{ ->> > +???????struct aspeed_peci *priv = arg; ->> > +???????u32 status; +>> > + struct aspeed_peci *priv = arg; +>> > + u32 status; >> > + ->> > +???????spin_lock(&priv->lock); ->> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS); ->> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS); ->> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK); +>> > + spin_lock(&priv->lock); +>> > + status = readl(priv->base + ASPEED_PECI_INT_STS); +>> > + writel(status, priv->base + ASPEED_PECI_INT_STS); +>> > + priv->status |= (status & ASPEED_PECI_INT_MASK); >> > + ->> > +???????/* ->> > +??????? * In most cases, interrupt bits will be set one by one but also +>> > + /* +>> > + * In most cases, interrupt bits will be set one by one but also >> > note ->> > +??????? * that multiple interrupt bits could be set at the same time. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + * that multiple interrupt bits could be set at the same time. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_BUS_TIMEOUT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_TIMEOUT\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_BUS_CONNECT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_CONNECT\n"); >> >> s/CONNECT/CONTENTION/ here too (in the message string). @@ -462,20 +462,20 @@ finding any explicit statement either way in the datasheet I've got). > >> >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_BAD) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_BAD\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_ABORT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_ABORT\n"); >> >> Bus contention can of course arise legitimately, and I suppose an >> offline host CPU might result in a timeout, so dbg seems fine for those >> (though as Dan suggests, making some counters available seems like a ->> good idea, especially for contention).? Are the FCS error cases +>> good idea, especially for contention). Are the FCS error cases >> significant enough to warrant something less likely to go unnoticed ->> though?? (e.g. dev_warn_ratelimited() or something?) +>> though? (e.g. dev_warn_ratelimited() or something?) > >It's similar story for FCS errors (can occur legitimately). >We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g. @@ -495,37 +495,37 @@ though, I think. >> >> > + ->> > +???????/* ->> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE +>> > + /* +>> > + * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE >> > bit ->> > +??????? * set even in an error case. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_CMD_DONE) ->> > +???????????????complete(&priv->xfer_complete); +>> > + * set even in an error case. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_CMD_DONE) +>> > + complete(&priv->xfer_complete); >> > + ->> > +???????spin_unlock(&priv->lock); +>> > + spin_unlock(&priv->lock); >> > + ->> > +???????return IRQ_HANDLED; +>> > + return IRQ_HANDLED; >> > +} >> > + >> > +static void __sanitize_clock_divider(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 clk_div; ->> > +???????int ret; +>> > + u32 clk_div; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "clock-divider", +>> > + ret = device_property_read_u32(priv->dev, "clock-divider", >> > &clk_div); ->> > +???????if (ret) { ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid clock-divider: %u, Using +>> > + if (ret) { +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { +>> > + dev_warn(priv->dev, "Invalid clock-divider: %u, Using >> > default: %u\n", ->> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); +>> > + clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); >> > + ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } >> > + ->> > +???????priv->clk_div = clk_div; +>> > + priv->clk_div = clk_div; >> > +} >> > + >> @@ -552,152 +552,152 @@ of name collisions and ensuing confusion). >> >> > +static void __sanitize_msg_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 msg_timing; ->> > +???????int ret; +>> > + u32 msg_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "msg-timing", +>> > + ret = device_property_read_u32(priv->dev, "msg-timing", >> > &msg_timing); ->> > +???????if (ret) { ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : +>> > + if (ret) { +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); +>> > + msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); >> > + ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->msg_timing = msg_timing; +>> > + priv->msg_timing = msg_timing; >> > +} >> > + >> > +static void __sanitize_addr_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 addr_timing; ->> > +???????int ret; +>> > + u32 addr_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "addr-timing", +>> > + ret = device_property_read_u32(priv->dev, "addr-timing", >> > &addr_timing); ->> > +???????if (ret) { ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : +>> > + if (ret) { +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); +>> > + addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); >> > + ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->addr_timing = addr_timing; +>> > + priv->addr_timing = addr_timing; >> > +} >> > + >> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 rd_sampling_point; ->> > +???????int ret; +>> > + u32 rd_sampling_point; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "rd-sampling-point", +>> > + ret = device_property_read_u32(priv->dev, "rd-sampling-point", >> > &rd_sampling_point); ->> > +???????if (ret) { ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use +>> > + if (ret) { +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { +>> > + dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use >> > default : %u\n", ->> > +??????????????????????? rd_sampling_point, +>> > + rd_sampling_point, >> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT); >> > + ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } >> > + ->> > +???????priv->rd_sampling_point = rd_sampling_point; +>> > + priv->rd_sampling_point = rd_sampling_point; >> > +} >> > + >> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 timeout; ->> > +???????int ret; +>> > + u32 timeout; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", +>> > + ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", >> > &timeout); ->> > +???????if (ret) { ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) +>> > + if (ret) { +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) >> > { ->> > +???????????????dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use +>> > + dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use >> > default: %u\n", ->> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); +>> > + timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); >> > + ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } >> > + ->> > +???????priv->cmd_timeout_ms = timeout; +>> > + priv->cmd_timeout_ms = timeout; >> > +} >> > + >> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv) >> > +{ ->> > +???????__sanitize_clock_divider(priv); ->> > +???????__sanitize_msg_timing(priv); ->> > +???????__sanitize_addr_timing(priv); ->> > +???????__sanitize_rd_sampling_point(priv); ->> > +???????__sanitize_cmd_timeout(priv); +>> > + __sanitize_clock_divider(priv); +>> > + __sanitize_msg_timing(priv); +>> > + __sanitize_addr_timing(priv); +>> > + __sanitize_rd_sampling_point(priv); +>> > + __sanitize_cmd_timeout(priv); >> > +} >> > + >> > +static void aspeed_peci_disable_clk(void *data) >> > +{ ->> > +???????clk_disable_unprepare(data); +>> > + clk_disable_unprepare(data); >> > +} >> > + >> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv) >> > +{ ->> > +???????int ret; +>> > + int ret; >> > + ->> > +???????priv->clk = devm_clk_get(priv->dev, NULL); ->> > +???????if (IS_ERR(priv->clk)) ->> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed +>> > + priv->clk = devm_clk_get(priv->dev, NULL); +>> > + if (IS_ERR(priv->clk)) +>> > + return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed >> > to get clk source\n"); >> > + ->> > +???????ret = clk_prepare_enable(priv->clk); ->> > +???????if (ret) { ->> > +???????????????dev_err(priv->dev, "Failed to enable clock\n"); ->> > +???????????????return ret; ->> > +???????} +>> > + ret = clk_prepare_enable(priv->clk); +>> > + if (ret) { +>> > + dev_err(priv->dev, "Failed to enable clock\n"); +>> > + return ret; +>> > + } >> > + ->> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, +>> > + ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, >> > priv->clk); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????aspeed_peci_device_property_sanitize(priv); +>> > + aspeed_peci_device_property_sanitize(priv); >> > + ->> > +???????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static int aspeed_peci_probe(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv; ->> > +???????int ret; +>> > + struct aspeed_peci *priv; +>> > + int ret; >> > + ->> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ->> > +???????if (!priv) ->> > +???????????????return -ENOMEM; +>> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); +>> > + if (!priv) +>> > + return -ENOMEM; >> > + ->> > +???????priv->dev = &pdev->dev; ->> > +???????dev_set_drvdata(priv->dev, priv); +>> > + priv->dev = &pdev->dev; +>> > + dev_set_drvdata(priv->dev, priv); >> > + ->> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0); ->> > +???????if (IS_ERR(priv->base)) ->> > +???????????????return PTR_ERR(priv->base); +>> > + priv->base = devm_platform_ioremap_resource(pdev, 0); +>> > + if (IS_ERR(priv->base)) +>> > + return PTR_ERR(priv->base); >> > + ->> > +???????priv->irq = platform_get_irq(pdev, 0); ->> > +???????if (!priv->irq) ->> > +???????????????return priv->irq; +>> > + priv->irq = platform_get_irq(pdev, 0); +>> > + if (!priv->irq) +>> > + return priv->irq; >> > + ->> > +???????ret = devm_request_irq(&pdev->dev, priv->irq, +>> > + ret = devm_request_irq(&pdev->dev, priv->irq, >> > aspeed_peci_irq_handler, ->> > +????????????????????????????? 0, "peci-aspeed-irq", priv); +>> > + 0, "peci-aspeed-irq", priv); >> ->> Might as well drop the "-irq" suffix here?? (Seems a bit redundant, and +>> Might as well drop the "-irq" suffix here? (Seems a bit redundant, and >> a quick glance through /proc/interrupts on the systems I have at hand >> doesn't show anything else following that convention.) > @@ -707,54 +707,54 @@ of name collisions and ensuing confusion). >-Iwona > >> ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????init_completion(&priv->xfer_complete); ->> > +???????spin_lock_init(&priv->lock); +>> > + init_completion(&priv->xfer_complete); +>> > + spin_lock_init(&priv->lock); >> > + ->> > +???????priv->controller.xfer = aspeed_peci_xfer; +>> > + priv->controller.xfer = aspeed_peci_xfer; >> > + ->> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL); ->> > +???????if (IS_ERR(priv->rst)) { ->> > +???????????????dev_err(&pdev->dev, "Missing or invalid reset controller +>> > + priv->rst = devm_reset_control_get(&pdev->dev, NULL); +>> > + if (IS_ERR(priv->rst)) { +>> > + dev_err(&pdev->dev, "Missing or invalid reset controller >> > entry\n"); ->> > +???????????????return PTR_ERR(priv->rst); ->> > +???????} ->> > +???????reset_control_deassert(priv->rst); +>> > + return PTR_ERR(priv->rst); +>> > + } +>> > + reset_control_deassert(priv->rst); >> > + ->> > +???????ret = aspeed_peci_init_ctrl(priv); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + ret = aspeed_peci_init_ctrl(priv); +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????return peci_controller_add(&priv->controller, priv->dev); +>> > + return peci_controller_add(&priv->controller, priv->dev); >> > +} >> > + >> > +static int aspeed_peci_remove(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); +>> > + struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); >> > + ->> > +???????peci_controller_remove(&priv->controller); ->> > +???????reset_control_assert(priv->rst); +>> > + peci_controller_remove(&priv->controller); +>> > + reset_control_assert(priv->rst); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static const struct of_device_id aspeed_peci_of_table[] = { ->> > +???????{ .compatible = "aspeed,ast2400-peci", }, ->> > +???????{ .compatible = "aspeed,ast2500-peci", }, ->> > +???????{ .compatible = "aspeed,ast2600-peci", }, ->> > +???????{ } +>> > + { .compatible = "aspeed,ast2400-peci", }, +>> > + { .compatible = "aspeed,ast2500-peci", }, +>> > + { .compatible = "aspeed,ast2600-peci", }, +>> > + { } >> > +}; >> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); >> > + >> > +static struct platform_driver aspeed_peci_driver = { ->> > +???????.probe? = aspeed_peci_probe, ->> > +???????.remove = aspeed_peci_remove, ->> > +???????.driver = { ->> > +???????????????.name?????????? = "peci-aspeed", ->> > +???????????????.of_match_table = aspeed_peci_of_table, ->> > +???????}, +>> > + .probe = aspeed_peci_probe, +>> > + .remove = aspeed_peci_remove, +>> > + .driver = { +>> > + .name = "peci-aspeed", +>> > + .of_match_table = aspeed_peci_of_table, +>> > + }, >> > +}; >> > +module_platform_driver(aspeed_peci_driver); >> > + diff --git a/a/content_digest b/N2/content_digest index 3bfd32f..1f3622f 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,9 +3,36 @@ "ref\020210727084901.GQ8018@packtop\0" "ref\0e6b7588abe48b00b2822ab4614ec0600f9e044f0.camel@intel.com\0" "From\0Zev Weiss <zweiss@equinix.com>\0" - "Subject\0[PATCH 07/14] peci: Add peci-aspeed controller driver\0" + "Subject\0Re: [PATCH 07/14] peci: Add peci-aspeed controller driver\0" "Date\0Thu, 29 Jul 2021 18:15:33 +0000\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Winiarska" + " Iwona <iwona.winiarska@intel.com>\0" + "Cc\0linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org>" + linux-doc@vger.kernel.org <linux-doc@vger.kernel.org> + jae.hyun.yoo@linux.intel.com <jae.hyun.yoo@linux.intel.com> + mchehab@kernel.org <mchehab@kernel.org> + corbet@lwn.net <corbet@lwn.net> + openbmc@lists.ozlabs.org <openbmc@lists.ozlabs.org> + x86@kernel.org <x86@kernel.org> + pierre-louis.bossart@linux.intel.com <pierre-louis.bossart@linux.intel.com> + mingo@redhat.com <mingo@redhat.com> + linux@roeck-us.net <linux@roeck-us.net> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + jdelvare@suse.com <jdelvare@suse.com> + robh+dt@kernel.org <robh+dt@kernel.org> + bp@alien8.de <bp@alien8.de> + Lutomirski + Andy <luto@kernel.org> + tglx@linutronix.de <tglx@linutronix.de> + andriy.shevchenko@linux.intel.com <andriy.shevchenko@linux.intel.com> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-hwmon@vger.kernel.org <linux-hwmon@vger.kernel.org> + Luck + Tony <tony.luck@intel.com> + andrew@aj.id.au <andrew@aj.id.au> + gregkh@linuxfoundation.org <gregkh@linuxfoundation.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + " yazen.ghannam@amd.com <yazen.ghannam@amd.com>\0" "\00:1\0" "b\0" "On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote:\n" @@ -21,11 +48,11 @@ ">> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>\n" ">> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\n" ">> > ---\n" - ">> > MAINTAINERS?????????????????????????? |?? 9 +\n" - ">> > drivers/peci/Kconfig????????????????? |?? 6 +\n" - ">> > drivers/peci/Makefile???????????????? |?? 3 +\n" - ">> > drivers/peci/controller/Kconfig?????? |? 12 +\n" - ">> > drivers/peci/controller/Makefile????? |?? 3 +\n" + ">> > MAINTAINERS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 9 +\n" + ">> > drivers/peci/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 6 +\n" + ">> > drivers/peci/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" + ">> > drivers/peci/controller/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 12 +\n" + ">> > drivers/peci/controller/Makefile\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" ">> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++\n" ">> > 6 files changed, 534 insertions(+)\n" ">> > create mode 100644 drivers/peci/controller/Kconfig\n" @@ -36,30 +63,30 @@ ">> > index 47411e2b6336..4ba874afa2fa 100644\n" ">> > --- a/MAINTAINERS\n" ">> > +++ b/MAINTAINERS\n" - ">> > @@ -2865,6 +2865,15 @@ S:???????Maintained\n" - ">> > F:??????Documentation/hwmon/asc7621.rst\n" - ">> > F:??????drivers/hwmon/asc7621.c\n" + ">> > @@ -2865,6 +2865,15 @@ S:\302\240\302\240\302\240\302\240\302\240\302\240\302\240Maintained\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240Documentation/hwmon/asc7621.rst\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240drivers/hwmon/asc7621.c\n" ">> >\n" ">> > +ASPEED PECI CONTROLLER\n" - ">> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com>\n" - ">> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" - ">> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +S:?????Supported\n" - ">> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" - ">> > +F:?????drivers/peci/controller/peci-aspeed.c\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Iwona Winiarska <iwona.winiarska@intel.com>\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240openbmc@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +S:\302\240\302\240\302\240\302\240\302\240Supported\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240drivers/peci/controller/peci-aspeed.c\n" ">> > +\n" ">> > ASPEED PINCTRL DRIVERS\n" - ">> > M:??????Andrew Jeffery <andrew@aj.id.au>\n" - ">> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" + ">> > M:\302\240\302\240\302\240\302\240\302\240\302\240Andrew Jeffery <andrew@aj.id.au>\n" + ">> > L:\302\240\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" ">> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig\n" ">> > index 601cc3c3c852..0d0ee8009713 100644\n" ">> > --- a/drivers/peci/Kconfig\n" ">> > +++ b/drivers/peci/Kconfig\n" ">> > @@ -12,3 +12,9 @@ menuconfig PECI\n" ">> >\n" - ">> > ????????? This support is also available as a module. If so, the module\n" - ">> > ????????? will be called peci.\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This support is also available as a module. If so, the module\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci.\n" ">> > +\n" ">> > +if PECI\n" ">> > +\n" @@ -87,15 +114,15 @@ ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" ">> > +config PECI_ASPEED\n" - ">> > +???????tristate \"ASPEED PECI support\"\n" - ">> > +???????depends on ARCH_ASPEED || COMPILE_TEST\n" - ">> > +???????depends on OF\n" - ">> > +???????depends on HAS_IOMEM\n" - ">> > +???????help\n" - ">> > +???????? Enable this driver if you want to support ASPEED PECI controller.\n" - ">> > +\n" - ">> > +???????? This driver can be also build as a module. If so, the module\n" - ">> > +???????? will be called peci-aspeed.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240tristate \"ASPEED PECI support\"\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on ARCH_ASPEED || COMPILE_TEST\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on OF\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on HAS_IOMEM\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240help\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 Enable this driver if you want to support ASPEED PECI controller.\n" + ">> > +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This driver can be also build as a module. If so, the module\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci-aspeed.\n" ">> > diff --git a/drivers/peci/controller/Makefile\n" ">> > b/drivers/peci/controller/Makefile\n" ">> > new file mode 100644\n" @@ -105,7 +132,7 @@ ">> > @@ -0,0 +1,3 @@\n" ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" - ">> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o\n" + ">> > +obj-$(CONFIG_PECI_ASPEED)\302\240\302\240\302\240\302\240\302\240\302\240+= peci-aspeed.o\n" ">> > diff --git a/drivers/peci/controller/peci-aspeed.c\n" ">> > b/drivers/peci/controller/peci-aspeed.c\n" ">> > new file mode 100644\n" @@ -134,11 +161,11 @@ ">> > +\n" ">> > +/* ASPEED PECI Registers */\n" ">> > +/* Control Register */\n" - ">> > +#define ASPEED_PECI_CTRL???????????????????????0x00\n" - ">> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13)\n" + ">> > +#define ASPEED_PECI_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x00\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_SAMPLING_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(19, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(13, 12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_COUNT\302\240\302\240\302\240\302\240\302\240BIT(12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_DBG\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(13)\n" ">>\n" ">> Nitpick: might be nice to keep things in a consistent descending order\n" ">> here (13 then 12).\n" @@ -146,17 +173,17 @@ ">\n" ">Sure, I'll change it in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_SOURCE_MASK\302\240\302\240\302\240\302\240\302\240BIT(11)\n" ">>\n" ">> _MASK suffix seems out of place on this one.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6)\n" - ">> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_DIV_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(10, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_OUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(7)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_IN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(6)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_BUS_CONTENT_EN\302\240\302\240\302\240\302\240\302\240\302\240BIT(5)\n" ">>\n" ">> It *is* already kind of a long macro name, but abbreviating \"contention\"\n" ">> to \"content\" seems a bit confusing; I'd suggest keeping the extra three\n" @@ -166,29 +193,29 @@ ">\n" ">You're right - it'll be renamed properly in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_CLK_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Timing Negotiation Register */\n" - ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04\n" - ">> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x04\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_MESSAGE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_ADDRESS_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Command Register */\n" - ">> > +#define ASPEED_PECI_CMD????????????????????????????????0x08\n" - ">> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24)\n" - ">> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3\n" - ">> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\\\n" - ">> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" - ">> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0)\n" + ">> > +#define ASPEED_PECI_CMD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x08\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_PIN_MON\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_STS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(27, 24)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_CMD_STS_ADDR_T_NEGO\302\240\302\240\302\240\302\2400x3\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_IDLE_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\\\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_FIRE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Read/Write Length Register */\n" - ">> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c\n" - ">> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_RW_LENGTH\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x0c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_AW_FCS_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_READ_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_WRITE_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TAGET_ADDR_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">>\n" ">> s/TAGET/TARGET/\n" ">>\n" @@ -197,116 +224,116 @@ ">\n" ">> > +\n" ">> > +/* Expected FCS Data Register */\n" - ">> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10\n" - ">> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_EXP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x10\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_AW_FCS_AUTO_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Captured FCS Data Register */\n" - ">> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14\n" - ">> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_CAP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x14\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Interrupt Register */\n" - ">> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18\n" - ">> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30)\n" - ">> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0\n" - ">> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1\n" - ">> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2\n" - ">> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3)\n" + ">> > +#define ASPEED_PECI_INT_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x18\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_NEGO_SEL_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(31, 30)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO\302\240\302\240\302\2400\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO\302\240\302\240\302\2401\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_MESSAGE_NEGO\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2402\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(4, 0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_TIMEOUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_CONNECT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(3)\n" ">>\n" ">> s/CONNECT/CONTENTION/\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2)\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1)\n" - ">> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_BAD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(2)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_ABORT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(1)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_CMD_DONE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Interrupt Status Register */\n" - ">> > +#define ASPEED_PECI_INT_STS????????????????????0x1c\n" - ">> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16)\n" - ">> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" + ">> > +#define ASPEED_PECI_INT_STS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x1c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_TIMING_RESULT_MASK\302\240\302\240\302\240GENMASK(29, 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" ">> > +\n" ">> > +/* Rx/Tx Data Buffer Registers */\n" - ">> > +#define ASPEED_PECI_W_DATA0????????????????????0x20\n" - ">> > +#define ASPEED_PECI_W_DATA1????????????????????0x24\n" - ">> > +#define ASPEED_PECI_W_DATA2????????????????????0x28\n" - ">> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c\n" - ">> > +#define ASPEED_PECI_R_DATA0????????????????????0x30\n" - ">> > +#define ASPEED_PECI_R_DATA1????????????????????0x34\n" - ">> > +#define ASPEED_PECI_R_DATA2????????????????????0x38\n" - ">> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c\n" - ">> > +#define ASPEED_PECI_W_DATA4????????????????????0x40\n" - ">> > +#define ASPEED_PECI_W_DATA5????????????????????0x44\n" - ">> > +#define ASPEED_PECI_W_DATA6????????????????????0x48\n" - ">> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c\n" - ">> > +#define ASPEED_PECI_R_DATA4????????????????????0x50\n" - ">> > +#define ASPEED_PECI_R_DATA5????????????????????0x54\n" - ">> > +#define ASPEED_PECI_R_DATA6????????????????????0x58\n" - ">> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c\n" - ">> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32\n" + ">> > +#define ASPEED_PECI_W_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x20\n" + ">> > +#define ASPEED_PECI_W_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x24\n" + ">> > +#define ASPEED_PECI_W_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x28\n" + ">> > +#define ASPEED_PECI_W_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x2c\n" + ">> > +#define ASPEED_PECI_R_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x30\n" + ">> > +#define ASPEED_PECI_R_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x34\n" + ">> > +#define ASPEED_PECI_R_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x38\n" + ">> > +#define ASPEED_PECI_R_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x3c\n" + ">> > +#define ASPEED_PECI_W_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x40\n" + ">> > +#define ASPEED_PECI_W_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x44\n" + ">> > +#define ASPEED_PECI_W_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x48\n" + ">> > +#define ASPEED_PECI_W_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x4c\n" + ">> > +#define ASPEED_PECI_R_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x50\n" + ">> > +#define ASPEED_PECI_R_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x54\n" + ">> > +#define ASPEED_PECI_R_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x58\n" + ">> > +#define ASPEED_PECI_R_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x5c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_DATA_BUF_SIZE_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\24032\n" ">> > +\n" ">> > +/* Timing Negotiation */\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1)\n" - ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0\n" - ">> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1)\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1)\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT\302\240\302\2408\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX\302\240\302\240\302\240\302\240\302\240\302\240(BIT(4) - 1)\n" + ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400\n" + ">> > +#define ASPEED_PECI_CLK_DIV_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(3) - 1)\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" ">> > +\n" ">> > +/* Timeout */\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US\302\240\302\240\302\240\302\240\302\240\302\240(50 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US\302\240\302\240\302\240\302\240\302\240(10 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT\302\240\302\240\302\240\302\240\302\240(1000)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(1000)\n" ">> > +\n" ">> > +struct aspeed_peci {\n" - ">> > +???????struct peci_controller controller;\n" - ">> > +???????struct device *dev;\n" - ">> > +???????void __iomem *base;\n" - ">> > +???????struct clk *clk;\n" - ">> > +???????struct reset_control *rst;\n" - ">> > +???????int irq;\n" - ">> > +???????spinlock_t lock; /* to sync completion status handling */\n" - ">> > +???????struct completion xfer_complete;\n" - ">> > +???????u32 status;\n" - ">> > +???????u32 cmd_timeout_ms;\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct peci_controller controller;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct device *dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240void __iomem *base;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct clk *clk;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct reset_control *rst;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spinlock_t lock; /* to sync completion status handling */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct completion xfer_complete;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_timeout_ms;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" ">> > +};\n" ">> > +\n" ">> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a)\n" ">> > +{\n" - ">> > +???????return container_of(a, struct aspeed_peci, controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return container_of(a, struct aspeed_peci, controller);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 val;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 val;\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" ">> > ASPEED_PECI_CLK_DIV_DEFAULT);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" - ">> > +???????/*\n" - ">> > +??????? * Timing negotiation period setting.\n" - ">> > +??????? * The unit of the programmed value is 4 times of PECI clock period.\n" - ">> > +??????? */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Timing negotiation period setting.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * The unit of the programmed value is 4 times of PECI clock period.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" ">> > >addr_timing);\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" ">> > +\n" - ">> > +???????/* Clear interrupts */\n" - ">> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Clear interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" ">> > ASPEED_PECI_INT_MASK;\n" ">>\n" ">> This should be & instead of |, I'm guessing?\n" @@ -322,66 +349,66 @@ "pattern they provide on a read is probably okay (I'm having trouble\n" "finding any explicit statement either way in the datasheet I've got).\n" "\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_STS);\n" ">> > +\n" - ">> > +???????/* Set timing negotiation mode and enable interrupts */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Set timing negotiation mode and enable interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" ">> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO);\n" - ">> > +???????val |= ASPEED_PECI_INT_MASK;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_INT_MASK;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" ">> > >rd_sampling_point);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_EN;\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" ">> > +}\n" ">> > +\n" ">> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" ">> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO)\n" - ">> > +???????????????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" - ">> > +???????????????????????????????? cmd_sts,\n" - ">> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 cmd_sts,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_xfer(struct peci_controller *controller,\n" - ">> > +?????????????????????????? u8 addr, struct peci_request *req)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 u8 addr, struct peci_request *req)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller);\n" - ">> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = to_aspeed_peci(controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned long flags, timeout = msecs_to_jiffies(priv-\n" ">> > >cmd_timeout_ms);\n" - ">> > +???????u32 peci_head;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 peci_head;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" - ">> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" - ">> > +???????????????return -EINVAL;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EINVAL;\n" ">> > +\n" - ">> > +???????/* Check command sts and bus idle state */\n" - ">> > +???????ret = aspeed_peci_check_idle(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret; /* -ETIMEDOUT */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Check command sts and bus idle state */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_check_idle(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret; /* -ETIMEDOUT */\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" - ">> > +???????reinit_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reinit_completion(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" ">> > +\n" - ">> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" ">> > +\n" - ">> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" - ">> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len > 16 ? 16 : req->tx.len);\n" ">>\n" ">> min(req->tx.len, 16) for the third argument there might be a bit\n" ">> clearer.\n" @@ -389,81 +416,81 @@ ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->tx.len > 16)\n" - ">> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" ">> > 16,\n" - ">> > +?????????????????????????? req->tx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len - 16);\n" ">> > +\n" - ">> > +???????dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" - ">> > +???????print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" ">> > >tx.len);\n" ">> > +\n" - ">> > +???????priv->status = 0;\n" - ">> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status = 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????ret = wait_for_completion_interruptible_timeout(&priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = wait_for_completion_interruptible_timeout(&priv-\n" ">> > >xfer_complete, timeout);\n" - ">> > +???????if (ret < 0)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret < 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????if (ret == 0) {\n" - ">> > +???????????????dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" - ">> > +???????????????return -ETIMEDOUT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret == 0) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ETIMEDOUT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????writel(0, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(0, priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" - ">> > +???????????????spin_unlock_irqrestore(&priv->lock, flags);\n" - ">> > +???????????????dev_dbg(priv->dev, \"No valid response!\\n\");\n" - ">> > +???????????????return -EIO;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"No valid response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EIO;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" - ">> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > 16 ? 16 : req->rx.len);\n" ">>\n" ">> Likewise, min(req->rx.len, 16) here.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->rx.len > 16)\n" - ">> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->rx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf + 16, priv->base +\n" ">> > ASPEED_PECI_R_DATA4,\n" - ">> > +???????????????????????????? req->rx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len - 16);\n" ">> > +\n" - ">> > +???????print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" ">> > >rx.len);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = arg;\n" - ">> > +???????u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = arg;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" ">> > +\n" - ">> > +???????spin_lock(&priv->lock);\n" - ">> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240status = readl(priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(status, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status |= (status & ASPEED_PECI_INT_MASK);\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * In most cases, interrupt bits will be set one by one but also\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * In most cases, interrupt bits will be set one by one but also\n" ">> > note\n" - ">> > +??????? * that multiple interrupt bits could be set at the same time.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * that multiple interrupt bits could be set at the same time.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_TIMEOUT\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_CONNECT\\n\");\n" ">>\n" ">> s/CONNECT/CONTENTION/ here too (in the message string).\n" @@ -472,20 +499,20 @@ ">\n" ">>\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_BAD\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_ABORT\\n\");\n" ">>\n" ">> Bus contention can of course arise legitimately, and I suppose an\n" ">> offline host CPU might result in a timeout, so dbg seems fine for those\n" ">> (though as Dan suggests, making some counters available seems like a\n" - ">> good idea, especially for contention).? Are the FCS error cases\n" + ">> good idea, especially for contention).\302\240 Are the FCS error cases\n" ">> significant enough to warrant something less likely to go unnoticed\n" - ">> though?? (e.g. dev_warn_ratelimited() or something?)\n" + ">> though?\302\240 (e.g. dev_warn_ratelimited() or something?)\n" ">\n" ">It's similar story for FCS errors (can occur legitimately).\n" ">We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g.\n" @@ -505,37 +532,37 @@ "\n" ">>\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" ">> > bit\n" - ">> > +??????? * set even in an error case.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_CMD_DONE)\n" - ">> > +???????????????complete(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * set even in an error case.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_CMD_DONE)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240complete(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????spin_unlock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock(&priv->lock);\n" ">> > +\n" - ">> > +???????return IRQ_HANDLED;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return IRQ_HANDLED;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_clock_divider(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 clk_div;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" ">> > &clk_div);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" ">> > +\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->clk_div = clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk_div = clk_div;\n" ">> > +}\n" ">> > +\n" ">>\n" @@ -562,152 +589,152 @@ ">>\n" ">> > +static void __sanitize_msg_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" ">> > &msg_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->msg_timing = msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->msg_timing = msg_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_addr_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" ">> > &addr_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->addr_timing = addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->addr_timing = addr_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" ">> > &rd_sampling_point);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" ">> > default : %u\\n\",\n" - ">> > +??????????????????????? rd_sampling_point,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 rd_sampling_point,\n" ">> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT);\n" ">> > +\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->rd_sampling_point = rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rd_sampling_point = rd_sampling_point;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 timeout;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" ">> > &timeout);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" ">> > {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" ">> > +\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->cmd_timeout_ms = timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->cmd_timeout_ms = timeout;\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????__sanitize_clock_divider(priv);\n" - ">> > +???????__sanitize_msg_timing(priv);\n" - ">> > +???????__sanitize_addr_timing(priv);\n" - ">> > +???????__sanitize_rd_sampling_point(priv);\n" - ">> > +???????__sanitize_cmd_timeout(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_clock_divider(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_msg_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_addr_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_rd_sampling_point(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_cmd_timeout(priv);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_disable_clk(void *data)\n" ">> > +{\n" - ">> > +???????clk_disable_unprepare(data);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_disable_unprepare(data);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv->clk = devm_clk_get(priv->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->clk))\n" - ">> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk = devm_clk_get(priv->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->clk))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" ">> > to get clk source\\n\");\n" ">> > +\n" - ">> > +???????ret = clk_prepare_enable(priv->clk);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????dev_err(priv->dev, \"Failed to enable clock\\n\");\n" - ">> > +???????????????return ret;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = clk_prepare_enable(priv->clk);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(priv->dev, \"Failed to enable clock\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" ">> > priv->clk);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????aspeed_peci_device_property_sanitize(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_device_property_sanitize(priv);\n" ">> > +\n" - ">> > +???????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_probe(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" - ">> > +???????if (!priv)\n" - ">> > +???????????????return -ENOMEM;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ENOMEM;\n" ">> > +\n" - ">> > +???????priv->dev = &pdev->dev;\n" - ">> > +???????dev_set_drvdata(priv->dev, priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->dev = &pdev->dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_set_drvdata(priv->dev, priv);\n" ">> > +\n" - ">> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0);\n" - ">> > +???????if (IS_ERR(priv->base))\n" - ">> > +???????????????return PTR_ERR(priv->base);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->base = devm_platform_ioremap_resource(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->base))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->base);\n" ">> > +\n" - ">> > +???????priv->irq = platform_get_irq(pdev, 0);\n" - ">> > +???????if (!priv->irq)\n" - ">> > +???????????????return priv->irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->irq = platform_get_irq(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv->irq)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return priv->irq;\n" ">> > +\n" - ">> > +???????ret = devm_request_irq(&pdev->dev, priv->irq,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_request_irq(&pdev->dev, priv->irq,\n" ">> > aspeed_peci_irq_handler,\n" - ">> > +????????????????????????????? 0, \"peci-aspeed-irq\", priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 0, \"peci-aspeed-irq\", priv);\n" ">>\n" - ">> Might as well drop the \"-irq\" suffix here?? (Seems a bit redundant, and\n" + ">> Might as well drop the \"-irq\" suffix here?\302\240 (Seems a bit redundant, and\n" ">> a quick glance through /proc/interrupts on the systems I have at hand\n" ">> doesn't show anything else following that convention.)\n" ">\n" @@ -717,54 +744,54 @@ ">-Iwona\n" ">\n" ">>\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????init_completion(&priv->xfer_complete);\n" - ">> > +???????spin_lock_init(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240init_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_init(&priv->lock);\n" ">> > +\n" - ">> > +???????priv->controller.xfer = aspeed_peci_xfer;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->controller.xfer = aspeed_peci_xfer;\n" ">> > +\n" - ">> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->rst)) {\n" - ">> > +???????????????dev_err(&pdev->dev, \"Missing or invalid reset controller\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->rst)) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(&pdev->dev, \"Missing or invalid reset controller\n" ">> > entry\\n\");\n" - ">> > +???????????????return PTR_ERR(priv->rst);\n" - ">> > +???????}\n" - ">> > +???????reset_control_deassert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_deassert(priv->rst);\n" ">> > +\n" - ">> > +???????ret = aspeed_peci_init_ctrl(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_init_ctrl(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????return peci_controller_add(&priv->controller, priv->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return peci_controller_add(&priv->controller, priv->dev);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_remove(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" ">> > +\n" - ">> > +???????peci_controller_remove(&priv->controller);\n" - ">> > +???????reset_control_assert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_controller_remove(&priv->controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_assert(priv->rst);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static const struct of_device_id aspeed_peci_of_table[] = {\n" - ">> > +???????{ .compatible = \"aspeed,ast2400-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2500-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2600-peci\", },\n" - ">> > +???????{ }\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2400-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2500-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2600-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ }\n" ">> > +};\n" ">> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table);\n" ">> > +\n" ">> > +static struct platform_driver aspeed_peci_driver = {\n" - ">> > +???????.probe? = aspeed_peci_probe,\n" - ">> > +???????.remove = aspeed_peci_remove,\n" - ">> > +???????.driver = {\n" - ">> > +???????????????.name?????????? = \"peci-aspeed\",\n" - ">> > +???????????????.of_match_table = aspeed_peci_of_table,\n" - ">> > +???????},\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.probe\302\240 = aspeed_peci_probe,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.remove = aspeed_peci_remove,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.driver = {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.name\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 = \"peci-aspeed\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.of_match_table = aspeed_peci_of_table,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240},\n" ">> > +};\n" ">> > +module_platform_driver(aspeed_peci_driver);\n" ">> > +\n" @@ -777,4 +804,4 @@ ">> > 2.31.1\n" > -4fcca7229ab842a56ccc7dac79d6a2bb35c1843d0d5ce7298682d7796c5ddef7 +e411869029fbf2c03605822bec8bc5b03667345bc838d07b8fd6bc4d2e0ad6ab
diff --git a/a/1.txt b/N3/1.txt index 4cd1ca7..aacaae1 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -11,11 +11,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> >> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> >> > --- ->> > MAINTAINERS?????????????????????????? |?? 9 + ->> > drivers/peci/Kconfig????????????????? |?? 6 + ->> > drivers/peci/Makefile???????????????? |?? 3 + ->> > drivers/peci/controller/Kconfig?????? |? 12 + ->> > drivers/peci/controller/Makefile????? |?? 3 + +>> > MAINTAINERS | 9 + +>> > drivers/peci/Kconfig | 6 + +>> > drivers/peci/Makefile | 3 + +>> > drivers/peci/controller/Kconfig | 12 + +>> > drivers/peci/controller/Makefile | 3 + >> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++ >> > 6 files changed, 534 insertions(+) >> > create mode 100644 drivers/peci/controller/Kconfig @@ -26,30 +26,30 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > index 47411e2b6336..4ba874afa2fa 100644 >> > --- a/MAINTAINERS >> > +++ b/MAINTAINERS ->> > @@ -2865,6 +2865,15 @@ S:???????Maintained ->> > F:??????Documentation/hwmon/asc7621.rst ->> > F:??????drivers/hwmon/asc7621.c +>> > @@ -2865,6 +2865,15 @@ S: Maintained +>> > F: Documentation/hwmon/asc7621.rst +>> > F: drivers/hwmon/asc7621.c >> > >> > +ASPEED PECI CONTROLLER ->> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com> ->> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> ->> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) ->> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers) ->> > +S:?????Supported ->> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml ->> > +F:?????drivers/peci/controller/peci-aspeed.c +>> > +M: Iwona Winiarska <iwona.winiarska@intel.com> +>> > +M: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> +>> > +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +>> > +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +>> > +S: Supported +>> > +F: Documentation/devicetree/bindings/peci/peci-aspeed.yaml +>> > +F: drivers/peci/controller/peci-aspeed.c >> > + >> > ASPEED PINCTRL DRIVERS ->> > M:??????Andrew Jeffery <andrew@aj.id.au> ->> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers) +>> > M: Andrew Jeffery <andrew@aj.id.au> +>> > L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) >> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig >> > index 601cc3c3c852..0d0ee8009713 100644 >> > --- a/drivers/peci/Kconfig >> > +++ b/drivers/peci/Kconfig >> > @@ -12,3 +12,9 @@ menuconfig PECI >> > ->> > ????????? This support is also available as a module. If so, the module ->> > ????????? will be called peci. +>> > This support is also available as a module. If so, the module +>> > will be called peci. >> > + >> > +if PECI >> > + @@ -77,15 +77,15 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + >> > +config PECI_ASPEED ->> > +???????tristate "ASPEED PECI support" ->> > +???????depends on ARCH_ASPEED || COMPILE_TEST ->> > +???????depends on OF ->> > +???????depends on HAS_IOMEM ->> > +???????help ->> > +???????? Enable this driver if you want to support ASPEED PECI controller. ->> > + ->> > +???????? This driver can be also build as a module. If so, the module ->> > +???????? will be called peci-aspeed. +>> > + tristate "ASPEED PECI support" +>> > + depends on ARCH_ASPEED || COMPILE_TEST +>> > + depends on OF +>> > + depends on HAS_IOMEM +>> > + help +>> > + Enable this driver if you want to support ASPEED PECI controller. +>> > + +>> > + This driver can be also build as a module. If so, the module +>> > + will be called peci-aspeed. >> > diff --git a/drivers/peci/controller/Makefile >> > b/drivers/peci/controller/Makefile >> > new file mode 100644 @@ -95,7 +95,7 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > @@ -0,0 +1,3 @@ >> > +# SPDX-License-Identifier: GPL-2.0-only >> > + ->> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o +>> > +obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o >> > diff --git a/drivers/peci/controller/peci-aspeed.c >> > b/drivers/peci/controller/peci-aspeed.c >> > new file mode 100644 @@ -124,11 +124,11 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: >> > + >> > +/* ASPEED PECI Registers */ >> > +/* Control Register */ ->> > +#define ASPEED_PECI_CTRL???????????????????????0x00 ->> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12) ->> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13) +>> > +#define ASPEED_PECI_CTRL 0x00 +>> > +#define ASPEED_PECI_CTRL_SAMPLING_MASK GENMASK(19, 16) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_MASK GENMASK(13, 12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_COUNT BIT(12) +>> > +#define ASPEED_PECI_CTRL_READ_MODE_DBG BIT(13) >> >> Nitpick: might be nice to keep things in a consistent descending order >> here (13 then 12). @@ -136,17 +136,17 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >Sure, I'll change it in v2. > ->> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11) +>> > +#define ASPEED_PECI_CTRL_CLK_SOURCE_MASK BIT(11) >> >> _MASK suffix seems out of place on this one. > >Ack. > >> ->> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7) ->> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6) ->> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5) +>> > +#define ASPEED_PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8) +>> > +#define ASPEED_PECI_CTRL_INVERT_OUT BIT(7) +>> > +#define ASPEED_PECI_CTRL_INVERT_IN BIT(6) +>> > +#define ASPEED_PECI_CTRL_BUS_CONTENT_EN BIT(5) >> >> It *is* already kind of a long macro name, but abbreviating "contention" >> to "content" seems a bit confusing; I'd suggest keeping the extra three @@ -156,29 +156,29 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >You're right - it'll be renamed properly in v2. > ->> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4) ->> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0) +>> > +#define ASPEED_PECI_CTRL_PECI_EN BIT(4) +>> > +#define ASPEED_PECI_CTRL_PECI_CLK_EN BIT(0) >> > + >> > +/* Timing Negotiation Register */ ->> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04 ->> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0) +>> > +#define ASPEED_PECI_TIMING_NEGOTIATION 0x04 +>> > +#define ASPEED_PECI_TIMING_MESSAGE_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TIMING_ADDRESS_MASK GENMASK(7, 0) >> > + >> > +/* Command Register */ ->> > +#define ASPEED_PECI_CMD????????????????????????????????0x08 ->> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31) ->> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24) ->> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3 ->> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\ ->> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) ->> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0) +>> > +#define ASPEED_PECI_CMD 0x08 +>> > +#define ASPEED_PECI_CMD_PIN_MON BIT(31) +>> > +#define ASPEED_PECI_CMD_STS_MASK GENMASK(27, 24) +>> > +#define ASPEED_PECI_CMD_STS_ADDR_T_NEGO 0x3 +>> > +#define ASPEED_PECI_CMD_IDLE_MASK \ +>> > + (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON) +>> > +#define ASPEED_PECI_CMD_FIRE BIT(0) >> > + >> > +/* Read/Write Length Register */ ->> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c ->> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31) ->> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0) +>> > +#define ASPEED_PECI_RW_LENGTH 0x0c +>> > +#define ASPEED_PECI_AW_FCS_EN BIT(31) +>> > +#define ASPEED_PECI_READ_LEN_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_WRITE_LEN_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_TAGET_ADDR_MASK GENMASK(7, 0) >> >> s/TAGET/TARGET/ >> @@ -187,116 +187,116 @@ On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote: > >> > + >> > +/* Expected FCS Data Register */ ->> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10 ->> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8) ->> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_EXP_FCS 0x10 +>> > +#define ASPEED_PECI_EXP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_EXP_AW_FCS_AUTO_MASK GENMASK(15, 8) +>> > +#define ASPEED_PECI_EXP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Captured FCS Data Register */ ->> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14 ->> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16) ->> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0) +>> > +#define ASPEED_PECI_CAP_FCS 0x14 +>> > +#define ASPEED_PECI_CAP_READ_FCS_MASK GENMASK(23, 16) +>> > +#define ASPEED_PECI_CAP_WRITE_FCS_MASK GENMASK(7, 0) >> > + >> > +/* Interrupt Register */ ->> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18 ->> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30) ->> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0 ->> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1 ->> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2 ->> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0) ->> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4) ->> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3) +>> > +#define ASPEED_PECI_INT_CTRL 0x18 +>> > +#define ASPEED_PECI_TIMING_NEGO_SEL_MASK GENMASK(31, 30) +>> > +#define ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO 0 +>> > +#define ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO 1 +>> > +#define ASPEED_PECI_MESSAGE_NEGO 2 +>> > +#define ASPEED_PECI_INT_MASK GENMASK(4, 0) +>> > +#define ASPEED_PECI_INT_BUS_TIMEOUT BIT(4) +>> > +#define ASPEED_PECI_INT_BUS_CONNECT BIT(3) >> >> s/CONNECT/CONTENTION/ > >Ack. > >> ->> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2) ->> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1) ->> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0) +>> > +#define ASPEED_PECI_INT_W_FCS_BAD BIT(2) +>> > +#define ASPEED_PECI_INT_W_FCS_ABORT BIT(1) +>> > +#define ASPEED_PECI_INT_CMD_DONE BIT(0) >> > + >> > +/* Interrupt Status Register */ ->> > +#define ASPEED_PECI_INT_STS????????????????????0x1c ->> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16) ->> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ +>> > +#define ASPEED_PECI_INT_STS 0x1c +>> > +#define ASPEED_PECI_INT_TIMING_RESULT_MASK GENMASK(29, 16) +>> > + /* bits[4..0]: Same bit fields in the 'Interrupt Register' */ >> > + >> > +/* Rx/Tx Data Buffer Registers */ ->> > +#define ASPEED_PECI_W_DATA0????????????????????0x20 ->> > +#define ASPEED_PECI_W_DATA1????????????????????0x24 ->> > +#define ASPEED_PECI_W_DATA2????????????????????0x28 ->> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c ->> > +#define ASPEED_PECI_R_DATA0????????????????????0x30 ->> > +#define ASPEED_PECI_R_DATA1????????????????????0x34 ->> > +#define ASPEED_PECI_R_DATA2????????????????????0x38 ->> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c ->> > +#define ASPEED_PECI_W_DATA4????????????????????0x40 ->> > +#define ASPEED_PECI_W_DATA5????????????????????0x44 ->> > +#define ASPEED_PECI_W_DATA6????????????????????0x48 ->> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c ->> > +#define ASPEED_PECI_R_DATA4????????????????????0x50 ->> > +#define ASPEED_PECI_R_DATA5????????????????????0x54 ->> > +#define ASPEED_PECI_R_DATA6????????????????????0x58 ->> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c ->> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32 +>> > +#define ASPEED_PECI_W_DATA0 0x20 +>> > +#define ASPEED_PECI_W_DATA1 0x24 +>> > +#define ASPEED_PECI_W_DATA2 0x28 +>> > +#define ASPEED_PECI_W_DATA3 0x2c +>> > +#define ASPEED_PECI_R_DATA0 0x30 +>> > +#define ASPEED_PECI_R_DATA1 0x34 +>> > +#define ASPEED_PECI_R_DATA2 0x38 +>> > +#define ASPEED_PECI_R_DATA3 0x3c +>> > +#define ASPEED_PECI_W_DATA4 0x40 +>> > +#define ASPEED_PECI_W_DATA5 0x44 +>> > +#define ASPEED_PECI_W_DATA6 0x48 +>> > +#define ASPEED_PECI_W_DATA7 0x4c +>> > +#define ASPEED_PECI_R_DATA4 0x50 +>> > +#define ASPEED_PECI_R_DATA5 0x54 +>> > +#define ASPEED_PECI_R_DATA6 0x58 +>> > +#define ASPEED_PECI_R_DATA7 0x5c +>> > +#define ASPEED_PECI_DATA_BUF_SIZE_MAX 32 >> > + >> > +/* Timing Negotiation */ ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8 ->> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1) ->> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0 ->> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1) ->> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1 ->> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1) ->> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1 ->> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1) +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT 8 +>> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX (BIT(4) - 1) +>> > +#define ASPEED_PECI_CLK_DIV_DEFAULT 0 +>> > +#define ASPEED_PECI_CLK_DIV_MAX (BIT(3) - 1) +>> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_MSG_TIMING_MAX (BIT(8) - 1) +>> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT 1 +>> > +#define ASPEED_PECI_ADDR_TIMING_MAX (BIT(8) - 1) >> > + >> > +/* Timeout */ ->> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000) ->> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000) +>> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US (50 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US (10 * USEC_PER_MSEC) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT (1000) +>> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX (1000) >> > + >> > +struct aspeed_peci { ->> > +???????struct peci_controller controller; ->> > +???????struct device *dev; ->> > +???????void __iomem *base; ->> > +???????struct clk *clk; ->> > +???????struct reset_control *rst; ->> > +???????int irq; ->> > +???????spinlock_t lock; /* to sync completion status handling */ ->> > +???????struct completion xfer_complete; ->> > +???????u32 status; ->> > +???????u32 cmd_timeout_ms; ->> > +???????u32 msg_timing; ->> > +???????u32 addr_timing; ->> > +???????u32 rd_sampling_point; ->> > +???????u32 clk_div; +>> > + struct peci_controller controller; +>> > + struct device *dev; +>> > + void __iomem *base; +>> > + struct clk *clk; +>> > + struct reset_control *rst; +>> > + int irq; +>> > + spinlock_t lock; /* to sync completion status handling */ +>> > + struct completion xfer_complete; +>> > + u32 status; +>> > + u32 cmd_timeout_ms; +>> > + u32 msg_timing; +>> > + u32 addr_timing; +>> > + u32 rd_sampling_point; +>> > + u32 clk_div; >> > +}; >> > + >> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a) >> > +{ ->> > +???????return container_of(a, struct aspeed_peci, controller); +>> > + return container_of(a, struct aspeed_peci, controller); >> > +} >> > + >> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 val; +>> > + u32 val; >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, >> > ASPEED_PECI_CLK_DIV_DEFAULT); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); ->> > +???????/* ->> > +??????? * Timing negotiation period setting. ->> > +??????? * The unit of the programmed value is 4 times of PECI clock period. ->> > +??????? */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + /* +>> > + * Timing negotiation period setting. +>> > + * The unit of the programmed value is 4 times of PECI clock period. +>> > + */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing); +>> > + val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv- >> > >addr_timing); ->> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); +>> > + writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION); >> > + ->> > +???????/* Clear interrupts */ ->> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) | +>> > + /* Clear interrupts */ +>> > + val = readl(priv->base + ASPEED_PECI_INT_STS) | >> > ASPEED_PECI_INT_MASK; >> >> This should be & instead of |, I'm guessing? @@ -312,66 +312,66 @@ zeros to reserved or RO bits, but I suppose re-writing whatever bit pattern they provide on a read is probably okay (I'm having trouble finding any explicit statement either way in the datasheet I've got). ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS); +>> > + writel(val, priv->base + ASPEED_PECI_INT_STS); >> > + ->> > +???????/* Set timing negotiation mode and enable interrupts */ ->> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, +>> > + /* Set timing negotiation mode and enable interrupts */ +>> > + val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK, >> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO); ->> > +???????val |= ASPEED_PECI_INT_MASK; ->> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL); +>> > + val |= ASPEED_PECI_INT_MASK; +>> > + writel(val, priv->base + ASPEED_PECI_INT_CTRL); >> > + ->> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- +>> > + val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv- >> > >rd_sampling_point); ->> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); ->> > +???????val |= ASPEED_PECI_CTRL_PECI_EN; ->> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN; ->> > +???????writel(val, priv->base + ASPEED_PECI_CTRL); +>> > + val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div); +>> > + val |= ASPEED_PECI_CTRL_PECI_EN; +>> > + val |= ASPEED_PECI_CTRL_PECI_CLK_EN; +>> > + writel(val, priv->base + ASPEED_PECI_CTRL); >> > +} >> > + >> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); +>> > + u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == +>> > + if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) == >> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO) ->> > +???????????????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, ->> > +???????????????????????????????? cmd_sts, ->> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US, ->> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); +>> > + return readl_poll_timeout(priv->base + ASPEED_PECI_CMD, +>> > + cmd_sts, +>> > + !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK), +>> > + ASPEED_PECI_IDLE_CHECK_INTERVAL_US, +>> > + ASPEED_PECI_IDLE_CHECK_TIMEOUT_US); >> > +} >> > + >> > +static int aspeed_peci_xfer(struct peci_controller *controller, ->> > +?????????????????????????? u8 addr, struct peci_request *req) +>> > + u8 addr, struct peci_request *req) >> > +{ ->> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller); ->> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv- +>> > + struct aspeed_peci *priv = to_aspeed_peci(controller); +>> > + unsigned long flags, timeout = msecs_to_jiffies(priv- >> > >cmd_timeout_ms); ->> > +???????u32 peci_head; ->> > +???????int ret; +>> > + u32 peci_head; +>> > + int ret; >> > + ->> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || ->> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) ->> > +???????????????return -EINVAL; +>> > + if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX || +>> > + req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX) +>> > + return -EINVAL; >> > + ->> > +???????/* Check command sts and bus idle state */ ->> > +???????ret = aspeed_peci_check_idle(priv); ->> > +???????if (ret) ->> > +???????????????return ret; /* -ETIMEDOUT */ +>> > + /* Check command sts and bus idle state */ +>> > + ret = aspeed_peci_check_idle(priv); +>> > + if (ret) +>> > + return ret; /* -ETIMEDOUT */ >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); ->> > +???????reinit_completion(&priv->xfer_complete); +>> > + spin_lock_irqsave(&priv->lock, flags); +>> > + reinit_completion(&priv->xfer_complete); >> > + ->> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | ->> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); +>> > + peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) | +>> > + FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) | +>> > + FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len); >> > + ->> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); +>> > + writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH); >> > + ->> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, ->> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len); +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf, +>> > + req->tx.len > 16 ? 16 : req->tx.len); >> >> min(req->tx.len, 16) for the third argument there might be a bit >> clearer. @@ -379,81 +379,81 @@ finding any explicit statement either way in the datasheet I've got). >Ack. > >> ->> > +???????if (req->tx.len > 16) ->> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + +>> > + if (req->tx.len > 16) +>> > + memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf + >> > 16, ->> > +?????????????????????????? req->tx.len - 16); +>> > + req->tx.len - 16); >> > + ->> > +???????dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); ->> > +???????print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- +>> > + dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); +>> > + print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req- >> > >tx.len); >> > + ->> > +???????priv->status = 0; ->> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + priv->status = 0; +>> > + writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????ret = wait_for_completion_interruptible_timeout(&priv- +>> > + ret = wait_for_completion_interruptible_timeout(&priv- >> > >xfer_complete, timeout); ->> > +???????if (ret < 0) ->> > +???????????????return ret; +>> > + if (ret < 0) +>> > + return ret; >> > + ->> > +???????if (ret == 0) { ->> > +???????????????dev_dbg(priv->dev, "Timeout waiting for a response!\n"); ->> > +???????????????return -ETIMEDOUT; ->> > +???????} +>> > + if (ret == 0) { +>> > + dev_dbg(priv->dev, "Timeout waiting for a response!\n"); +>> > + return -ETIMEDOUT; +>> > + } >> > + ->> > +???????spin_lock_irqsave(&priv->lock, flags); +>> > + spin_lock_irqsave(&priv->lock, flags); >> > + ->> > +???????writel(0, priv->base + ASPEED_PECI_CMD); +>> > + writel(0, priv->base + ASPEED_PECI_CMD); >> > + ->> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) { ->> > +???????????????spin_unlock_irqrestore(&priv->lock, flags); ->> > +???????????????dev_dbg(priv->dev, "No valid response!\n"); ->> > +???????????????return -EIO; ->> > +???????} +>> > + if (priv->status != ASPEED_PECI_INT_CMD_DONE) { +>> > + spin_unlock_irqrestore(&priv->lock, flags); +>> > + dev_dbg(priv->dev, "No valid response!\n"); +>> > + return -EIO; +>> > + } >> > + ->> > +???????spin_unlock_irqrestore(&priv->lock, flags); +>> > + spin_unlock_irqrestore(&priv->lock, flags); >> > + ->> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, ->> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len); +>> > + memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0, +>> > + req->rx.len > 16 ? 16 : req->rx.len); >> >> Likewise, min(req->rx.len, 16) here. > >Ack. > >> ->> > +???????if (req->rx.len > 16) ->> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base + +>> > + if (req->rx.len > 16) +>> > + memcpy_fromio(req->rx.buf + 16, priv->base + >> > ASPEED_PECI_R_DATA4, ->> > +???????????????????????????? req->rx.len - 16); +>> > + req->rx.len - 16); >> > + ->> > +???????print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- +>> > + print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req- >> > >rx.len); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) >> > +{ ->> > +???????struct aspeed_peci *priv = arg; ->> > +???????u32 status; +>> > + struct aspeed_peci *priv = arg; +>> > + u32 status; >> > + ->> > +???????spin_lock(&priv->lock); ->> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS); ->> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS); ->> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK); +>> > + spin_lock(&priv->lock); +>> > + status = readl(priv->base + ASPEED_PECI_INT_STS); +>> > + writel(status, priv->base + ASPEED_PECI_INT_STS); +>> > + priv->status |= (status & ASPEED_PECI_INT_MASK); >> > + ->> > +???????/* ->> > +??????? * In most cases, interrupt bits will be set one by one but also +>> > + /* +>> > + * In most cases, interrupt bits will be set one by one but also >> > note ->> > +??????? * that multiple interrupt bits could be set at the same time. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + * that multiple interrupt bits could be set at the same time. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_BUS_TIMEOUT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_TIMEOUT\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_BUS_CONNECT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_BUS_CONNECT\n"); >> >> s/CONNECT/CONTENTION/ here too (in the message string). @@ -462,20 +462,20 @@ finding any explicit statement either way in the datasheet I've got). > >> >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_BAD) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_BAD\n"); >> > + ->> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT) ->> > +???????????????dev_dbg_ratelimited(priv->dev, +>> > + if (status & ASPEED_PECI_INT_W_FCS_ABORT) +>> > + dev_dbg_ratelimited(priv->dev, >> > "ASPEED_PECI_INT_W_FCS_ABORT\n"); >> >> Bus contention can of course arise legitimately, and I suppose an >> offline host CPU might result in a timeout, so dbg seems fine for those >> (though as Dan suggests, making some counters available seems like a ->> good idea, especially for contention).? Are the FCS error cases +>> good idea, especially for contention). Are the FCS error cases >> significant enough to warrant something less likely to go unnoticed ->> though?? (e.g. dev_warn_ratelimited() or something?) +>> though? (e.g. dev_warn_ratelimited() or something?) > >It's similar story for FCS errors (can occur legitimately). >We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g. @@ -495,37 +495,37 @@ though, I think. >> >> > + ->> > +???????/* ->> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE +>> > + /* +>> > + * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE >> > bit ->> > +??????? * set even in an error case. ->> > +??????? */ ->> > +???????if (status & ASPEED_PECI_INT_CMD_DONE) ->> > +???????????????complete(&priv->xfer_complete); +>> > + * set even in an error case. +>> > + */ +>> > + if (status & ASPEED_PECI_INT_CMD_DONE) +>> > + complete(&priv->xfer_complete); >> > + ->> > +???????spin_unlock(&priv->lock); +>> > + spin_unlock(&priv->lock); >> > + ->> > +???????return IRQ_HANDLED; +>> > + return IRQ_HANDLED; >> > +} >> > + >> > +static void __sanitize_clock_divider(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 clk_div; ->> > +???????int ret; +>> > + u32 clk_div; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "clock-divider", +>> > + ret = device_property_read_u32(priv->dev, "clock-divider", >> > &clk_div); ->> > +???????if (ret) { ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid clock-divider: %u, Using +>> > + if (ret) { +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) { +>> > + dev_warn(priv->dev, "Invalid clock-divider: %u, Using >> > default: %u\n", ->> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); +>> > + clk_div, ASPEED_PECI_CLK_DIV_DEFAULT); >> > + ->> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; ->> > +???????} +>> > + clk_div = ASPEED_PECI_CLK_DIV_DEFAULT; +>> > + } >> > + ->> > +???????priv->clk_div = clk_div; +>> > + priv->clk_div = clk_div; >> > +} >> > + >> @@ -552,152 +552,152 @@ of name collisions and ensuing confusion). >> >> > +static void __sanitize_msg_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 msg_timing; ->> > +???????int ret; +>> > + u32 msg_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "msg-timing", +>> > + ret = device_property_read_u32(priv->dev, "msg-timing", >> > &msg_timing); ->> > +???????if (ret) { ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : +>> > + if (ret) { +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid msg-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); +>> > + msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT); >> > + ->> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; ->> > +???????} +>> > + msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->msg_timing = msg_timing; +>> > + priv->msg_timing = msg_timing; >> > +} >> > + >> > +static void __sanitize_addr_timing(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 addr_timing; ->> > +???????int ret; +>> > + u32 addr_timing; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "addr-timing", +>> > + ret = device_property_read_u32(priv->dev, "addr-timing", >> > &addr_timing); ->> > +???????if (ret) { ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : +>> > + if (ret) { +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) { +>> > + dev_warn(priv->dev, "Invalid addr-timing : %u, Use default : >> > %u\n", ->> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); +>> > + addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT); >> > + ->> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; ->> > +???????} +>> > + addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT; +>> > + } >> > + ->> > +???????priv->addr_timing = addr_timing; +>> > + priv->addr_timing = addr_timing; >> > +} >> > + >> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 rd_sampling_point; ->> > +???????int ret; +>> > + u32 rd_sampling_point; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "rd-sampling-point", +>> > + ret = device_property_read_u32(priv->dev, "rd-sampling-point", >> > &rd_sampling_point); ->> > +???????if (ret) { ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { ->> > +???????????????dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use +>> > + if (ret) { +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) { +>> > + dev_warn(priv->dev, "Invalid rd-sampling-point: %u, Use >> > default : %u\n", ->> > +??????????????????????? rd_sampling_point, +>> > + rd_sampling_point, >> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT); >> > + ->> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; ->> > +???????} +>> > + rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT; +>> > + } >> > + ->> > +???????priv->rd_sampling_point = rd_sampling_point; +>> > + priv->rd_sampling_point = rd_sampling_point; >> > +} >> > + >> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv) >> > +{ ->> > +???????u32 timeout; ->> > +???????int ret; +>> > + u32 timeout; +>> > + int ret; >> > + ->> > +???????ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", +>> > + ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", >> > &timeout); ->> > +???????if (ret) { ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) +>> > + if (ret) { +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0) >> > { ->> > +???????????????dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use +>> > + dev_warn(priv->dev, "Invalid cmd-timeout-ms: %u, Use >> > default: %u\n", ->> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); +>> > + timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT); >> > + ->> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; ->> > +???????} +>> > + timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT; +>> > + } >> > + ->> > +???????priv->cmd_timeout_ms = timeout; +>> > + priv->cmd_timeout_ms = timeout; >> > +} >> > + >> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv) >> > +{ ->> > +???????__sanitize_clock_divider(priv); ->> > +???????__sanitize_msg_timing(priv); ->> > +???????__sanitize_addr_timing(priv); ->> > +???????__sanitize_rd_sampling_point(priv); ->> > +???????__sanitize_cmd_timeout(priv); +>> > + __sanitize_clock_divider(priv); +>> > + __sanitize_msg_timing(priv); +>> > + __sanitize_addr_timing(priv); +>> > + __sanitize_rd_sampling_point(priv); +>> > + __sanitize_cmd_timeout(priv); >> > +} >> > + >> > +static void aspeed_peci_disable_clk(void *data) >> > +{ ->> > +???????clk_disable_unprepare(data); +>> > + clk_disable_unprepare(data); >> > +} >> > + >> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv) >> > +{ ->> > +???????int ret; +>> > + int ret; >> > + ->> > +???????priv->clk = devm_clk_get(priv->dev, NULL); ->> > +???????if (IS_ERR(priv->clk)) ->> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed +>> > + priv->clk = devm_clk_get(priv->dev, NULL); +>> > + if (IS_ERR(priv->clk)) +>> > + return dev_err_probe(priv->dev, PTR_ERR(priv->clk), "Failed >> > to get clk source\n"); >> > + ->> > +???????ret = clk_prepare_enable(priv->clk); ->> > +???????if (ret) { ->> > +???????????????dev_err(priv->dev, "Failed to enable clock\n"); ->> > +???????????????return ret; ->> > +???????} +>> > + ret = clk_prepare_enable(priv->clk); +>> > + if (ret) { +>> > + dev_err(priv->dev, "Failed to enable clock\n"); +>> > + return ret; +>> > + } >> > + ->> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, +>> > + ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk, >> > priv->clk); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????aspeed_peci_device_property_sanitize(priv); +>> > + aspeed_peci_device_property_sanitize(priv); >> > + ->> > +???????aspeed_peci_init_regs(priv); +>> > + aspeed_peci_init_regs(priv); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static int aspeed_peci_probe(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv; ->> > +???????int ret; +>> > + struct aspeed_peci *priv; +>> > + int ret; >> > + ->> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ->> > +???????if (!priv) ->> > +???????????????return -ENOMEM; +>> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); +>> > + if (!priv) +>> > + return -ENOMEM; >> > + ->> > +???????priv->dev = &pdev->dev; ->> > +???????dev_set_drvdata(priv->dev, priv); +>> > + priv->dev = &pdev->dev; +>> > + dev_set_drvdata(priv->dev, priv); >> > + ->> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0); ->> > +???????if (IS_ERR(priv->base)) ->> > +???????????????return PTR_ERR(priv->base); +>> > + priv->base = devm_platform_ioremap_resource(pdev, 0); +>> > + if (IS_ERR(priv->base)) +>> > + return PTR_ERR(priv->base); >> > + ->> > +???????priv->irq = platform_get_irq(pdev, 0); ->> > +???????if (!priv->irq) ->> > +???????????????return priv->irq; +>> > + priv->irq = platform_get_irq(pdev, 0); +>> > + if (!priv->irq) +>> > + return priv->irq; >> > + ->> > +???????ret = devm_request_irq(&pdev->dev, priv->irq, +>> > + ret = devm_request_irq(&pdev->dev, priv->irq, >> > aspeed_peci_irq_handler, ->> > +????????????????????????????? 0, "peci-aspeed-irq", priv); +>> > + 0, "peci-aspeed-irq", priv); >> ->> Might as well drop the "-irq" suffix here?? (Seems a bit redundant, and +>> Might as well drop the "-irq" suffix here? (Seems a bit redundant, and >> a quick glance through /proc/interrupts on the systems I have at hand >> doesn't show anything else following that convention.) > @@ -707,54 +707,54 @@ of name collisions and ensuing confusion). >-Iwona > >> ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????init_completion(&priv->xfer_complete); ->> > +???????spin_lock_init(&priv->lock); +>> > + init_completion(&priv->xfer_complete); +>> > + spin_lock_init(&priv->lock); >> > + ->> > +???????priv->controller.xfer = aspeed_peci_xfer; +>> > + priv->controller.xfer = aspeed_peci_xfer; >> > + ->> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL); ->> > +???????if (IS_ERR(priv->rst)) { ->> > +???????????????dev_err(&pdev->dev, "Missing or invalid reset controller +>> > + priv->rst = devm_reset_control_get(&pdev->dev, NULL); +>> > + if (IS_ERR(priv->rst)) { +>> > + dev_err(&pdev->dev, "Missing or invalid reset controller >> > entry\n"); ->> > +???????????????return PTR_ERR(priv->rst); ->> > +???????} ->> > +???????reset_control_deassert(priv->rst); +>> > + return PTR_ERR(priv->rst); +>> > + } +>> > + reset_control_deassert(priv->rst); >> > + ->> > +???????ret = aspeed_peci_init_ctrl(priv); ->> > +???????if (ret) ->> > +???????????????return ret; +>> > + ret = aspeed_peci_init_ctrl(priv); +>> > + if (ret) +>> > + return ret; >> > + ->> > +???????return peci_controller_add(&priv->controller, priv->dev); +>> > + return peci_controller_add(&priv->controller, priv->dev); >> > +} >> > + >> > +static int aspeed_peci_remove(struct platform_device *pdev) >> > +{ ->> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); +>> > + struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); >> > + ->> > +???????peci_controller_remove(&priv->controller); ->> > +???????reset_control_assert(priv->rst); +>> > + peci_controller_remove(&priv->controller); +>> > + reset_control_assert(priv->rst); >> > + ->> > +???????return 0; +>> > + return 0; >> > +} >> > + >> > +static const struct of_device_id aspeed_peci_of_table[] = { ->> > +???????{ .compatible = "aspeed,ast2400-peci", }, ->> > +???????{ .compatible = "aspeed,ast2500-peci", }, ->> > +???????{ .compatible = "aspeed,ast2600-peci", }, ->> > +???????{ } +>> > + { .compatible = "aspeed,ast2400-peci", }, +>> > + { .compatible = "aspeed,ast2500-peci", }, +>> > + { .compatible = "aspeed,ast2600-peci", }, +>> > + { } >> > +}; >> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); >> > + >> > +static struct platform_driver aspeed_peci_driver = { ->> > +???????.probe? = aspeed_peci_probe, ->> > +???????.remove = aspeed_peci_remove, ->> > +???????.driver = { ->> > +???????????????.name?????????? = "peci-aspeed", ->> > +???????????????.of_match_table = aspeed_peci_of_table, ->> > +???????}, +>> > + .probe = aspeed_peci_probe, +>> > + .remove = aspeed_peci_remove, +>> > + .driver = { +>> > + .name = "peci-aspeed", +>> > + .of_match_table = aspeed_peci_of_table, +>> > + }, >> > +}; >> > +module_platform_driver(aspeed_peci_driver); >> > + @@ -766,3 +766,7 @@ of name collisions and ensuing confusion). >> > -- >> > 2.31.1 > +_______________________________________________ +linux-arm-kernel mailing list +linux-arm-kernel@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/a/content_digest b/N3/content_digest index 3bfd32f..4f7f345 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -3,9 +3,36 @@ "ref\020210727084901.GQ8018@packtop\0" "ref\0e6b7588abe48b00b2822ab4614ec0600f9e044f0.camel@intel.com\0" "From\0Zev Weiss <zweiss@equinix.com>\0" - "Subject\0[PATCH 07/14] peci: Add peci-aspeed controller driver\0" + "Subject\0Re: [PATCH 07/14] peci: Add peci-aspeed controller driver\0" "Date\0Thu, 29 Jul 2021 18:15:33 +0000\0" - "To\0linux-aspeed@lists.ozlabs.org\0" + "To\0Winiarska" + " Iwona <iwona.winiarska@intel.com>\0" + "Cc\0corbet@lwn.net <corbet@lwn.net>" + jae.hyun.yoo@linux.intel.com <jae.hyun.yoo@linux.intel.com> + Lutomirski + Andy <luto@kernel.org> + linux-hwmon@vger.kernel.org <linux-hwmon@vger.kernel.org> + Luck + Tony <tony.luck@intel.com> + andrew@aj.id.au <andrew@aj.id.au> + mchehab@kernel.org <mchehab@kernel.org> + jdelvare@suse.com <jdelvare@suse.com> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + mingo@redhat.com <mingo@redhat.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + tglx@linutronix.de <tglx@linutronix.de> + linux@roeck-us.net <linux@roeck-us.net> + linux-aspeed@lists.ozlabs.org <linux-aspeed@lists.ozlabs.org> + linux-doc@vger.kernel.org <linux-doc@vger.kernel.org> + yazen.ghannam@amd.com <yazen.ghannam@amd.com> + robh+dt@kernel.org <robh+dt@kernel.org> + openbmc@lists.ozlabs.org <openbmc@lists.ozlabs.org> + bp@alien8.de <bp@alien8.de> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + pierre-louis.bossart@linux.intel.com <pierre-louis.bossart@linux.intel.com> + andriy.shevchenko@linux.intel.com <andriy.shevchenko@linux.intel.com> + x86@kernel.org <x86@kernel.org> + " gregkh@linuxfoundation.org <gregkh@linuxfoundation.org>\0" "\00:1\0" "b\0" "On Thu, Jul 29, 2021 at 09:03:28AM CDT, Winiarska, Iwona wrote:\n" @@ -21,11 +48,11 @@ ">> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>\n" ">> > Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\n" ">> > ---\n" - ">> > MAINTAINERS?????????????????????????? |?? 9 +\n" - ">> > drivers/peci/Kconfig????????????????? |?? 6 +\n" - ">> > drivers/peci/Makefile???????????????? |?? 3 +\n" - ">> > drivers/peci/controller/Kconfig?????? |? 12 +\n" - ">> > drivers/peci/controller/Makefile????? |?? 3 +\n" + ">> > MAINTAINERS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 9 +\n" + ">> > drivers/peci/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 6 +\n" + ">> > drivers/peci/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" + ">> > drivers/peci/controller/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 12 +\n" + ">> > drivers/peci/controller/Makefile\302\240\302\240\302\240\302\240\302\240 |\302\240\302\240 3 +\n" ">> > drivers/peci/controller/peci-aspeed.c | 501 ++++++++++++++++++++++++++\n" ">> > 6 files changed, 534 insertions(+)\n" ">> > create mode 100644 drivers/peci/controller/Kconfig\n" @@ -36,30 +63,30 @@ ">> > index 47411e2b6336..4ba874afa2fa 100644\n" ">> > --- a/MAINTAINERS\n" ">> > +++ b/MAINTAINERS\n" - ">> > @@ -2865,6 +2865,15 @@ S:???????Maintained\n" - ">> > F:??????Documentation/hwmon/asc7621.rst\n" - ">> > F:??????drivers/hwmon/asc7621.c\n" + ">> > @@ -2865,6 +2865,15 @@ S:\302\240\302\240\302\240\302\240\302\240\302\240\302\240Maintained\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240Documentation/hwmon/asc7621.rst\n" + ">> > F:\302\240\302\240\302\240\302\240\302\240\302\240drivers/hwmon/asc7621.c\n" ">> >\n" ">> > +ASPEED PECI CONTROLLER\n" - ">> > +M:?????Iwona Winiarska <iwona.winiarska@intel.com>\n" - ">> > +M:?????Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" - ">> > +L:?????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +L:?????openbmc at lists.ozlabs.org?(moderated for non-subscribers)\n" - ">> > +S:?????Supported\n" - ">> > +F:?????Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" - ">> > +F:?????drivers/peci/controller/peci-aspeed.c\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Iwona Winiarska <iwona.winiarska@intel.com>\n" + ">> > +M:\302\240\302\240\302\240\302\240\302\240Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +L:\302\240\302\240\302\240\302\240\302\240openbmc@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" + ">> > +S:\302\240\302\240\302\240\302\240\302\240Supported\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240Documentation/devicetree/bindings/peci/peci-aspeed.yaml\n" + ">> > +F:\302\240\302\240\302\240\302\240\302\240drivers/peci/controller/peci-aspeed.c\n" ">> > +\n" ">> > ASPEED PINCTRL DRIVERS\n" - ">> > M:??????Andrew Jeffery <andrew@aj.id.au>\n" - ">> > L:??????linux-aspeed at lists.ozlabs.org?(moderated for non-subscribers)\n" + ">> > M:\302\240\302\240\302\240\302\240\302\240\302\240Andrew Jeffery <andrew@aj.id.au>\n" + ">> > L:\302\240\302\240\302\240\302\240\302\240\302\240linux-aspeed@lists.ozlabs.org\302\240(moderated for non-subscribers)\n" ">> > diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig\n" ">> > index 601cc3c3c852..0d0ee8009713 100644\n" ">> > --- a/drivers/peci/Kconfig\n" ">> > +++ b/drivers/peci/Kconfig\n" ">> > @@ -12,3 +12,9 @@ menuconfig PECI\n" ">> >\n" - ">> > ????????? This support is also available as a module. If so, the module\n" - ">> > ????????? will be called peci.\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This support is also available as a module. If so, the module\n" + ">> > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci.\n" ">> > +\n" ">> > +if PECI\n" ">> > +\n" @@ -87,15 +114,15 @@ ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" ">> > +config PECI_ASPEED\n" - ">> > +???????tristate \"ASPEED PECI support\"\n" - ">> > +???????depends on ARCH_ASPEED || COMPILE_TEST\n" - ">> > +???????depends on OF\n" - ">> > +???????depends on HAS_IOMEM\n" - ">> > +???????help\n" - ">> > +???????? Enable this driver if you want to support ASPEED PECI controller.\n" - ">> > +\n" - ">> > +???????? This driver can be also build as a module. If so, the module\n" - ">> > +???????? will be called peci-aspeed.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240tristate \"ASPEED PECI support\"\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on ARCH_ASPEED || COMPILE_TEST\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on OF\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240depends on HAS_IOMEM\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240help\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 Enable this driver if you want to support ASPEED PECI controller.\n" + ">> > +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 This driver can be also build as a module. If so, the module\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 will be called peci-aspeed.\n" ">> > diff --git a/drivers/peci/controller/Makefile\n" ">> > b/drivers/peci/controller/Makefile\n" ">> > new file mode 100644\n" @@ -105,7 +132,7 @@ ">> > @@ -0,0 +1,3 @@\n" ">> > +# SPDX-License-Identifier: GPL-2.0-only\n" ">> > +\n" - ">> > +obj-$(CONFIG_PECI_ASPEED)??????+= peci-aspeed.o\n" + ">> > +obj-$(CONFIG_PECI_ASPEED)\302\240\302\240\302\240\302\240\302\240\302\240+= peci-aspeed.o\n" ">> > diff --git a/drivers/peci/controller/peci-aspeed.c\n" ">> > b/drivers/peci/controller/peci-aspeed.c\n" ">> > new file mode 100644\n" @@ -134,11 +161,11 @@ ">> > +\n" ">> > +/* ASPEED PECI Registers */\n" ">> > +/* Control Register */\n" - ">> > +#define ASPEED_PECI_CTRL???????????????????????0x00\n" - ">> > +#define?? ASPEED_PECI_CTRL_SAMPLING_MASK???????GENMASK(19, 16)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_MASK??????GENMASK(13, 12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_COUNT?????BIT(12)\n" - ">> > +#define?? ASPEED_PECI_CTRL_READ_MODE_DBG???????BIT(13)\n" + ">> > +#define ASPEED_PECI_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x00\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_SAMPLING_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(19, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(13, 12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_COUNT\302\240\302\240\302\240\302\240\302\240BIT(12)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_READ_MODE_DBG\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(13)\n" ">>\n" ">> Nitpick: might be nice to keep things in a consistent descending order\n" ">> here (13 then 12).\n" @@ -146,17 +173,17 @@ ">\n" ">Sure, I'll change it in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_SOURCE_MASK?????BIT(11)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_SOURCE_MASK\302\240\302\240\302\240\302\240\302\240BIT(11)\n" ">>\n" ">> _MASK suffix seems out of place on this one.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_CTRL_CLK_DIV_MASK????????????????GENMASK(10, 8)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_OUT??????????BIT(7)\n" - ">> > +#define?? ASPEED_PECI_CTRL_INVERT_IN???????????BIT(6)\n" - ">> > +#define?? ASPEED_PECI_CTRL_BUS_CONTENT_EN??????BIT(5)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_CLK_DIV_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(10, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_OUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(7)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_INVERT_IN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(6)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_BUS_CONTENT_EN\302\240\302\240\302\240\302\240\302\240\302\240BIT(5)\n" ">>\n" ">> It *is* already kind of a long macro name, but abbreviating \"contention\"\n" ">> to \"content\" seems a bit confusing; I'd suggest keeping the extra three\n" @@ -166,29 +193,29 @@ ">\n" ">You're right - it'll be renamed properly in v2.\n" ">\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_EN?????????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_CTRL_PECI_CLK_EN?????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CTRL_PECI_CLK_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Timing Negotiation Register */\n" - ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION?????????0x04\n" - ">> > +#define?? ASPEED_PECI_TIMING_MESSAGE_MASK??????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TIMING_ADDRESS_MASK??????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_TIMING_NEGOTIATION\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x04\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_MESSAGE_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_ADDRESS_MASK\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Command Register */\n" - ">> > +#define ASPEED_PECI_CMD????????????????????????????????0x08\n" - ">> > +#define?? ASPEED_PECI_CMD_PIN_MON??????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_CMD_STS_MASK?????????????GENMASK(27, 24)\n" - ">> > +#define???? ASPEED_PECI_CMD_STS_ADDR_T_NEGO????0x3\n" - ">> > +#define?? ASPEED_PECI_CMD_IDLE_MASK????????????\\\n" - ">> > +???????? (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" - ">> > +#define?? ASPEED_PECI_CMD_FIRE?????????????????BIT(0)\n" + ">> > +#define ASPEED_PECI_CMD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x08\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_PIN_MON\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_STS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(27, 24)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_CMD_STS_ADDR_T_NEGO\302\240\302\240\302\240\302\2400x3\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_IDLE_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\\\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 (ASPEED_PECI_CMD_STS_MASK | ASPEED_PECI_CMD_PIN_MON)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CMD_FIRE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Read/Write Length Register */\n" - ">> > +#define ASPEED_PECI_RW_LENGTH??????????????????0x0c\n" - ">> > +#define?? ASPEED_PECI_AW_FCS_EN????????????????????????BIT(31)\n" - ">> > +#define?? ASPEED_PECI_READ_LEN_MASK????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_WRITE_LEN_MASK???????????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_TAGET_ADDR_MASK??????????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_RW_LENGTH\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x0c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_AW_FCS_EN\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(31)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_READ_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_WRITE_LEN_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TAGET_ADDR_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">>\n" ">> s/TAGET/TARGET/\n" ">>\n" @@ -197,116 +224,116 @@ ">\n" ">> > +\n" ">> > +/* Expected FCS Data Register */\n" - ">> > +#define ASPEED_PECI_EXP_FCS????????????????????0x10\n" - ">> > +#define?? ASPEED_PECI_EXP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_EXP_AW_FCS_AUTO_MASK?????GENMASK(15, 8)\n" - ">> > +#define?? ASPEED_PECI_EXP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_EXP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x10\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_AW_FCS_AUTO_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(15, 8)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_EXP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Captured FCS Data Register */\n" - ">> > +#define ASPEED_PECI_CAP_FCS????????????????????0x14\n" - ">> > +#define?? ASPEED_PECI_CAP_READ_FCS_MASK????????????????GENMASK(23, 16)\n" - ">> > +#define?? ASPEED_PECI_CAP_WRITE_FCS_MASK???????GENMASK(7, 0)\n" + ">> > +#define ASPEED_PECI_CAP_FCS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x14\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_READ_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(23, 16)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_CAP_WRITE_FCS_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(7, 0)\n" ">> > +\n" ">> > +/* Interrupt Register */\n" - ">> > +#define ASPEED_PECI_INT_CTRL???????????????????0x18\n" - ">> > +#define?? ASPEED_PECI_TIMING_NEGO_SEL_MASK?????GENMASK(31, 30)\n" - ">> > +#define???? ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO???0\n" - ">> > +#define???? ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO???1\n" - ">> > +#define???? ASPEED_PECI_MESSAGE_NEGO???????????2\n" - ">> > +#define?? ASPEED_PECI_INT_MASK?????????????????GENMASK(4, 0)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_TIMEOUT??????????BIT(4)\n" - ">> > +#define?? ASPEED_PECI_INT_BUS_CONNECT??????????BIT(3)\n" + ">> > +#define ASPEED_PECI_INT_CTRL\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x18\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_TIMING_NEGO_SEL_MASK\302\240\302\240\302\240\302\240\302\240GENMASK(31, 30)\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO\302\240\302\240\302\2400\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_2ND_BIT_OF_ADDR_NEGO\302\240\302\240\302\2401\n" + ">> > +#define\302\240\302\240\302\240\302\240 ASPEED_PECI_MESSAGE_NEGO\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2402\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_MASK\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240GENMASK(4, 0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_TIMEOUT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(4)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_BUS_CONNECT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(3)\n" ">>\n" ">> s/CONNECT/CONTENTION/\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_BAD????????????BIT(2)\n" - ">> > +#define?? ASPEED_PECI_INT_W_FCS_ABORT??????????BIT(1)\n" - ">> > +#define?? ASPEED_PECI_INT_CMD_DONE?????????????BIT(0)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_BAD\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(2)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_W_FCS_ABORT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(1)\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_CMD_DONE\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240BIT(0)\n" ">> > +\n" ">> > +/* Interrupt Status Register */\n" - ">> > +#define ASPEED_PECI_INT_STS????????????????????0x1c\n" - ">> > +#define?? ASPEED_PECI_INT_TIMING_RESULT_MASK???GENMASK(29, 16)\n" - ">> > +???????? /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" + ">> > +#define ASPEED_PECI_INT_STS\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x1c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_INT_TIMING_RESULT_MASK\302\240\302\240\302\240GENMASK(29, 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /* bits[4..0]: Same bit fields in the 'Interrupt Register' */\n" ">> > +\n" ">> > +/* Rx/Tx Data Buffer Registers */\n" - ">> > +#define ASPEED_PECI_W_DATA0????????????????????0x20\n" - ">> > +#define ASPEED_PECI_W_DATA1????????????????????0x24\n" - ">> > +#define ASPEED_PECI_W_DATA2????????????????????0x28\n" - ">> > +#define ASPEED_PECI_W_DATA3????????????????????0x2c\n" - ">> > +#define ASPEED_PECI_R_DATA0????????????????????0x30\n" - ">> > +#define ASPEED_PECI_R_DATA1????????????????????0x34\n" - ">> > +#define ASPEED_PECI_R_DATA2????????????????????0x38\n" - ">> > +#define ASPEED_PECI_R_DATA3????????????????????0x3c\n" - ">> > +#define ASPEED_PECI_W_DATA4????????????????????0x40\n" - ">> > +#define ASPEED_PECI_W_DATA5????????????????????0x44\n" - ">> > +#define ASPEED_PECI_W_DATA6????????????????????0x48\n" - ">> > +#define ASPEED_PECI_W_DATA7????????????????????0x4c\n" - ">> > +#define ASPEED_PECI_R_DATA4????????????????????0x50\n" - ">> > +#define ASPEED_PECI_R_DATA5????????????????????0x54\n" - ">> > +#define ASPEED_PECI_R_DATA6????????????????????0x58\n" - ">> > +#define ASPEED_PECI_R_DATA7????????????????????0x5c\n" - ">> > +#define?? ASPEED_PECI_DATA_BUF_SIZE_MAX????????????????32\n" + ">> > +#define ASPEED_PECI_W_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x20\n" + ">> > +#define ASPEED_PECI_W_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x24\n" + ">> > +#define ASPEED_PECI_W_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x28\n" + ">> > +#define ASPEED_PECI_W_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x2c\n" + ">> > +#define ASPEED_PECI_R_DATA0\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x30\n" + ">> > +#define ASPEED_PECI_R_DATA1\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x34\n" + ">> > +#define ASPEED_PECI_R_DATA2\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x38\n" + ">> > +#define ASPEED_PECI_R_DATA3\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x3c\n" + ">> > +#define ASPEED_PECI_W_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x40\n" + ">> > +#define ASPEED_PECI_W_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x44\n" + ">> > +#define ASPEED_PECI_W_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x48\n" + ">> > +#define ASPEED_PECI_W_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x4c\n" + ">> > +#define ASPEED_PECI_R_DATA4\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x50\n" + ">> > +#define ASPEED_PECI_R_DATA5\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x54\n" + ">> > +#define ASPEED_PECI_R_DATA6\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x58\n" + ">> > +#define ASPEED_PECI_R_DATA7\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400x5c\n" + ">> > +#define\302\240\302\240 ASPEED_PECI_DATA_BUF_SIZE_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\24032\n" ">> > +\n" ">> > +/* Timing Negotiation */\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT??8\n" - ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX??????(BIT(4) - 1)\n" - ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT????????????0\n" - ">> > +#define ASPEED_PECI_CLK_DIV_MAX????????????????????????(BIT(3) - 1)\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT?????????1\n" - ">> > +#define ASPEED_PECI_MSG_TIMING_MAX?????????????(BIT(8) - 1)\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT????????????????1\n" - ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX????????????(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT\302\240\302\2408\n" + ">> > +#define ASPEED_PECI_RD_SAMPLING_POINT_MAX\302\240\302\240\302\240\302\240\302\240\302\240(BIT(4) - 1)\n" + ">> > +#define ASPEED_PECI_CLK_DIV_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2400\n" + ">> > +#define ASPEED_PECI_CLK_DIV_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(3) - 1)\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_MSG_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_DEFAULT\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\2401\n" + ">> > +#define ASPEED_PECI_ADDR_TIMING_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(BIT(8) - 1)\n" ">> > +\n" ">> > +/* Timeout */\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US??????(50 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US?????(10 * USEC_PER_MSEC)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT?????(1000)\n" - ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX?????????(1000)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_TIMEOUT_US\302\240\302\240\302\240\302\240\302\240\302\240(50 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_IDLE_CHECK_INTERVAL_US\302\240\302\240\302\240\302\240\302\240(10 * USEC_PER_MSEC)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT\302\240\302\240\302\240\302\240\302\240(1000)\n" + ">> > +#define ASPEED_PECI_CMD_TIMEOUT_MS_MAX\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240(1000)\n" ">> > +\n" ">> > +struct aspeed_peci {\n" - ">> > +???????struct peci_controller controller;\n" - ">> > +???????struct device *dev;\n" - ">> > +???????void __iomem *base;\n" - ">> > +???????struct clk *clk;\n" - ">> > +???????struct reset_control *rst;\n" - ">> > +???????int irq;\n" - ">> > +???????spinlock_t lock; /* to sync completion status handling */\n" - ">> > +???????struct completion xfer_complete;\n" - ">> > +???????u32 status;\n" - ">> > +???????u32 cmd_timeout_ms;\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct peci_controller controller;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct device *dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240void __iomem *base;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct clk *clk;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct reset_control *rst;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spinlock_t lock; /* to sync completion status handling */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct completion xfer_complete;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_timeout_ms;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" ">> > +};\n" ">> > +\n" ">> > +static inline struct aspeed_peci *to_aspeed_peci(struct peci_controller *a)\n" ">> > +{\n" - ">> > +???????return container_of(a, struct aspeed_peci, controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return container_of(a, struct aspeed_peci, controller);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_init_regs(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 val;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 val;\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK,\n" ">> > ASPEED_PECI_CLK_DIV_DEFAULT);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" - ">> > +???????/*\n" - ">> > +??????? * Timing negotiation period setting.\n" - ">> > +??????? * The unit of the programmed value is 4 times of PECI clock period.\n" - ">> > +??????? */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Timing negotiation period setting.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * The unit of the programmed value is 4 times of PECI clock period.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_MESSAGE_MASK, priv->msg_timing);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_TIMING_ADDRESS_MASK, priv-\n" ">> > >addr_timing);\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_TIMING_NEGOTIATION);\n" ">> > +\n" - ">> > +???????/* Clear interrupts */\n" - ">> > +???????val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Clear interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = readl(priv->base + ASPEED_PECI_INT_STS) |\n" ">> > ASPEED_PECI_INT_MASK;\n" ">>\n" ">> This should be & instead of |, I'm guessing?\n" @@ -322,66 +349,66 @@ "pattern they provide on a read is probably okay (I'm having trouble\n" "finding any explicit statement either way in the datasheet I've got).\n" "\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_STS);\n" ">> > +\n" - ">> > +???????/* Set timing negotiation mode and enable interrupts */\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Set timing negotiation mode and enable interrupts */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_TIMING_NEGO_SEL_MASK,\n" ">> > ASPEED_PECI_1ST_BIT_OF_ADDR_NEGO);\n" - ">> > +???????val |= ASPEED_PECI_INT_MASK;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_INT_MASK;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_INT_CTRL);\n" ">> > +\n" - ">> > +???????val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val = FIELD_PREP(ASPEED_PECI_CTRL_SAMPLING_MASK, priv-\n" ">> > >rd_sampling_point);\n" - ">> > +???????val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_EN;\n" - ">> > +???????val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" - ">> > +???????writel(val, priv->base + ASPEED_PECI_CTRL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= FIELD_PREP(ASPEED_PECI_CTRL_CLK_DIV_MASK, priv->clk_div);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240val |= ASPEED_PECI_CTRL_PECI_CLK_EN;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(val, priv->base + ASPEED_PECI_CTRL);\n" ">> > +}\n" ">> > +\n" ">> > +static inline int aspeed_peci_check_idle(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 cmd_sts = readl(priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (FIELD_GET(ASPEED_PECI_CMD_STS_MASK, cmd_sts) ==\n" ">> > ASPEED_PECI_CMD_STS_ADDR_T_NEGO)\n" - ">> > +???????????????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" - ">> > +???????????????????????????????? cmd_sts,\n" - ">> > +???????????????????????????????? !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" - ">> > +???????????????????????????????? ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return readl_poll_timeout(priv->base + ASPEED_PECI_CMD,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 cmd_sts,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 !(cmd_sts & ASPEED_PECI_CMD_IDLE_MASK),\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_INTERVAL_US,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 ASPEED_PECI_IDLE_CHECK_TIMEOUT_US);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_xfer(struct peci_controller *controller,\n" - ">> > +?????????????????????????? u8 addr, struct peci_request *req)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 u8 addr, struct peci_request *req)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = to_aspeed_peci(controller);\n" - ">> > +???????unsigned long flags, timeout = msecs_to_jiffies(priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = to_aspeed_peci(controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240unsigned long flags, timeout = msecs_to_jiffies(priv-\n" ">> > >cmd_timeout_ms);\n" - ">> > +???????u32 peci_head;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 peci_head;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" - ">> > +?????????? req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" - ">> > +???????????????return -EINVAL;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX ||\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > ASPEED_PECI_DATA_BUF_SIZE_MAX)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EINVAL;\n" ">> > +\n" - ">> > +???????/* Check command sts and bus idle state */\n" - ">> > +???????ret = aspeed_peci_check_idle(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret; /* -ETIMEDOUT */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/* Check command sts and bus idle state */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_check_idle(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret; /* -ETIMEDOUT */\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" - ">> > +???????reinit_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reinit_completion(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" - ">> > +?????????????????? FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_head = FIELD_PREP(ASPEED_PECI_TAGET_ADDR_MASK, addr) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_WRITE_LEN_MASK, req->tx.len) |\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 FIELD_PREP(ASPEED_PECI_READ_LEN_MASK, req->rx.len);\n" ">> > +\n" - ">> > +???????writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);\n" ">> > +\n" - ">> > +???????memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" - ">> > +?????????????????? req->tx.len > 16 ? 16 : req->tx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA0, req->tx.buf,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len > 16 ? 16 : req->tx.len);\n" ">>\n" ">> min(req->tx.len, 16) for the third argument there might be a bit\n" ">> clearer.\n" @@ -389,81 +416,81 @@ ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->tx.len > 16)\n" - ">> > +???????????????memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->tx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_toio(priv->base + ASPEED_PECI_W_DATA4, req->tx.buf +\n" ">> > 16,\n" - ">> > +?????????????????????????? req->tx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->tx.len - 16);\n" ">> > +\n" - ">> > +???????dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" - ">> > +???????print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"HEAD : 0x%08x\\n\", peci_head);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"TX : \", DUMP_PREFIX_NONE, req->tx.buf, req-\n" ">> > >tx.len);\n" ">> > +\n" - ">> > +???????priv->status = 0;\n" - ">> > +???????writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status = 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????ret = wait_for_completion_interruptible_timeout(&priv-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = wait_for_completion_interruptible_timeout(&priv-\n" ">> > >xfer_complete, timeout);\n" - ">> > +???????if (ret < 0)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret < 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????if (ret == 0) {\n" - ">> > +???????????????dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" - ">> > +???????????????return -ETIMEDOUT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret == 0) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"Timeout waiting for a response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ETIMEDOUT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_lock_irqsave(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_irqsave(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????writel(0, priv->base + ASPEED_PECI_CMD);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(0, priv->base + ASPEED_PECI_CMD);\n" ">> > +\n" - ">> > +???????if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" - ">> > +???????????????spin_unlock_irqrestore(&priv->lock, flags);\n" - ">> > +???????????????dev_dbg(priv->dev, \"No valid response!\\n\");\n" - ">> > +???????????????return -EIO;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (priv->status != ASPEED_PECI_INT_CMD_DONE) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg(priv->dev, \"No valid response!\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -EIO;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????spin_unlock_irqrestore(&priv->lock, flags);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock_irqrestore(&priv->lock, flags);\n" ">> > +\n" - ">> > +???????memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" - ">> > +???????????????????? req->rx.len > 16 ? 16 : req->rx.len);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf, priv->base + ASPEED_PECI_R_DATA0,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len > 16 ? 16 : req->rx.len);\n" ">>\n" ">> Likewise, min(req->rx.len, 16) here.\n" ">\n" ">Ack.\n" ">\n" ">>\n" - ">> > +???????if (req->rx.len > 16)\n" - ">> > +???????????????memcpy_fromio(req->rx.buf + 16, priv->base +\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (req->rx.len > 16)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240memcpy_fromio(req->rx.buf + 16, priv->base +\n" ">> > ASPEED_PECI_R_DATA4,\n" - ">> > +???????????????????????????? req->rx.len - 16);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 req->rx.len - 16);\n" ">> > +\n" - ">> > +???????print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240print_hex_dump_bytes(\"RX : \", DUMP_PREFIX_NONE, req->rx.buf, req-\n" ">> > >rx.len);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = arg;\n" - ">> > +???????u32 status;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = arg;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 status;\n" ">> > +\n" - ">> > +???????spin_lock(&priv->lock);\n" - ">> > +???????status = readl(priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????writel(status, priv->base + ASPEED_PECI_INT_STS);\n" - ">> > +???????priv->status |= (status & ASPEED_PECI_INT_MASK);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240status = readl(priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240writel(status, priv->base + ASPEED_PECI_INT_STS);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->status |= (status & ASPEED_PECI_INT_MASK);\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * In most cases, interrupt bits will be set one by one but also\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * In most cases, interrupt bits will be set one by one but also\n" ">> > note\n" - ">> > +??????? * that multiple interrupt bits could be set at the same time.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * that multiple interrupt bits could be set at the same time.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_TIMEOUT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_TIMEOUT\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_BUS_CONNECT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_BUS_CONNECT\\n\");\n" ">>\n" ">> s/CONNECT/CONTENTION/ here too (in the message string).\n" @@ -472,20 +499,20 @@ ">\n" ">>\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_BAD)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_BAD\\n\");\n" ">> > +\n" - ">> > +???????if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" - ">> > +???????????????dev_dbg_ratelimited(priv->dev,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_W_FCS_ABORT)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_dbg_ratelimited(priv->dev,\n" ">> > \"ASPEED_PECI_INT_W_FCS_ABORT\\n\");\n" ">>\n" ">> Bus contention can of course arise legitimately, and I suppose an\n" ">> offline host CPU might result in a timeout, so dbg seems fine for those\n" ">> (though as Dan suggests, making some counters available seems like a\n" - ">> good idea, especially for contention).? Are the FCS error cases\n" + ">> good idea, especially for contention).\302\240 Are the FCS error cases\n" ">> significant enough to warrant something less likely to go unnoticed\n" - ">> though?? (e.g. dev_warn_ratelimited() or something?)\n" + ">> though?\302\240 (e.g. dev_warn_ratelimited() or something?)\n" ">\n" ">It's similar story for FCS errors (can occur legitimately).\n" ">We can hit ASPEED_PECI_INT_W_FCS_BAD in completely valid scenarios, e.g.\n" @@ -505,37 +532,37 @@ "\n" ">>\n" ">> > +\n" - ">> > +???????/*\n" - ">> > +??????? * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240/*\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * All commands should be ended up with a ASPEED_PECI_INT_CMD_DONE\n" ">> > bit\n" - ">> > +??????? * set even in an error case.\n" - ">> > +??????? */\n" - ">> > +???????if (status & ASPEED_PECI_INT_CMD_DONE)\n" - ">> > +???????????????complete(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * set even in an error case.\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (status & ASPEED_PECI_INT_CMD_DONE)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240complete(&priv->xfer_complete);\n" ">> > +\n" - ">> > +???????spin_unlock(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_unlock(&priv->lock);\n" ">> > +\n" - ">> > +???????return IRQ_HANDLED;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return IRQ_HANDLED;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_clock_divider(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 clk_div;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"clock-divider\",\n" ">> > &clk_div);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (clk_div > ASPEED_PECI_CLK_DIV_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid clock-divider: %u, Using\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 clk_div, ASPEED_PECI_CLK_DIV_DEFAULT);\n" ">> > +\n" - ">> > +???????????????clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_div = ASPEED_PECI_CLK_DIV_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->clk_div = clk_div;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk_div = clk_div;\n" ">> > +}\n" ">> > +\n" ">>\n" @@ -562,152 +589,152 @@ ">>\n" ">> > +static void __sanitize_msg_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 msg_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"msg-timing\",\n" ">> > &msg_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (msg_timing > ASPEED_PECI_MSG_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid msg-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 msg_timing, ASPEED_PECI_MSG_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240msg_timing = ASPEED_PECI_MSG_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->msg_timing = msg_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->msg_timing = msg_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_addr_timing(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 addr_timing;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"addr-timing\",\n" ">> > &addr_timing);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (addr_timing > ASPEED_PECI_ADDR_TIMING_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid addr-timing : %u, Use default :\n" ">> > %u\\n\",\n" - ">> > +??????????????????????? addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 addr_timing, ASPEED_PECI_ADDR_TIMING_DEFAULT);\n" ">> > +\n" - ">> > +???????????????addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240addr_timing = ASPEED_PECI_ADDR_TIMING_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->addr_timing = addr_timing;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->addr_timing = addr_timing;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_rd_sampling_point(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 rd_sampling_point;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"rd-sampling-point\",\n" ">> > &rd_sampling_point);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (rd_sampling_point > ASPEED_PECI_RD_SAMPLING_POINT_MAX) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid rd-sampling-point: %u, Use\n" ">> > default : %u\\n\",\n" - ">> > +??????????????????????? rd_sampling_point,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 rd_sampling_point,\n" ">> > ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT);\n" ">> > +\n" - ">> > +???????????????rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240rd_sampling_point = ASPEED_PECI_RD_SAMPLING_POINT_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->rd_sampling_point = rd_sampling_point;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rd_sampling_point = rd_sampling_point;\n" ">> > +}\n" ">> > +\n" ">> > +static void __sanitize_cmd_timeout(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????u32 timeout;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240u32 timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = device_property_read_u32(priv->dev, \"cmd-timeout-ms\",\n" ">> > &timeout);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240} else if (timeout > ASPEED_PECI_CMD_TIMEOUT_MS_MAX || timeout == 0)\n" ">> > {\n" - ">> > +???????????????dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_warn(priv->dev, \"Invalid cmd-timeout-ms: %u, Use\n" ">> > default: %u\\n\",\n" - ">> > +??????????????????????? timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 timeout, ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT);\n" ">> > +\n" - ">> > +???????????????timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240timeout = ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????priv->cmd_timeout_ms = timeout;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->cmd_timeout_ms = timeout;\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_device_property_sanitize(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????__sanitize_clock_divider(priv);\n" - ">> > +???????__sanitize_msg_timing(priv);\n" - ">> > +???????__sanitize_addr_timing(priv);\n" - ">> > +???????__sanitize_rd_sampling_point(priv);\n" - ">> > +???????__sanitize_cmd_timeout(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_clock_divider(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_msg_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_addr_timing(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_rd_sampling_point(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240__sanitize_cmd_timeout(priv);\n" ">> > +}\n" ">> > +\n" ">> > +static void aspeed_peci_disable_clk(void *data)\n" ">> > +{\n" - ">> > +???????clk_disable_unprepare(data);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240clk_disable_unprepare(data);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv)\n" ">> > +{\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv->clk = devm_clk_get(priv->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->clk))\n" - ">> > +???????????????return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->clk = devm_clk_get(priv->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->clk))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return dev_err_probe(priv->dev, PTR_ERR(priv->clk), \"Failed\n" ">> > to get clk source\\n\");\n" ">> > +\n" - ">> > +???????ret = clk_prepare_enable(priv->clk);\n" - ">> > +???????if (ret) {\n" - ">> > +???????????????dev_err(priv->dev, \"Failed to enable clock\\n\");\n" - ">> > +???????????????return ret;\n" - ">> > +???????}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = clk_prepare_enable(priv->clk);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(priv->dev, \"Failed to enable clock\\n\");\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" ">> > +\n" - ">> > +???????ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_add_action_or_reset(priv->dev, aspeed_peci_disable_clk,\n" ">> > priv->clk);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????aspeed_peci_device_property_sanitize(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_device_property_sanitize(priv);\n" ">> > +\n" - ">> > +???????aspeed_peci_init_regs(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240aspeed_peci_init_regs(priv);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_probe(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv;\n" - ">> > +???????int ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240int ret;\n" ">> > +\n" - ">> > +???????priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" - ">> > +???????if (!priv)\n" - ">> > +???????????????return -ENOMEM;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return -ENOMEM;\n" ">> > +\n" - ">> > +???????priv->dev = &pdev->dev;\n" - ">> > +???????dev_set_drvdata(priv->dev, priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->dev = &pdev->dev;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_set_drvdata(priv->dev, priv);\n" ">> > +\n" - ">> > +???????priv->base = devm_platform_ioremap_resource(pdev, 0);\n" - ">> > +???????if (IS_ERR(priv->base))\n" - ">> > +???????????????return PTR_ERR(priv->base);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->base = devm_platform_ioremap_resource(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->base))\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->base);\n" ">> > +\n" - ">> > +???????priv->irq = platform_get_irq(pdev, 0);\n" - ">> > +???????if (!priv->irq)\n" - ">> > +???????????????return priv->irq;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->irq = platform_get_irq(pdev, 0);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (!priv->irq)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return priv->irq;\n" ">> > +\n" - ">> > +???????ret = devm_request_irq(&pdev->dev, priv->irq,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = devm_request_irq(&pdev->dev, priv->irq,\n" ">> > aspeed_peci_irq_handler,\n" - ">> > +????????????????????????????? 0, \"peci-aspeed-irq\", priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 0, \"peci-aspeed-irq\", priv);\n" ">>\n" - ">> Might as well drop the \"-irq\" suffix here?? (Seems a bit redundant, and\n" + ">> Might as well drop the \"-irq\" suffix here?\302\240 (Seems a bit redundant, and\n" ">> a quick glance through /proc/interrupts on the systems I have at hand\n" ">> doesn't show anything else following that convention.)\n" ">\n" @@ -717,54 +744,54 @@ ">-Iwona\n" ">\n" ">>\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????init_completion(&priv->xfer_complete);\n" - ">> > +???????spin_lock_init(&priv->lock);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240init_completion(&priv->xfer_complete);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240spin_lock_init(&priv->lock);\n" ">> > +\n" - ">> > +???????priv->controller.xfer = aspeed_peci_xfer;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->controller.xfer = aspeed_peci_xfer;\n" ">> > +\n" - ">> > +???????priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" - ">> > +???????if (IS_ERR(priv->rst)) {\n" - ">> > +???????????????dev_err(&pdev->dev, \"Missing or invalid reset controller\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240priv->rst = devm_reset_control_get(&pdev->dev, NULL);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (IS_ERR(priv->rst)) {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240dev_err(&pdev->dev, \"Missing or invalid reset controller\n" ">> > entry\\n\");\n" - ">> > +???????????????return PTR_ERR(priv->rst);\n" - ">> > +???????}\n" - ">> > +???????reset_control_deassert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return PTR_ERR(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240}\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_deassert(priv->rst);\n" ">> > +\n" - ">> > +???????ret = aspeed_peci_init_ctrl(priv);\n" - ">> > +???????if (ret)\n" - ">> > +???????????????return ret;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240ret = aspeed_peci_init_ctrl(priv);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240if (ret)\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240return ret;\n" ">> > +\n" - ">> > +???????return peci_controller_add(&priv->controller, priv->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return peci_controller_add(&priv->controller, priv->dev);\n" ">> > +}\n" ">> > +\n" ">> > +static int aspeed_peci_remove(struct platform_device *pdev)\n" ">> > +{\n" - ">> > +???????struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev);\n" ">> > +\n" - ">> > +???????peci_controller_remove(&priv->controller);\n" - ">> > +???????reset_control_assert(priv->rst);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240peci_controller_remove(&priv->controller);\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240reset_control_assert(priv->rst);\n" ">> > +\n" - ">> > +???????return 0;\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240return 0;\n" ">> > +}\n" ">> > +\n" ">> > +static const struct of_device_id aspeed_peci_of_table[] = {\n" - ">> > +???????{ .compatible = \"aspeed,ast2400-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2500-peci\", },\n" - ">> > +???????{ .compatible = \"aspeed,ast2600-peci\", },\n" - ">> > +???????{ }\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2400-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2500-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ .compatible = \"aspeed,ast2600-peci\", },\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240{ }\n" ">> > +};\n" ">> > +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table);\n" ">> > +\n" ">> > +static struct platform_driver aspeed_peci_driver = {\n" - ">> > +???????.probe? = aspeed_peci_probe,\n" - ">> > +???????.remove = aspeed_peci_remove,\n" - ">> > +???????.driver = {\n" - ">> > +???????????????.name?????????? = \"peci-aspeed\",\n" - ">> > +???????????????.of_match_table = aspeed_peci_of_table,\n" - ">> > +???????},\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.probe\302\240 = aspeed_peci_probe,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.remove = aspeed_peci_remove,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240.driver = {\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.name\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 = \"peci-aspeed\",\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240.of_match_table = aspeed_peci_of_table,\n" + ">> > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240},\n" ">> > +};\n" ">> > +module_platform_driver(aspeed_peci_driver);\n" ">> > +\n" @@ -775,6 +802,10 @@ ">> > +MODULE_IMPORT_NS(PECI);\n" ">> > --\n" ">> > 2.31.1\n" - > + ">\n" + "_______________________________________________\n" + "linux-arm-kernel mailing list\n" + "linux-arm-kernel@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -4fcca7229ab842a56ccc7dac79d6a2bb35c1843d0d5ce7298682d7796c5ddef7 +6733504c9db8ffc26b42d42420b6cbbdd4543925b0ad19e885ad9261cf7cffaa
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