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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id q23sm143022lfp.169.2021.08.04.02.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 02:25:52 -0700 (PDT) Date: Wed, 4 Aug 2021 11:25:52 +0200 From: "Edgar E. Iglesias" To: Richard Henderson Subject: Re: [PATCH v2 06/55] target/microblaze: Do not set MO_ALIGN for user-only Message-ID: <20210804092552.GE3586016@toto> References: <20210803041443.55452-1-richard.henderson@linaro.org> <20210803041443.55452-7-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210803041443.55452-7-richard.henderson@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x22e.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=2.896, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Aug 02, 2021 at 06:13:54PM -1000, Richard Henderson wrote: > The kernel will fix up unaligned accesses, so emulate that > by allowing unaligned accesses to succeed. Reviewed-by: Edgar E. Iglesias > > Cc: Edgar E. Iglesias > Signed-off-by: Richard Henderson > --- > target/microblaze/translate.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index a14ffed784..ef44bca2fd 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) > } > #endif > > +#ifndef CONFIG_USER_ONLY > static void record_unaligned_ess(DisasContext *dc, int rd, > MemOp size, bool store) > { > @@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd, > > tcg_set_insn_start_param(dc->insn_start, 1, iflags); > } > +#endif > > static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, > int mem_index, bool rev) > @@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, > } > } > > + /* > + * For system mode, enforce alignment if the cpu configuration > + * requires it. For user-mode, the Linux kernel will have fixed up > + * any unaligned access, so emulate that by *not* setting MO_ALIGN. > + */ > +#ifndef CONFIG_USER_ONLY > if (size > MO_8 && > (dc->tb_flags & MSR_EE) && > dc->cfg->unaligned_exceptions) { > record_unaligned_ess(dc, rd, size, false); > mop |= MO_ALIGN; > } > +#endif > > tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); > > @@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop, > } > } > > + /* > + * For system mode, enforce alignment if the cpu configuration > + * requires it. For user-mode, the Linux kernel will have fixed up > + * any unaligned access, so emulate that by *not* setting MO_ALIGN. > + */ > +#ifndef CONFIG_USER_ONLY > if (size > MO_8 && > (dc->tb_flags & MSR_EE) && > dc->cfg->unaligned_exceptions) { > record_unaligned_ess(dc, rd, size, true); > mop |= MO_ALIGN; > } > +#endif > > tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); > > -- > 2.25.1 >