From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40CD2C4338F for ; Fri, 6 Aug 2021 18:09:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 107A460EBC for ; Fri, 6 Aug 2021 18:09:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbhHFSJe convert rfc822-to-8bit (ORCPT ); Fri, 6 Aug 2021 14:09:34 -0400 Received: from relay2-d.mail.gandi.net ([217.70.183.194]:58793 "EHLO relay2-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230109AbhHFSJd (ORCPT ); Fri, 6 Aug 2021 14:09:33 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id 4914A40005; Fri, 6 Aug 2021 18:09:14 +0000 (UTC) Date: Fri, 6 Aug 2021 20:09:13 +0200 From: Miquel Raynal To: Keguang Zhang Cc: linux-mtd@lists.infradead.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Weinberger , Vignesh Raghavendra , Boris Brezillon Subject: Re: [PATCH V5 RESEND] mtd: rawnand: Add Loongson1 NAND driver Message-ID: <20210806200913.0a04c71c@xps13> In-Reply-To: <20210520224213.7907-1-keguang.zhang@gmail.com> References: <20210520224213.7907-1-keguang.zhang@gmail.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Hi Keguang, Sorry again for the very late review, here are my comments. Keguang Zhang wrote on Fri, 21 May 2021 06:42:13 +0800: > From: Kelvin Cheung > > This patch adds NAND driver for Loongson1B. > > Signed-off-by: Kelvin Cheung > --- > V4 -> V5: > Update the driver to fit the raw NAND framework. > Implement exec_op() instead of legacy cmdfunc(). > Use dma_request_chan() instead of dma_request_channel(). > Some minor fixes and cleanups. > V3 -> V4: > Retrieve the controller from nand_hw_control. > V2 -> V3: > Replace __raw_readl/__raw_writel with readl/writel. > Split ls1x_nand into two structures: ls1x_nand_chip and > ls1x_nand_controller. > V1 -> V2: > Modify the dependency in Kconfig due to the changes of DMA > module. > --- > drivers/mtd/nand/raw/Kconfig | 8 + > drivers/mtd/nand/raw/Makefile | 1 + > drivers/mtd/nand/raw/loongson1_nand.c | 770 ++++++++++++++++++++++++++ > 3 files changed, 779 insertions(+) > create mode 100644 drivers/mtd/nand/raw/loongson1_nand.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index 30f061939560..63402e335df4 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -453,6 +453,14 @@ config MTD_NAND_ROCKCHIP > NFC v800: RK3308, RV1108 > NFC v900: PX30, RK3326 > > +config MTD_NAND_LOONGSON1 > + tristate "Support for Loongson1 SoC NAND controller" Can you please match the style for the titles? > + depends on MACH_LOONGSON32 || CROSS_COMPILE > + select MTD_NAND_ECC_SW_HAMMING > + select LOONGSON1_DMA Maybe this should be a depends on? > + help > + Enables support for NAND controller on Loongson1 SoCs. > + > comment "Misc" > > config MTD_SM_COMMON > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > index d011c6c53f8f..50a51ad6ec21 100644 > --- a/drivers/mtd/nand/raw/Makefile > +++ b/drivers/mtd/nand/raw/Makefile > @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o > obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o > obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o > obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o > +obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1_nand.o > > nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o > nand-objs += nand_onfi.o > diff --git a/drivers/mtd/nand/raw/loongson1_nand.c b/drivers/mtd/nand/raw/loongson1_nand.c > new file mode 100644 > index 000000000000..b06e36ec32da > --- /dev/null > +++ b/drivers/mtd/nand/raw/loongson1_nand.c > @@ -0,0 +1,770 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * NAND Flash Driver for Loongson 1 SoC > + * > + * Copyright (C) 2015-2021 Zhang, Keguang > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Loongson 1 NAND Register Definitions */ > +#define NAND_CMD 0x0 > +#define NAND_ADDR1 0x4 > +#define NAND_ADDR2 0x8 > +#define NAND_TIMING 0xc > +#define NAND_IDL 0x10 > +#define NAND_IDH 0x14 > +#define NAND_STATUS 0x15 > +#define NAND_PARAM 0x18 > +#define NAND_OP_NUM 0x1c > +#define NAND_CS_RDY 0x20 > + > +#define NAND_DMA_ADDR 0x40 > + > +/* NAND Command Register Bits */ > +#define OP_DONE BIT(10) > +#define OP_SPARE BIT(9) > +#define OP_MAIN BIT(8) > +#define CMD_STATUS BIT(7) > +#define CMD_RESET BIT(6) > +#define CMD_READID BIT(5) > +#define BLOCKS_ERASE BIT(4) > +#define CMD_ERASE BIT(3) > +#define CMD_WRITE BIT(2) > +#define CMD_READ BIT(1) > +#define CMD_VALID BIT(0) > + > +#define MAX_ADDR_CYC 5U > +#define MAX_ID_SIZE (NAND_STATUS - NAND_IDL) Strange. I guess you can hardcode it. > +#define SIZE_MASK GENMASK(11, 8) > + > +#define BITS_PER_WORD 32 > + > +/* macros for registers read/write */ > +#define nand_readl(nc, off) \ > + readl((nc)->reg_base + (off)) > + > +#define nand_writel(nc, off, val) \ > + writel((val), (nc)->reg_base + (off)) > + > +struct ls1x_nand_controller { > + void __iomem *reg_base; > + __le32 addr1_reg; > + __le32 addr2_reg; > + > + char *buf; > + unsigned int len; > + unsigned int rdy_timeout; > + > + /* DMA Engine stuff */ > + struct dma_chan *dma_chan; > + dma_cookie_t dma_cookie; > + struct completion dma_complete; > +}; > + > +struct ls1x_nand { > + struct device *dev; > + struct clk *clk; > + struct nand_chip chip; > + struct nand_controller controller; > + struct ls1x_nand_controller nc; > + struct plat_ls1x_nand *pdata; > +}; > + > +static void ls1x_nand_dump_regs(struct nand_chip *chip) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + > + print_hex_dump(KERN_INFO, "REG: ", DUMP_PREFIX_OFFSET, 16, 4, > + nc->reg_base, 0x44, false); > +} > + > +static void ls1x_nand_dma_callback(void *data) > +{ > + struct ls1x_nand *nand = (struct ls1x_nand *)data; > + struct ls1x_nand_controller *nc = &nand->nc; > + enum dma_status status; > + > + status = dmaengine_tx_status(nc->dma_chan, nc->dma_cookie, NULL); > + if (likely(status == DMA_COMPLETE)) > + dev_dbg(nand->dev, "DMA complete with cookie=%d\n", > + nc->dma_cookie); > + else > + dev_err(nand->dev, "DMA error with cookie=%d\n", > + nc->dma_cookie); > + > + complete(&nc->dma_complete); > +} > + > +static int ls1x_nand_dma_transfer(struct ls1x_nand *nand, bool is_write) > +{ > + struct ls1x_nand_controller *nc = &nand->nc; > + struct dma_chan *chan = nc->dma_chan; > + struct dma_async_tx_descriptor *desc; > + enum dma_data_direction data_dir = > + is_write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; > + enum dma_transfer_direction xfer_dir = > + is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; > + dma_addr_t dma_addr; > + int ret; > + > + dma_addr = dma_map_single(chan->device->dev, nc->buf, nc->len, > + data_dir); > + if (dma_mapping_error(chan->device->dev, dma_addr)) { > + dev_err(nand->dev, "failed to map DMA buffer!\n"); > + return -ENXIO; > + } > + > + desc = dmaengine_prep_slave_single(chan, dma_addr, nc->len, xfer_dir, > + DMA_PREP_INTERRUPT); > + if (!desc) { > + dev_err(nand->dev, "failed to prepare DMA descriptor!\n"); > + ret = PTR_ERR(desc); > + goto err; > + } > + desc->callback = ls1x_nand_dma_callback; > + desc->callback_param = nand; > + > + nc->dma_cookie = dmaengine_submit(desc); > + ret = dma_submit_error(nc->dma_cookie); > + if (ret) { > + dev_err(nand->dev, "failed to submit DMA descriptor!\n"); > + goto err; > + } > + > + dev_dbg(nand->dev, "issue DMA with cookie=%d\n", nc->dma_cookie); > + dma_async_issue_pending(chan); > + > + ret = wait_for_completion_timeout(&nc->dma_complete, > + msecs_to_jiffies(nc->rdy_timeout)); > + if (ret <= 0) { > + dev_err(nand->dev, "DMA timeout!\n"); > + dmaengine_terminate_all(chan); > + ret = -EIO; > + } > + ret = 0; > +err: > + dma_unmap_single(chan->device->dev, dma_addr, nc->len, data_dir); > + > + return ret; > +} > + > +static inline void ls1x_nand_parse_address(struct nand_chip *chip, > + const u8 *addrs, > + unsigned int naddrs, int cmd) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > +#if defined(CONFIG_LOONGSON1_LS1B) Please use a regular if (IS_DEFINED()) I don't like this symbol anyway, you should get this information from a compatible (like the machine compatible) not from a Kconfig symbol. > + unsigned int page_shift = chip->page_shift + 1; > +#endif > + int i; > + > + nc->addr1_reg = 0; > + nc->addr2_reg = 0; > +#if defined(CONFIG_LOONGSON1_LS1B) > + if (cmd == CMD_ERASE) { > + page_shift = chip->page_shift; > + > + for (i = 0; i < min(MAX_ADDR_CYC - 2, naddrs); i++) > + nc->addr1_reg |= > + (u32)addrs[i] << (page_shift + BITS_PER_BYTE * i); > + if (i == MAX_ADDR_CYC - 2) > + nc->addr2_reg |= > + (u32)addrs[i] >> (BITS_PER_WORD - page_shift - > + BITS_PER_BYTE * (i - 1)); > + > + return; > + } > + > + for (i = 0; i < min(2U, naddrs); i++) > + nc->addr1_reg |= (u32)addrs[i] << BITS_PER_BYTE * i; > + for (i = 2; i < min(MAX_ADDR_CYC, naddrs); i++) > + nc->addr1_reg |= > + (u32)addrs[i] << (page_shift + BITS_PER_BYTE * (i - 2)); > + if (i == MAX_ADDR_CYC) > + nc->addr2_reg |= > + (u32)addrs[i] >> (BITS_PER_WORD - page_shift - > + BITS_PER_BYTE * (i - 1)); > +#elif defined(CONFIG_LOONGSON1_LS1C) > + if (cmd == CMD_ERASE) { > + for (i = 0; i < min(MAX_ADDR_CYC, naddrs); i++) > + nc->addr2_reg |= (u32)addrs[i] << BITS_PER_BYTE * i; > + > + return; > + } > + > + for (i = 0; i < min(MAX_ADDR_CYC, naddrs); i++) { > + if (i < 2) > + nc->addr1_reg |= (u32)addrs[i] << BITS_PER_BYTE * i; > + else > + nc->addr2_reg |= > + (u32)addrs[i] << BITS_PER_BYTE * (i - 2); > + } > +#endif > +} > + > +static int ls1x_nand_set_controller(struct nand_chip *chip, > + const struct nand_subop *subop, int cmd) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + unsigned int op_id; > + > + nc->buf = NULL; > + nc->len = 0; > + nc->rdy_timeout = 0; > + > + for (op_id = 0; op_id < subop->ninstrs; op_id++) { > + const struct nand_op_instr *instr = &subop->instrs[op_id]; > + unsigned int offset, naddrs; > + const u8 *addrs; > + > + switch (instr->type) { > + case NAND_OP_CMD_INSTR: > + break; This is very suspicious. You should definitely do something with the command bytes, you should not guess the commands based on the format of the operation. > + case NAND_OP_ADDR_INSTR: > + offset = nand_subop_get_addr_start_off(subop, op_id); > + naddrs = nand_subop_get_num_addr_cyc(subop, op_id); > + addrs = &instr->ctx.addr.addrs[offset]; > + > + ls1x_nand_parse_address(chip, addrs, naddrs, cmd); > + /* set NAND address */ > + nand_writel(nc, NAND_ADDR1, nc->addr1_reg); > + nand_writel(nc, NAND_ADDR2, nc->addr2_reg); > + break; > + case NAND_OP_DATA_IN_INSTR: > + offset = nand_subop_get_data_start_off(subop, op_id); > + nc->len = nand_subop_get_data_len(subop, op_id); > + nc->buf = instr->ctx.data.buf.in + offset; > + > + if (!IS_ALIGNED(nc->len, chip->buf_align) || > + !IS_ALIGNED((unsigned int)nc->buf, chip->buf_align)) > + return -ENOTSUPP; > + /* set NAND data length */ > + nand_writel(nc, NAND_OP_NUM, nc->len); > + break; > + case NAND_OP_DATA_OUT_INSTR: > + offset = nand_subop_get_data_start_off(subop, op_id); > + nc->len = nand_subop_get_data_len(subop, op_id); > + nc->buf = (void *)instr->ctx.data.buf.out + offset; > + > + if (!IS_ALIGNED(nc->len, chip->buf_align) || > + !IS_ALIGNED((unsigned int)nc->buf, chip->buf_align)) > + return -ENOTSUPP; > + /* set NAND data length */ > + nand_writel(nc, NAND_OP_NUM, nc->len); > + break; > + case NAND_OP_WAITRDY_INSTR: > + nc->rdy_timeout = instr->ctx.waitrdy.timeout_ms; > + break; > + } > + } > + > + /*set NAND erase block count */ > + if (cmd & CMD_ERASE) > + nand_writel(nc, NAND_OP_NUM, 1); > + /*set NAND operation region */ Please fix all your comments in the driver, eg: /* Set NAND operation region */ > + if (nc->buf && nc->len) { > + if (nc->addr1_reg & BIT(chip->page_shift)) > + cmd |= OP_SPARE; > + else > + cmd |= OP_SPARE | OP_MAIN; Is this really needed? Can't you always stick to OP_SPARE | OP_MAIN? > + } > + > + /*set NAND command */ > + nand_writel(nc, NAND_CMD, cmd); > + /* Trigger operation */ > + nand_writel(nc, NAND_CMD, nand_readl(nc, NAND_CMD) | CMD_VALID); > + > + return 0; > +} > + > +static inline int ls1x_nand_wait_for_op_done(struct ls1x_nand_controller *nc) > +{ > + unsigned int val; > + int ret = 0; > + > + /* Wait for operation done */ > + if (nc->rdy_timeout) > + ret = readl_relaxed_poll_timeout(nc->reg_base + NAND_CMD, val, > + val & OP_DONE, 0, > + nc->rdy_timeout * 1000); > + > + return ret; > +} > + > +static int ls1x_nand_reset_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_RESET); > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) > + dev_err(nand->dev, "CMD_RESET failed! %d\n", ret); > + > + return ret; > +} > + > +static int ls1x_nand_read_id_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int idl, i; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_READID); > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) { > + dev_err(nand->dev, "CMD_READID failed! %d\n", ret); > + return ret; > + } > + > + idl = (nand_readl(nc, NAND_IDL)); Unneeded outer ( ). > + for (i = 0; i < min_t(unsigned int, nc->len, MAX_ID_SIZE); i++) The core enforces the number of data cycles to be less or equal than MAX_ID_SIZE if correctly described below (see the comment in the exec_op array) so you don't need this min_t() here. Please use { } to enclose the if/else block. > + if (i > 0) This looks very suspicious, I would expect the condition to be i < 4 > + nc->buf[i] = *((char *)&idl + 4 - i); Please rewrite this, it is hard to follow. > + else > + nc->buf[i] = (char)(nand_readl(nc, NAND_IDH)); > + > + return ret; > +} > + > +static int ls1x_nand_erase_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_ERASE); > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) > + dev_err(nand->dev, "CMD_ERASE failed! %d\n", ret); > + > + return ret; > +} > + > +static int ls1x_nand_read_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_READ); > + > + ret = ls1x_nand_dma_transfer(nand, false); Please use an intermediate variable such as bool write = false; (same below) > + if (ret) > + return ret; > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) > + dev_err(nand->dev, "CMD_READ failed! %d\n", ret); > + > + return ret; > +} > + > +static int ls1x_nand_write_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_WRITE); > + > + ret = ls1x_nand_dma_transfer(nand, true); > + if (ret) > + return ret; > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) > + dev_err(nand->dev, "CMD_WRITE failed! %d\n", ret); > + > + return ret; > +} > + > +static int ls1x_nand_read_status_exec(struct nand_chip *chip, > + const struct nand_subop *subop) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + int ret; > + > + ls1x_nand_set_controller(chip, subop, CMD_STATUS); > + > + ret = ls1x_nand_wait_for_op_done(nc); > + if (ret) { > + dev_err(nand->dev, "CMD_STATUS failed! %d\n", ret); > + return ret; > + } > + > + nc->buf[0] = nand_readl(nc, NAND_IDH) >> BITS_PER_BYTE; This looks very specific to the status cmd, which is not a valid implementation. Can you turn this function generic to any cmd+data bytes? (the number of data bytes could be different than 1). > + > + return ret; > +} > + > +static const struct nand_op_parser ls1x_nand_op_parser = NAND_OP_PARSER( > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_reset_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_read_id_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), Please use the definition used above ^ > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_erase_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_read_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_write_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDR_CYC), > + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), > + NAND_OP_PARSER_PATTERN( > + ls1x_nand_read_status_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), > + ); > + > +static int ls1x_nand_exec_op(struct nand_chip *chip, > + const struct nand_operation *op, bool check_only) > +{ > + return nand_op_parser_exec_op(chip, &ls1x_nand_op_parser, op, > + check_only); > +} > + > +static int ls1x_nand_read_subpage(struct nand_chip *chip, > + unsigned int data_offs, unsigned int readlen, > + unsigned char *bufpoi, int page) > +{ There is nothing specific to your controller in that helper, why do you need it? > + struct mtd_info *mtd = nand_to_mtd(chip); > + int start_step, end_step, num_steps, ret; > + char *p; > + int data_col_addr, i; > + int datafrag_len, eccfrag_len, aligned_len, aligned_pos; > + int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; > + int index, section = 0; > + unsigned int max_bitflips = 0; > + struct mtd_oob_region oobregion = { }; > + > + /* Read the whole page and OOB data */ > + ret = chip->ecc.read_page_raw(chip, bufpoi, 1, page); > + if (ret) > + return ret; > + > + /* Column address within the page aligned to ECC size (256bytes) */ > + start_step = data_offs / chip->ecc.size; > + end_step = (data_offs + readlen - 1) / chip->ecc.size; > + num_steps = end_step - start_step + 1; > + index = start_step * chip->ecc.bytes; > + > + /* Data size aligned to ECC ecc.size */ > + datafrag_len = num_steps * chip->ecc.size; > + eccfrag_len = num_steps * chip->ecc.bytes; > + > + data_col_addr = start_step * chip->ecc.size; > + /* If we read not a page aligned data */ > + p = bufpoi + data_col_addr; > + > + /* Calculate ECC */ > + for (i = 0; i < eccfrag_len; i += chip->ecc.bytes, p += chip->ecc.size) > + chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); > + > + ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); > + if (ret) > + return ret; > + > + aligned_pos = oobregion.offset & ~(busw - 1); > + aligned_len = eccfrag_len; > + if (oobregion.offset & (busw - 1)) > + aligned_len++; > + if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & (busw - 1)) > + aligned_len++; > + > + memcpy(&chip->oob_poi[aligned_pos], > + bufpoi + mtd->writesize + aligned_pos, aligned_len); > + > + ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, > + chip->oob_poi, index, eccfrag_len); > + if (ret) > + return ret; > + > + p = bufpoi + data_col_addr; > + for (i = 0; i < eccfrag_len; i += chip->ecc.bytes, p += chip->ecc.size) { > + int stat; > + > + stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], > + &chip->ecc.calc_buf[i]); > + if (stat) > + ls1x_nand_dump_regs(chip); > + > + if (stat == -EBADMSG && > + (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { > + /* check for empty pages with bitflips */ > + stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, > + &chip->ecc.code_buf[i], > + chip->ecc.bytes, > + NULL, 0, > + chip->ecc.strength); > + } > + > + if (stat < 0) { > + mtd->ecc_stats.failed++; > + } else { > + mtd->ecc_stats.corrected += stat; > + max_bitflips = max_t(unsigned int, max_bitflips, stat); > + } > + } > + return max_bitflips; > +} > + > +static int ls1x_nand_attach_chip(struct nand_chip *chip) > +{ > + struct ls1x_nand *nand = nand_get_controller_data(chip); > + struct ls1x_nand_controller *nc = &nand->nc; > + struct plat_ls1x_nand *pdata = nand->pdata; > + int hold_cycle = pdata->hold_cycle; > + int wait_cycle = pdata->wait_cycle; > + u64 chipsize = nanddev_target_size(&chip->base); > + int cell_size = 0; > + You should somehow be able to configure the controller to work in software mode or without ECC for debug purposes. Please add and test those two features. > + switch (chipsize) { > + case SZ_128M: > + cell_size = 0x0; > + break; > + case SZ_256M: > + cell_size = 0x1; > + break; > + case SZ_512M: > + cell_size = 0x2; > + break; > + case SZ_1G: > + cell_size = 0x3; > + break; > + case SZ_2G: > + cell_size = 0x4; > + break; > + case SZ_4G: > + cell_size = 0x5; > + break; > + case (SZ_2G * SZ_4G): /*8G */ > + cell_size = 0x6; > + break; > + case (SZ_4G * SZ_4G): /*16G */ > + cell_size = 0x7; > + break; > + default: > + dev_err(nand->dev, "unsupported chip size: %llu MB\n", > + chipsize); > + break; > + } > + > + if (hold_cycle && wait_cycle) > + nand_writel(nc, NAND_TIMING, > + (hold_cycle << BITS_PER_BYTE) | wait_cycle); > + nand_writel(nc, NAND_PARAM, > + (nand_readl(nc, NAND_PARAM) & ~SIZE_MASK) | cell_size << > + BITS_PER_BYTE); Please do this in three steps for readability: param = nand_readl() param |= cell_size... nand_writel() > + > + chip->ecc.read_page_raw = nand_monolithic_read_page_raw; > + chip->ecc.write_page_raw = nand_monolithic_write_page_raw; Nice :) > + > + return 0; > +} > + > +static const struct nand_controller_ops ls1x_nc_ops = { > + .exec_op = ls1x_nand_exec_op, > + .attach_chip = ls1x_nand_attach_chip, > +}; > + > +static void ls1x_nand_controller_cleanup(struct ls1x_nand *nand) > +{ > + if (nand->nc.dma_chan) > + dma_release_channel(nand->nc.dma_chan); > +} > + > +static int ls1x_nand_controller_init(struct ls1x_nand *nand, > + struct platform_device *pdev) > +{ > + struct ls1x_nand_controller *nc = &nand->nc; > + struct device *dev = &pdev->dev; > + struct dma_slave_config cfg; > + struct resource *res; > + int ret; > + > + nc->reg_base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(nc->reg_base)) > + return PTR_ERR(nc->reg_base); > + > + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); > + if (!res) { > + dev_err(dev, "failed to get DMA information!\n"); > + return -ENXIO; > + } > + > + nc->dma_chan = dma_request_chan(dev, res->name); > + if (!nc->dma_chan) { > + dev_err(dev, "failed to request DMA channel!\n"); > + return -EBUSY; > + } > + dev_info(dev, "got %s for %s access\n", > + dma_chan_name(nc->dma_chan), dev_name(dev)); > + > + cfg.src_addr = CPHYSADDR(nc->reg_base + NAND_DMA_ADDR); > + cfg.dst_addr = CPHYSADDR(nc->reg_base + NAND_DMA_ADDR); > + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; > + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; > + ret = dmaengine_slave_config(nc->dma_chan, &cfg); > + if (ret) { > + dev_err(dev, "failed to config DMA channel!\n"); > + dma_release_channel(nc->dma_chan); > + return ret; > + } > + > + init_completion(&nc->dma_complete); > + > + return 0; > +} > + > +static int ls1x_nand_chip_init(struct ls1x_nand *nand) > +{ > + struct nand_chip *chip = &nand->chip; > + struct mtd_info *mtd = nand_to_mtd(chip); > + struct plat_ls1x_nand *pdata = nand->pdata; > + int ret = 0; > + > + chip->controller = &nand->controller; > + chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA | NAND_BROKEN_XD; > + chip->buf_align = 16; > + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; > + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; ECC configuration should only be done in ->attach_chip(). > + nand_set_controller_data(chip, nand); > + > + mtd->dev.parent = nand->dev; > + mtd->name = "ls1x-nand"; > + mtd->owner = THIS_MODULE; > + > + ret = nand_scan(chip, 1); > + if (ret) > + return ret; > + > + chip->ecc.read_subpage = ls1x_nand_read_subpage; Do you really need this? It looks like your implementation of read_subpage is very similar to the one from the core. > + > + ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); > + if (ret) { > + dev_err(nand->dev, "failed to register MTD device! %d\n", ret); > + nand_cleanup(chip); > + } > + > + return ret; > +} > + > +static int ls1x_nand_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct plat_ls1x_nand *pdata; > + struct ls1x_nand *nand; Please use another name for the variable, "nand"/"chip" is used by the core for the nand_chip structure, for yours you can name it eg ls1x or lsnand. > + int ret; > + > + pdata = dev_get_platdata(dev); > + if (!pdata) { > + dev_err(dev, "platform data missing!\n"); > + return -EINVAL; > + } > + > + nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL); > + if (!nand) > + return -ENOMEM; > + > + nand->pdata = pdata; > + nand->dev = dev; > + nand->controller.ops = &ls1x_nc_ops; > + nand_controller_init(&nand->controller); > + > + ret = ls1x_nand_controller_init(nand, pdev); I'm not sure this deserves a helper (same for the chip init) but why not. > + if (ret) > + return ret; > + > + nand->clk = devm_clk_get(dev, pdev->name); > + if (IS_ERR(nand->clk)) { > + dev_err(dev, "failed to get %s clock!\n", pdev->name); > + return PTR_ERR(nand->clk); > + } > + clk_prepare_enable(nand->clk); > + > + ret = ls1x_nand_chip_init(nand); > + if (ret) { > + clk_disable_unprepare(nand->clk); > + goto err; > + } > + > + platform_set_drvdata(pdev, nand); > + dev_info(dev, "Loongson1 NAND driver registered\n"); I don't think this is useful, you can drop that trace. > + > + return 0; > +err: > + ls1x_nand_controller_cleanup(nand); > + return ret; > +} > + > +static int ls1x_nand_remove(struct platform_device *pdev) > +{ > + struct ls1x_nand *nand = platform_get_drvdata(pdev); > + struct nand_chip *chip = &nand->chip; > + > + mtd_device_unregister(nand_to_mtd(chip)); ret = mtd_device_unregister() WARN_ON(ret); > + nand_cleanup(chip); > + clk_disable_unprepare(nand->clk); > + ls1x_nand_controller_cleanup(nand); > + > + return 0; > +} > + > +static struct platform_driver ls1x_nand_driver = { > + .probe = ls1x_nand_probe, > + .remove = ls1x_nand_remove, > + .driver = { > + .name = "ls1x-nand", ls1x-nand-controller > + .owner = THIS_MODULE, > + }, > +}; > + > +module_platform_driver(ls1x_nand_driver); > + > +MODULE_AUTHOR("Kelvin Cheung "); > +MODULE_DESCRIPTION("Loongson1 NAND Flash driver"); > +MODULE_LICENSE("GPL"); > > base-commit: fd0d8d85f7230052e638a56d1bfea170c488e6bc Thanks, Miquèl From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=ham 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miquel.raynal@bootlin.com) by relay2-d.mail.gandi.net (Postfix) with ESMTPSA id 4914A40005; Fri, 6 Aug 2021 18:09:14 +0000 (UTC) Date: Fri, 6 Aug 2021 20:09:13 +0200 From: Miquel Raynal To: Keguang Zhang Cc: linux-mtd@lists.infradead.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Weinberger , Vignesh Raghavendra , Boris Brezillon Subject: Re: [PATCH V5 RESEND] mtd: rawnand: Add Loongson1 NAND driver Message-ID: <20210806200913.0a04c71c@xps13> In-Reply-To: <20210520224213.7907-1-keguang.zhang@gmail.com> References: <20210520224213.7907-1-keguang.zhang@gmail.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210806_110920_455239_4A7D3E27 X-CRM114-Status: GOOD ( 40.86 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgS2VndWFuZywKClNvcnJ5IGFnYWluIGZvciB0aGUgdmVyeSBsYXRlIHJldmlldywgaGVyZSBh cmUgbXkgY29tbWVudHMuCgpLZWd1YW5nIFpoYW5nIDxrZWd1YW5nLnpoYW5nQGdtYWlsLmNvbT4g d3JvdGUgb24gRnJpLCAyMSBNYXkgMjAyMQowNjo0MjoxMyArMDgwMDoKCj4gRnJvbTogS2Vsdmlu IENoZXVuZyA8a2VndWFuZy56aGFuZ0BnbWFpbC5jb20+Cj4gCj4gVGhpcyBwYXRjaCBhZGRzIE5B TkQgZHJpdmVyIGZvciBMb29uZ3NvbjFCLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEtlbHZpbiBDaGV1 bmcgPGtlZ3VhbmcuemhhbmdAZ21haWwuY29tPgo+IC0tLQo+IFY0IC0+IFY1Ogo+ICAgIFVwZGF0 ZSB0aGUgZHJpdmVyIHRvIGZpdCB0aGUgcmF3IE5BTkQgZnJhbWV3b3JrLgo+ICAgIEltcGxlbWVu dCBleGVjX29wKCkgaW5zdGVhZCBvZiBsZWdhY3kgY21kZnVuYygpLgo+ICAgIFVzZSBkbWFfcmVx dWVzdF9jaGFuKCkgaW5zdGVhZCBvZiBkbWFfcmVxdWVzdF9jaGFubmVsKCkuCj4gICAgU29tZSBt aW5vciBmaXhlcyBhbmQgY2xlYW51cHMuCj4gVjMgLT4gVjQ6Cj4gICAgUmV0cmlldmUgdGhlIGNv bnRyb2xsZXIgZnJvbSBuYW5kX2h3X2NvbnRyb2wuCj4gVjIgLT4gVjM6Cj4gICAgUmVwbGFjZSBf X3Jhd19yZWFkbC9fX3Jhd193cml0ZWwgd2l0aCByZWFkbC93cml0ZWwuCj4gICAgU3BsaXQgbHMx eF9uYW5kIGludG8gdHdvIHN0cnVjdHVyZXM6IGxzMXhfbmFuZF9jaGlwIGFuZAo+ICAgIGxzMXhf bmFuZF9jb250cm9sbGVyLgo+IFYxIC0+IFYyOgo+ICAgIE1vZGlmeSB0aGUgZGVwZW5kZW5jeSBp biBLY29uZmlnIGR1ZSB0byB0aGUgY2hhbmdlcyBvZiBETUEKPiAgICBtb2R1bGUuCj4gLS0tCj4g IGRyaXZlcnMvbXRkL25hbmQvcmF3L0tjb25maWcgICAgICAgICAgfCAgIDggKwo+ICBkcml2ZXJz L210ZC9uYW5kL3Jhdy9NYWtlZmlsZSAgICAgICAgIHwgICAxICsKPiAgZHJpdmVycy9tdGQvbmFu ZC9yYXcvbG9vbmdzb24xX25hbmQuYyB8IDc3MCArKysrKysrKysrKysrKysrKysrKysrKysrKwo+ ICAzIGZpbGVzIGNoYW5nZWQsIDc3OSBpbnNlcnRpb25zKCspCj4gIGNyZWF0ZSBtb2RlIDEwMDY0 NCBkcml2ZXJzL210ZC9uYW5kL3Jhdy9sb29uZ3NvbjFfbmFuZC5jCj4gCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvbXRkL25hbmQvcmF3L0tjb25maWcgYi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9LY29u ZmlnCj4gaW5kZXggMzBmMDYxOTM5NTYwLi42MzQwMmUzMzVkZjQgMTAwNjQ0Cj4gLS0tIGEvZHJp dmVycy9tdGQvbmFuZC9yYXcvS2NvbmZpZwo+ICsrKyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L0tj b25maWcKPiBAQCAtNDUzLDYgKzQ1MywxNCBAQCBjb25maWcgTVREX05BTkRfUk9DS0NISVAKPiAg CSAgICBORkMgdjgwMDogUkszMzA4LCBSVjExMDgKPiAgCSAgICBORkMgdjkwMDogUFgzMCwgUksz MzI2Cj4gIAo+ICtjb25maWcgTVREX05BTkRfTE9PTkdTT04xCj4gKwl0cmlzdGF0ZSAiU3VwcG9y dCBmb3IgTG9vbmdzb24xIFNvQyBOQU5EIGNvbnRyb2xsZXIiCgpDYW4geW91IHBsZWFzZSBtYXRj aCB0aGUgc3R5bGUgZm9yIHRoZSB0aXRsZXM/Cgo+ICsJZGVwZW5kcyBvbiBNQUNIX0xPT05HU09O MzIKCiB8fCBDUk9TU19DT01QSUxFCgo+ICsJc2VsZWN0IE1URF9OQU5EX0VDQ19TV19IQU1NSU5H Cj4gKwlzZWxlY3QgTE9PTkdTT04xX0RNQQoKTWF5YmUgdGhpcyBzaG91bGQgYmUgYSBkZXBlbmRz IG9uPwoKPiArCWhlbHAKPiArCSAgRW5hYmxlcyBzdXBwb3J0IGZvciBOQU5EIGNvbnRyb2xsZXIg b24gTG9vbmdzb24xIFNvQ3MuCj4gKwo+ICBjb21tZW50ICJNaXNjIgo+ICAKPiAgY29uZmlnIE1U RF9TTV9DT01NT04KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQvbmFuZC9yYXcvTWFrZWZpbGUg Yi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9NYWtlZmlsZQo+IGluZGV4IGQwMTFjNmM1M2Y4Zi4uNTBh NTFhZDZlYzIxIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvbXRkL25hbmQvcmF3L01ha2VmaWxlCj4g KysrIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvTWFrZWZpbGUKPiBAQCAtNTcsNiArNTcsNyBAQCBv YmotJChDT05GSUdfTVREX05BTkRfQ0FERU5DRSkJCSs9IGNhZGVuY2UtbmFuZC1jb250cm9sbGVy Lm8KPiAgb2JqLSQoQ09ORklHX01URF9OQU5EX0FSQVNBTikJCSs9IGFyYXNhbi1uYW5kLWNvbnRy b2xsZXIubwo+ICBvYmotJChDT05GSUdfTVREX05BTkRfSU5URUxfTEdNKQkrPSBpbnRlbC1uYW5k LWNvbnRyb2xsZXIubwo+ICBvYmotJChDT05GSUdfTVREX05BTkRfUk9DS0NISVApCQkrPSByb2Nr Y2hpcC1uYW5kLWNvbnRyb2xsZXIubwo+ICtvYmotJChDT05GSUdfTVREX05BTkRfTE9PTkdTT04x KSAgICAgICAgKz0gbG9vbmdzb24xX25hbmQubwo+ICAKPiAgbmFuZC1vYmpzIDo9IG5hbmRfYmFz ZS5vIG5hbmRfbGVnYWN5Lm8gbmFuZF9iYnQubyBuYW5kX3RpbWluZ3MubyBuYW5kX2lkcy5vCj4g IG5hbmQtb2JqcyArPSBuYW5kX29uZmkubwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL210ZC9uYW5k L3Jhdy9sb29uZ3NvbjFfbmFuZC5jIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvbG9vbmdzb24xX25h bmQuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwLi5iMDZlMzZl YzMyZGEKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvbG9vbmdz b24xX25hbmQuYwo+IEBAIC0wLDAgKzEsNzcwIEBACj4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlm aWVyOiBHUEwtMi4wLW9yLWxhdGVyCj4gKy8qCj4gKyAqIE5BTkQgRmxhc2ggRHJpdmVyIGZvciBM b29uZ3NvbiAxIFNvQwo+ICsgKgo+ICsgKiBDb3B5cmlnaHQgKEMpIDIwMTUtMjAyMSBaaGFuZywg S2VndWFuZyA8a2VndWFuZy56aGFuZ0BnbWFpbC5jb20+Cj4gKyAqLwo+ICsKPiArI2luY2x1ZGUg PGxpbnV4L2tlcm5lbC5oPgo+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9jbGsuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2RtYWVuZ2luZS5oPgo+ICsjaW5jbHVk ZSA8bGludXgvZG1hLW1hcHBpbmcuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2lvcG9sbC5oPgo+ICsj aW5jbHVkZSA8bGludXgvbXRkL210ZC5oPgo+ICsjaW5jbHVkZSA8bGludXgvbXRkL3Jhd25hbmQu aD4KPiArI2luY2x1ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgo+ICsjaW5jbHVkZSA8bGlu dXgvc2l6ZXMuaD4KPiArCj4gKyNpbmNsdWRlIDxuYW5kLmg+Cj4gKwo+ICsvKiBMb29uZ3NvbiAx IE5BTkQgUmVnaXN0ZXIgRGVmaW5pdGlvbnMgKi8KPiArI2RlZmluZSBOQU5EX0NNRAkJMHgwCj4g KyNkZWZpbmUgTkFORF9BRERSMQkJMHg0Cj4gKyNkZWZpbmUgTkFORF9BRERSMgkJMHg4Cj4gKyNk ZWZpbmUgTkFORF9USU1JTkcJCTB4Ywo+ICsjZGVmaW5lIE5BTkRfSURMCQkweDEwCj4gKyNkZWZp bmUgTkFORF9JREgJCTB4MTQKPiArI2RlZmluZSBOQU5EX1NUQVRVUwkJMHgxNQo+ICsjZGVmaW5l IE5BTkRfUEFSQU0JCTB4MTgKPiArI2RlZmluZSBOQU5EX09QX05VTQkJMHgxYwo+ICsjZGVmaW5l IE5BTkRfQ1NfUkRZCQkweDIwCj4gKwo+ICsjZGVmaW5lIE5BTkRfRE1BX0FERFIJCTB4NDAKPiAr Cj4gKy8qIE5BTkQgQ29tbWFuZCBSZWdpc3RlciBCaXRzICovCj4gKyNkZWZpbmUgT1BfRE9ORQkJ CUJJVCgxMCkKPiArI2RlZmluZSBPUF9TUEFSRQkJQklUKDkpCj4gKyNkZWZpbmUgT1BfTUFJTgkJ CUJJVCg4KQo+ICsjZGVmaW5lIENNRF9TVEFUVVMJCUJJVCg3KQo+ICsjZGVmaW5lIENNRF9SRVNF VAkJQklUKDYpCj4gKyNkZWZpbmUgQ01EX1JFQURJRAkJQklUKDUpCj4gKyNkZWZpbmUgQkxPQ0tT X0VSQVNFCQlCSVQoNCkKPiArI2RlZmluZSBDTURfRVJBU0UJCUJJVCgzKQo+ICsjZGVmaW5lIENN RF9XUklURQkJQklUKDIpCj4gKyNkZWZpbmUgQ01EX1JFQUQJCUJJVCgxKQo+ICsjZGVmaW5lIENN RF9WQUxJRAkJQklUKDApCj4gKwo+ICsjZGVmaW5lIE1BWF9BRERSX0NZQwkJNVUKPiArI2RlZmlu ZSBNQVhfSURfU0laRQkJKE5BTkRfU1RBVFVTIC0gTkFORF9JREwpCgpTdHJhbmdlLiBJIGd1ZXNz IHlvdSBjYW4gaGFyZGNvZGUgaXQuCgo+ICsjZGVmaW5lIFNJWkVfTUFTSwkJR0VOTUFTSygxMSwg OCkKPiArCj4gKyNkZWZpbmUgQklUU19QRVJfV09SRAkJMzIKPiArCj4gKy8qIG1hY3JvcyBmb3Ig cmVnaXN0ZXJzIHJlYWQvd3JpdGUgKi8KPiArI2RlZmluZSBuYW5kX3JlYWRsKG5jLCBvZmYpCQlc Cj4gKwlyZWFkbCgobmMpLT5yZWdfYmFzZSArIChvZmYpKQo+ICsKPiArI2RlZmluZSBuYW5kX3dy aXRlbChuYywgb2ZmLCB2YWwpCVwKPiArCXdyaXRlbCgodmFsKSwgKG5jKS0+cmVnX2Jhc2UgKyAo b2ZmKSkKPiArCj4gK3N0cnVjdCBsczF4X25hbmRfY29udHJvbGxlciB7Cj4gKwl2b2lkIF9faW9t ZW0gKnJlZ19iYXNlOwo+ICsJX19sZTMyIGFkZHIxX3JlZzsKPiArCV9fbGUzMiBhZGRyMl9yZWc7 Cj4gKwo+ICsJY2hhciAqYnVmOwo+ICsJdW5zaWduZWQgaW50IGxlbjsKPiArCXVuc2lnbmVkIGlu dCByZHlfdGltZW91dDsKPiArCj4gKwkvKiBETUEgRW5naW5lIHN0dWZmICovCj4gKwlzdHJ1Y3Qg ZG1hX2NoYW4gKmRtYV9jaGFuOwo+ICsJZG1hX2Nvb2tpZV90IGRtYV9jb29raWU7Cj4gKwlzdHJ1 Y3QgY29tcGxldGlvbiBkbWFfY29tcGxldGU7Cj4gK307Cj4gKwo+ICtzdHJ1Y3QgbHMxeF9uYW5k IHsKPiArCXN0cnVjdCBkZXZpY2UgKmRldjsKPiArCXN0cnVjdCBjbGsgKmNsazsKPiArCXN0cnVj dCBuYW5kX2NoaXAgY2hpcDsKPiArCXN0cnVjdCBuYW5kX2NvbnRyb2xsZXIgY29udHJvbGxlcjsK PiArCXN0cnVjdCBsczF4X25hbmRfY29udHJvbGxlciBuYzsKPiArCXN0cnVjdCBwbGF0X2xzMXhf bmFuZCAqcGRhdGE7Cj4gK307Cj4gKwo+ICtzdGF0aWMgdm9pZCBsczF4X25hbmRfZHVtcF9yZWdz KHN0cnVjdCBuYW5kX2NoaXAgKmNoaXApCj4gK3sKPiArCXN0cnVjdCBsczF4X25hbmQgKm5hbmQg PSBuYW5kX2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4gKwlzdHJ1Y3QgbHMxeF9uYW5kX2Nv bnRyb2xsZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsKPiArCXByaW50X2hleF9kdW1wKEtFUk5fSU5G TywgIlJFRzogIiwgRFVNUF9QUkVGSVhfT0ZGU0VULCAxNiwgNCwKPiArCQkgICAgICAgbmMtPnJl Z19iYXNlLCAweDQ0LCBmYWxzZSk7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIGxzMXhfbmFuZF9k bWFfY2FsbGJhY2sodm9pZCAqZGF0YSkKPiArewo+ICsJc3RydWN0IGxzMXhfbmFuZCAqbmFuZCA9 IChzdHJ1Y3QgbHMxeF9uYW5kICopZGF0YTsKPiArCXN0cnVjdCBsczF4X25hbmRfY29udHJvbGxl ciAqbmMgPSAmbmFuZC0+bmM7Cj4gKwllbnVtIGRtYV9zdGF0dXMgc3RhdHVzOwo+ICsKPiArCXN0 YXR1cyA9IGRtYWVuZ2luZV90eF9zdGF0dXMobmMtPmRtYV9jaGFuLCBuYy0+ZG1hX2Nvb2tpZSwg TlVMTCk7Cj4gKwlpZiAobGlrZWx5KHN0YXR1cyA9PSBETUFfQ09NUExFVEUpKQo+ICsJCWRldl9k YmcobmFuZC0+ZGV2LCAiRE1BIGNvbXBsZXRlIHdpdGggY29va2llPSVkXG4iLAo+ICsJCQluYy0+ ZG1hX2Nvb2tpZSk7Cj4gKwllbHNlCj4gKwkJZGV2X2VycihuYW5kLT5kZXYsICJETUEgZXJyb3Ig d2l0aCBjb29raWU9JWRcbiIsCj4gKwkJCW5jLT5kbWFfY29va2llKTsKPiArCj4gKwljb21wbGV0 ZSgmbmMtPmRtYV9jb21wbGV0ZSk7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgbHMxeF9uYW5kX2Rt YV90cmFuc2ZlcihzdHJ1Y3QgbHMxeF9uYW5kICpuYW5kLCBib29sIGlzX3dyaXRlKQo+ICt7Cj4g KwlzdHJ1Y3QgbHMxeF9uYW5kX2NvbnRyb2xsZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsJc3RydWN0 IGRtYV9jaGFuICpjaGFuID0gbmMtPmRtYV9jaGFuOwo+ICsJc3RydWN0IGRtYV9hc3luY190eF9k ZXNjcmlwdG9yICpkZXNjOwo+ICsJZW51bSBkbWFfZGF0YV9kaXJlY3Rpb24gZGF0YV9kaXIgPQo+ ICsJICAgIGlzX3dyaXRlID8gRE1BX1RPX0RFVklDRSA6IERNQV9GUk9NX0RFVklDRTsKPiArCWVu dW0gZG1hX3RyYW5zZmVyX2RpcmVjdGlvbiB4ZmVyX2RpciA9Cj4gKwkgICAgaXNfd3JpdGUgPyBE TUFfTUVNX1RPX0RFViA6IERNQV9ERVZfVE9fTUVNOwo+ICsJZG1hX2FkZHJfdCBkbWFfYWRkcjsK PiArCWludCByZXQ7Cj4gKwo+ICsJZG1hX2FkZHIgPSBkbWFfbWFwX3NpbmdsZShjaGFuLT5kZXZp Y2UtPmRldiwgbmMtPmJ1ZiwgbmMtPmxlbiwKPiArCQkJCSAgZGF0YV9kaXIpOwo+ICsJaWYgKGRt YV9tYXBwaW5nX2Vycm9yKGNoYW4tPmRldmljZS0+ZGV2LCBkbWFfYWRkcikpIHsKPiArCQlkZXZf ZXJyKG5hbmQtPmRldiwgImZhaWxlZCB0byBtYXAgRE1BIGJ1ZmZlciFcbiIpOwo+ICsJCXJldHVy biAtRU5YSU87Cj4gKwl9Cj4gKwo+ICsJZGVzYyA9IGRtYWVuZ2luZV9wcmVwX3NsYXZlX3Npbmds ZShjaGFuLCBkbWFfYWRkciwgbmMtPmxlbiwgeGZlcl9kaXIsCj4gKwkJCQkJICAgRE1BX1BSRVBf SU5URVJSVVBUKTsKPiArCWlmICghZGVzYykgewo+ICsJCWRldl9lcnIobmFuZC0+ZGV2LCAiZmFp bGVkIHRvIHByZXBhcmUgRE1BIGRlc2NyaXB0b3IhXG4iKTsKPiArCQlyZXQgPSBQVFJfRVJSKGRl c2MpOwo+ICsJCWdvdG8gZXJyOwo+ICsJfQo+ICsJZGVzYy0+Y2FsbGJhY2sgPSBsczF4X25hbmRf ZG1hX2NhbGxiYWNrOwo+ICsJZGVzYy0+Y2FsbGJhY2tfcGFyYW0gPSBuYW5kOwo+ICsKPiArCW5j LT5kbWFfY29va2llID0gZG1hZW5naW5lX3N1Ym1pdChkZXNjKTsKPiArCXJldCA9IGRtYV9zdWJt aXRfZXJyb3IobmMtPmRtYV9jb29raWUpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIobmFu ZC0+ZGV2LCAiZmFpbGVkIHRvIHN1Ym1pdCBETUEgZGVzY3JpcHRvciFcbiIpOwo+ICsJCWdvdG8g ZXJyOwo+ICsJfQo+ICsKPiArCWRldl9kYmcobmFuZC0+ZGV2LCAiaXNzdWUgRE1BIHdpdGggY29v a2llPSVkXG4iLCBuYy0+ZG1hX2Nvb2tpZSk7Cj4gKwlkbWFfYXN5bmNfaXNzdWVfcGVuZGluZyhj aGFuKTsKPiArCj4gKwlyZXQgPSB3YWl0X2Zvcl9jb21wbGV0aW9uX3RpbWVvdXQoJm5jLT5kbWFf Y29tcGxldGUsCj4gKwkJCQkJICBtc2Vjc190b19qaWZmaWVzKG5jLT5yZHlfdGltZW91dCkpOwo+ ICsJaWYgKHJldCA8PSAwKSB7Cj4gKwkJZGV2X2VycihuYW5kLT5kZXYsICJETUEgdGltZW91dCFc biIpOwo+ICsJCWRtYWVuZ2luZV90ZXJtaW5hdGVfYWxsKGNoYW4pOwo+ICsJCXJldCA9IC1FSU87 Cj4gKwl9Cj4gKwlyZXQgPSAwOwo+ICtlcnI6Cj4gKwlkbWFfdW5tYXBfc2luZ2xlKGNoYW4tPmRl dmljZS0+ZGV2LCBkbWFfYWRkciwgbmMtPmxlbiwgZGF0YV9kaXIpOwo+ICsKPiArCXJldHVybiBy ZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbmxpbmUgdm9pZCBsczF4X25hbmRfcGFyc2VfYWRkcmVz cyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICsJCQkJCSAgIGNvbnN0IHU4ICphZGRycywKPiAr CQkJCQkgICB1bnNpZ25lZCBpbnQgbmFkZHJzLCBpbnQgY21kKQo+ICt7Cj4gKwlzdHJ1Y3QgbHMx eF9uYW5kICpuYW5kID0gbmFuZF9nZXRfY29udHJvbGxlcl9kYXRhKGNoaXApOwo+ICsJc3RydWN0 IGxzMXhfbmFuZF9jb250cm9sbGVyICpuYyA9ICZuYW5kLT5uYzsKPiArI2lmIGRlZmluZWQoQ09O RklHX0xPT05HU09OMV9MUzFCKQoKUGxlYXNlIHVzZSBhIHJlZ3VsYXIgaWYgKElTX0RFRklORUQo KSkKCkkgZG9uJ3QgbGlrZSB0aGlzIHN5bWJvbCBhbnl3YXksIHlvdSBzaG91bGQgZ2V0IHRoaXMg aW5mb3JtYXRpb24gZnJvbSBhCmNvbXBhdGlibGUgKGxpa2UgdGhlIG1hY2hpbmUgY29tcGF0aWJs ZSkgbm90IGZyb20gYSBLY29uZmlnIHN5bWJvbC4KCj4gKwl1bnNpZ25lZCBpbnQgcGFnZV9zaGlm dCA9IGNoaXAtPnBhZ2Vfc2hpZnQgKyAxOwo+ICsjZW5kaWYKPiArCWludCBpOwo+ICsKPiArCW5j LT5hZGRyMV9yZWcgPSAwOwo+ICsJbmMtPmFkZHIyX3JlZyA9IDA7Cj4gKyNpZiBkZWZpbmVkKENP TkZJR19MT09OR1NPTjFfTFMxQikKPiArCWlmIChjbWQgPT0gQ01EX0VSQVNFKSB7Cj4gKwkJcGFn ZV9zaGlmdCA9IGNoaXAtPnBhZ2Vfc2hpZnQ7Cj4gKwo+ICsJCWZvciAoaSA9IDA7IGkgPCBtaW4o TUFYX0FERFJfQ1lDIC0gMiwgbmFkZHJzKTsgaSsrKQo+ICsJCQluYy0+YWRkcjFfcmVnIHw9Cj4g KwkJCSAgICAodTMyKWFkZHJzW2ldIDw8IChwYWdlX3NoaWZ0ICsgQklUU19QRVJfQllURSAqIGkp Owo+ICsJCWlmIChpID09IE1BWF9BRERSX0NZQyAtIDIpCj4gKwkJCW5jLT5hZGRyMl9yZWcgfD0K PiArCQkJICAgICh1MzIpYWRkcnNbaV0gPj4gKEJJVFNfUEVSX1dPUkQgLSBwYWdlX3NoaWZ0IC0K PiArCQkJCQkgICAgICBCSVRTX1BFUl9CWVRFICogKGkgLSAxKSk7Cj4gKwo+ICsJCXJldHVybjsK PiArCX0KPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgbWluKDJVLCBuYWRkcnMpOyBpKyspCj4gKwkJ bmMtPmFkZHIxX3JlZyB8PSAodTMyKWFkZHJzW2ldIDw8IEJJVFNfUEVSX0JZVEUgKiBpOwo+ICsJ Zm9yIChpID0gMjsgaSA8IG1pbihNQVhfQUREUl9DWUMsIG5hZGRycyk7IGkrKykKPiArCQluYy0+ YWRkcjFfcmVnIHw9Cj4gKwkJICAgICh1MzIpYWRkcnNbaV0gPDwgKHBhZ2Vfc2hpZnQgKyBCSVRT X1BFUl9CWVRFICogKGkgLSAyKSk7Cj4gKwlpZiAoaSA9PSBNQVhfQUREUl9DWUMpCj4gKwkJbmMt PmFkZHIyX3JlZyB8PQo+ICsJCSAgICAodTMyKWFkZHJzW2ldID4+IChCSVRTX1BFUl9XT1JEIC0g cGFnZV9zaGlmdCAtCj4gKwkJCQkgICAgICBCSVRTX1BFUl9CWVRFICogKGkgLSAxKSk7Cj4gKyNl bGlmIGRlZmluZWQoQ09ORklHX0xPT05HU09OMV9MUzFDKQo+ICsJaWYgKGNtZCA9PSBDTURfRVJB U0UpIHsKPiArCQlmb3IgKGkgPSAwOyBpIDwgbWluKE1BWF9BRERSX0NZQywgbmFkZHJzKTsgaSsr KQo+ICsJCQluYy0+YWRkcjJfcmVnIHw9ICh1MzIpYWRkcnNbaV0gPDwgQklUU19QRVJfQllURSAq IGk7Cj4gKwo+ICsJCXJldHVybjsKPiArCX0KPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgbWluKE1B WF9BRERSX0NZQywgbmFkZHJzKTsgaSsrKSB7Cj4gKwkJaWYgKGkgPCAyKQo+ICsJCQluYy0+YWRk cjFfcmVnIHw9ICh1MzIpYWRkcnNbaV0gPDwgQklUU19QRVJfQllURSAqIGk7Cj4gKwkJZWxzZQo+ ICsJCQluYy0+YWRkcjJfcmVnIHw9Cj4gKwkJCSAgICAodTMyKWFkZHJzW2ldIDw8IEJJVFNfUEVS X0JZVEUgKiAoaSAtIDIpOwo+ICsJfQo+ICsjZW5kaWYKPiArfQo+ICsKPiArc3RhdGljIGludCBs czF4X25hbmRfc2V0X2NvbnRyb2xsZXIoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwKPiArCQkJCSAg ICBjb25zdCBzdHJ1Y3QgbmFuZF9zdWJvcCAqc3Vib3AsIGludCBjbWQpCj4gK3sKPiArCXN0cnVj dCBsczF4X25hbmQgKm5hbmQgPSBuYW5kX2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4gKwlz dHJ1Y3QgbHMxeF9uYW5kX2NvbnRyb2xsZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsJdW5zaWduZWQg aW50IG9wX2lkOwo+ICsKPiArCW5jLT5idWYgPSBOVUxMOwo+ICsJbmMtPmxlbiA9IDA7Cj4gKwlu Yy0+cmR5X3RpbWVvdXQgPSAwOwo+ICsKPiArCWZvciAob3BfaWQgPSAwOyBvcF9pZCA8IHN1Ym9w LT5uaW5zdHJzOyBvcF9pZCsrKSB7Cj4gKwkJY29uc3Qgc3RydWN0IG5hbmRfb3BfaW5zdHIgKmlu c3RyID0gJnN1Ym9wLT5pbnN0cnNbb3BfaWRdOwo+ICsJCXVuc2lnbmVkIGludCBvZmZzZXQsIG5h ZGRyczsKPiArCQljb25zdCB1OCAqYWRkcnM7Cj4gKwo+ICsJCXN3aXRjaCAoaW5zdHItPnR5cGUp IHsKPiArCQljYXNlIE5BTkRfT1BfQ01EX0lOU1RSOgo+ICsJCQlicmVhazsKClRoaXMgaXMgdmVy eSBzdXNwaWNpb3VzLiBZb3Ugc2hvdWxkIGRlZmluaXRlbHkgZG8gc29tZXRoaW5nIHdpdGggdGhl CmNvbW1hbmQgYnl0ZXMsIHlvdSBzaG91bGQgbm90IGd1ZXNzIHRoZSBjb21tYW5kcyBiYXNlZCBv biB0aGUgZm9ybWF0IG9mCnRoZSBvcGVyYXRpb24uCgo+ICsJCWNhc2UgTkFORF9PUF9BRERSX0lO U1RSOgo+ICsJCQlvZmZzZXQgPSBuYW5kX3N1Ym9wX2dldF9hZGRyX3N0YXJ0X29mZihzdWJvcCwg b3BfaWQpOwo+ICsJCQluYWRkcnMgPSBuYW5kX3N1Ym9wX2dldF9udW1fYWRkcl9jeWMoc3Vib3As IG9wX2lkKTsKPiArCQkJYWRkcnMgPSAmaW5zdHItPmN0eC5hZGRyLmFkZHJzW29mZnNldF07Cj4g Kwo+ICsJCQlsczF4X25hbmRfcGFyc2VfYWRkcmVzcyhjaGlwLCBhZGRycywgbmFkZHJzLCBjbWQp Owo+ICsJCQkvKiBzZXQgTkFORCBhZGRyZXNzICovCj4gKwkJCW5hbmRfd3JpdGVsKG5jLCBOQU5E X0FERFIxLCBuYy0+YWRkcjFfcmVnKTsKPiArCQkJbmFuZF93cml0ZWwobmMsIE5BTkRfQUREUjIs IG5jLT5hZGRyMl9yZWcpOwo+ICsJCQlicmVhazsKPiArCQljYXNlIE5BTkRfT1BfREFUQV9JTl9J TlNUUjoKPiArCQkJb2Zmc2V0ID0gbmFuZF9zdWJvcF9nZXRfZGF0YV9zdGFydF9vZmYoc3Vib3As IG9wX2lkKTsKPiArCQkJbmMtPmxlbiA9IG5hbmRfc3Vib3BfZ2V0X2RhdGFfbGVuKHN1Ym9wLCBv cF9pZCk7Cj4gKwkJCW5jLT5idWYgPSBpbnN0ci0+Y3R4LmRhdGEuYnVmLmluICsgb2Zmc2V0Owo+ ICsKPiArCQkJaWYgKCFJU19BTElHTkVEKG5jLT5sZW4sIGNoaXAtPmJ1Zl9hbGlnbikgfHwKPiAr CQkJICAgICFJU19BTElHTkVEKCh1bnNpZ25lZCBpbnQpbmMtPmJ1ZiwgY2hpcC0+YnVmX2FsaWdu KSkKPiArCQkJCXJldHVybiAtRU5PVFNVUFA7Cj4gKwkJCS8qIHNldCBOQU5EIGRhdGEgbGVuZ3Ro ICovCj4gKwkJCW5hbmRfd3JpdGVsKG5jLCBOQU5EX09QX05VTSwgbmMtPmxlbik7Cj4gKwkJCWJy ZWFrOwo+ICsJCWNhc2UgTkFORF9PUF9EQVRBX09VVF9JTlNUUjoKPiArCQkJb2Zmc2V0ID0gbmFu ZF9zdWJvcF9nZXRfZGF0YV9zdGFydF9vZmYoc3Vib3AsIG9wX2lkKTsKPiArCQkJbmMtPmxlbiA9 IG5hbmRfc3Vib3BfZ2V0X2RhdGFfbGVuKHN1Ym9wLCBvcF9pZCk7Cj4gKwkJCW5jLT5idWYgPSAo dm9pZCAqKWluc3RyLT5jdHguZGF0YS5idWYub3V0ICsgb2Zmc2V0Owo+ICsKPiArCQkJaWYgKCFJ U19BTElHTkVEKG5jLT5sZW4sIGNoaXAtPmJ1Zl9hbGlnbikgfHwKPiArCQkJICAgICFJU19BTElH TkVEKCh1bnNpZ25lZCBpbnQpbmMtPmJ1ZiwgY2hpcC0+YnVmX2FsaWduKSkKPiArCQkJCXJldHVy biAtRU5PVFNVUFA7Cj4gKwkJCS8qIHNldCBOQU5EIGRhdGEgbGVuZ3RoICovCj4gKwkJCW5hbmRf d3JpdGVsKG5jLCBOQU5EX09QX05VTSwgbmMtPmxlbik7Cj4gKwkJCWJyZWFrOwo+ICsJCWNhc2Ug TkFORF9PUF9XQUlUUkRZX0lOU1RSOgo+ICsJCQluYy0+cmR5X3RpbWVvdXQgPSBpbnN0ci0+Y3R4 LndhaXRyZHkudGltZW91dF9tczsKPiArCQkJYnJlYWs7Cj4gKwkJfQo+ICsJfQo+ICsKPiArCS8q c2V0IE5BTkQgZXJhc2UgYmxvY2sgY291bnQgKi8KPiArCWlmIChjbWQgJiBDTURfRVJBU0UpCj4g KwkJbmFuZF93cml0ZWwobmMsIE5BTkRfT1BfTlVNLCAxKTsKPiArCS8qc2V0IE5BTkQgb3BlcmF0 aW9uIHJlZ2lvbiAqLwoKUGxlYXNlIGZpeCBhbGwgeW91ciBjb21tZW50cyBpbiB0aGUgZHJpdmVy LCBlZzoKCgkvKiBTZXQgTkFORCBvcGVyYXRpb24gcmVnaW9uICovCgo+ICsJaWYgKG5jLT5idWYg JiYgbmMtPmxlbikgewo+ICsJCWlmIChuYy0+YWRkcjFfcmVnICYgQklUKGNoaXAtPnBhZ2Vfc2hp ZnQpKQo+ICsJCQljbWQgfD0gT1BfU1BBUkU7Cj4gKwkJZWxzZQo+ICsJCQljbWQgfD0gT1BfU1BB UkUgfCBPUF9NQUlOOwoKSXMgdGhpcyByZWFsbHkgbmVlZGVkPyBDYW4ndCB5b3UgYWx3YXlzIHN0 aWNrIHRvIE9QX1NQQVJFIHwgT1BfTUFJTj8KCj4gKwl9Cj4gKwo+ICsJLypzZXQgTkFORCBjb21t YW5kICovCj4gKwluYW5kX3dyaXRlbChuYywgTkFORF9DTUQsIGNtZCk7Cj4gKwkvKiBUcmlnZ2Vy IG9wZXJhdGlvbiAqLwo+ICsJbmFuZF93cml0ZWwobmMsIE5BTkRfQ01ELCBuYW5kX3JlYWRsKG5j LCBOQU5EX0NNRCkgfCBDTURfVkFMSUQpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtz dGF0aWMgaW5saW5lIGludCBsczF4X25hbmRfd2FpdF9mb3Jfb3BfZG9uZShzdHJ1Y3QgbHMxeF9u YW5kX2NvbnRyb2xsZXIgKm5jKQo+ICt7Cj4gKwl1bnNpZ25lZCBpbnQgdmFsOwo+ICsJaW50IHJl dCA9IDA7Cj4gKwo+ICsJLyogV2FpdCBmb3Igb3BlcmF0aW9uIGRvbmUgKi8KPiArCWlmIChuYy0+ cmR5X3RpbWVvdXQpCj4gKwkJcmV0ID0gcmVhZGxfcmVsYXhlZF9wb2xsX3RpbWVvdXQobmMtPnJl Z19iYXNlICsgTkFORF9DTUQsIHZhbCwKPiArCQkJCQkJIHZhbCAmIE9QX0RPTkUsIDAsCj4gKwkJ CQkJCSBuYy0+cmR5X3RpbWVvdXQgKiAxMDAwKTsKPiArCj4gKwlyZXR1cm4gcmV0Owo+ICt9Cj4g Kwo+ICtzdGF0aWMgaW50IGxzMXhfbmFuZF9yZXNldF9leGVjKHN0cnVjdCBuYW5kX2NoaXAgKmNo aXAsCj4gKwkJCQljb25zdCBzdHJ1Y3QgbmFuZF9zdWJvcCAqc3Vib3ApCj4gK3sKPiArCXN0cnVj dCBsczF4X25hbmQgKm5hbmQgPSBuYW5kX2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4gKwlz dHJ1Y3QgbHMxeF9uYW5kX2NvbnRyb2xsZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsJaW50IHJldDsK PiArCj4gKwlsczF4X25hbmRfc2V0X2NvbnRyb2xsZXIoY2hpcCwgc3Vib3AsIENNRF9SRVNFVCk7 Cj4gKwo+ICsJcmV0ID0gbHMxeF9uYW5kX3dhaXRfZm9yX29wX2RvbmUobmMpOwo+ICsJaWYgKHJl dCkKPiArCQlkZXZfZXJyKG5hbmQtPmRldiwgIkNNRF9SRVNFVCBmYWlsZWQhICVkXG4iLCByZXQp Owo+ICsKPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgbHMxeF9uYW5kX3Jl YWRfaWRfZXhlYyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICsJCQkJICBjb25zdCBzdHJ1Y3Qg bmFuZF9zdWJvcCAqc3Vib3ApCj4gK3sKPiArCXN0cnVjdCBsczF4X25hbmQgKm5hbmQgPSBuYW5k X2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4gKwlzdHJ1Y3QgbHMxeF9uYW5kX2NvbnRyb2xs ZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsJaW50IGlkbCwgaTsKPiArCWludCByZXQ7Cj4gKwo+ICsJ bHMxeF9uYW5kX3NldF9jb250cm9sbGVyKGNoaXAsIHN1Ym9wLCBDTURfUkVBRElEKTsKPiArCj4g KwlyZXQgPSBsczF4X25hbmRfd2FpdF9mb3Jfb3BfZG9uZShuYyk7Cj4gKwlpZiAocmV0KSB7Cj4g KwkJZGV2X2VycihuYW5kLT5kZXYsICJDTURfUkVBRElEIGZhaWxlZCEgJWRcbiIsIHJldCk7Cj4g KwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlpZGwgPSAobmFuZF9yZWFkbChuYywgTkFORF9J REwpKTsKClVubmVlZGVkIG91dGVyICggKS4KCj4gKwlmb3IgKGkgPSAwOyBpIDwgbWluX3QodW5z aWduZWQgaW50LCBuYy0+bGVuLCBNQVhfSURfU0laRSk7IGkrKykKClRoZSBjb3JlIGVuZm9yY2Vz IHRoZSBudW1iZXIgb2YgZGF0YSBjeWNsZXMgdG8gYmUgbGVzcyBvcgplcXVhbCB0aGFuIE1BWF9J RF9TSVpFIGlmIGNvcnJlY3RseSBkZXNjcmliZWQgYmVsb3cgKHNlZSB0aGUgY29tbWVudCBpbgp0 aGUgZXhlY19vcCBhcnJheSkgc28geW91IGRvbid0IG5lZWQgdGhpcyBtaW5fdCgpIGhlcmUuCgpQ bGVhc2UgdXNlIHsgfSB0byBlbmNsb3NlIHRoZSBpZi9lbHNlIGJsb2NrLgoKPiArCQlpZiAoaSA+ IDApCgpUaGlzIGxvb2tzIHZlcnkgc3VzcGljaW91cywgSSB3b3VsZCBleHBlY3QgdGhlIGNvbmRp dGlvbiB0byBiZSBpIDwgNAoKPiArCQkJbmMtPmJ1ZltpXSA9ICooKGNoYXIgKikmaWRsICsgNCAt IGkpOwoKUGxlYXNlIHJld3JpdGUgdGhpcywgaXQgaXMgaGFyZCB0byBmb2xsb3cuCgo+ICsJCWVs c2UKPiArCQkJbmMtPmJ1ZltpXSA9IChjaGFyKShuYW5kX3JlYWRsKG5jLCBOQU5EX0lESCkpOwo+ ICsKPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgbHMxeF9uYW5kX2VyYXNl X2V4ZWMoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwKPiArCQkJCWNvbnN0IHN0cnVjdCBuYW5kX3N1 Ym9wICpzdWJvcCkKPiArewo+ICsJc3RydWN0IGxzMXhfbmFuZCAqbmFuZCA9IG5hbmRfZ2V0X2Nv bnRyb2xsZXJfZGF0YShjaGlwKTsKPiArCXN0cnVjdCBsczF4X25hbmRfY29udHJvbGxlciAqbmMg PSAmbmFuZC0+bmM7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCWxzMXhfbmFuZF9zZXRfY29udHJvbGxl cihjaGlwLCBzdWJvcCwgQ01EX0VSQVNFKTsKPiArCj4gKwlyZXQgPSBsczF4X25hbmRfd2FpdF9m b3Jfb3BfZG9uZShuYyk7Cj4gKwlpZiAocmV0KQo+ICsJCWRldl9lcnIobmFuZC0+ZGV2LCAiQ01E X0VSQVNFIGZhaWxlZCEgJWRcbiIsIHJldCk7Cj4gKwo+ICsJcmV0dXJuIHJldDsKPiArfQo+ICsK PiArc3RhdGljIGludCBsczF4X25hbmRfcmVhZF9leGVjKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAs Cj4gKwkJCSAgICAgICBjb25zdCBzdHJ1Y3QgbmFuZF9zdWJvcCAqc3Vib3ApCj4gK3sKPiArCXN0 cnVjdCBsczF4X25hbmQgKm5hbmQgPSBuYW5kX2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4g KwlzdHJ1Y3QgbHMxeF9uYW5kX2NvbnRyb2xsZXIgKm5jID0gJm5hbmQtPm5jOwo+ICsJaW50IHJl dDsKPiArCj4gKwlsczF4X25hbmRfc2V0X2NvbnRyb2xsZXIoY2hpcCwgc3Vib3AsIENNRF9SRUFE KTsKPiArCj4gKwlyZXQgPSBsczF4X25hbmRfZG1hX3RyYW5zZmVyKG5hbmQsIGZhbHNlKTsKClBs ZWFzZSB1c2UgYW4gaW50ZXJtZWRpYXRlIHZhcmlhYmxlIHN1Y2ggYXMgYm9vbCB3cml0ZSA9IGZh bHNlOyAoc2FtZQpiZWxvdykKCj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJ cmV0ID0gbHMxeF9uYW5kX3dhaXRfZm9yX29wX2RvbmUobmMpOwo+ICsJaWYgKHJldCkKPiArCQlk ZXZfZXJyKG5hbmQtPmRldiwgIkNNRF9SRUFEIGZhaWxlZCEgJWRcbiIsIHJldCk7Cj4gKwo+ICsJ cmV0dXJuIHJldDsKPiArfQo+ICsKPiArc3RhdGljIGludCBsczF4X25hbmRfd3JpdGVfZXhlYyhz dHJ1Y3QgbmFuZF9jaGlwICpjaGlwLAo+ICsJCQkJY29uc3Qgc3RydWN0IG5hbmRfc3Vib3AgKnN1 Ym9wKQo+ICt7Cj4gKwlzdHJ1Y3QgbHMxeF9uYW5kICpuYW5kID0gbmFuZF9nZXRfY29udHJvbGxl cl9kYXRhKGNoaXApOwo+ICsJc3RydWN0IGxzMXhfbmFuZF9jb250cm9sbGVyICpuYyA9ICZuYW5k LT5uYzsKPiArCWludCByZXQ7Cj4gKwo+ICsJbHMxeF9uYW5kX3NldF9jb250cm9sbGVyKGNoaXAs IHN1Ym9wLCBDTURfV1JJVEUpOwo+ICsKPiArCXJldCA9IGxzMXhfbmFuZF9kbWFfdHJhbnNmZXIo bmFuZCwgdHJ1ZSk7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJcmV0ID0g bHMxeF9uYW5kX3dhaXRfZm9yX29wX2RvbmUobmMpOwo+ICsJaWYgKHJldCkKPiArCQlkZXZfZXJy KG5hbmQtPmRldiwgIkNNRF9XUklURSBmYWlsZWQhICVkXG4iLCByZXQpOwo+ICsKPiArCXJldHVy biByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgbHMxeF9uYW5kX3JlYWRfc3RhdHVzX2V4ZWMo c3RydWN0IG5hbmRfY2hpcCAqY2hpcCwKPiArCQkJCSAgICAgIGNvbnN0IHN0cnVjdCBuYW5kX3N1 Ym9wICpzdWJvcCkKPiArewo+ICsJc3RydWN0IGxzMXhfbmFuZCAqbmFuZCA9IG5hbmRfZ2V0X2Nv bnRyb2xsZXJfZGF0YShjaGlwKTsKPiArCXN0cnVjdCBsczF4X25hbmRfY29udHJvbGxlciAqbmMg PSAmbmFuZC0+bmM7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCWxzMXhfbmFuZF9zZXRfY29udHJvbGxl cihjaGlwLCBzdWJvcCwgQ01EX1NUQVRVUyk7Cj4gKwo+ICsJcmV0ID0gbHMxeF9uYW5kX3dhaXRf Zm9yX29wX2RvbmUobmMpOwo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIobmFuZC0+ZGV2LCAi Q01EX1NUQVRVUyBmYWlsZWQhICVkXG4iLCByZXQpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4g Kwo+ICsJbmMtPmJ1ZlswXSA9IG5hbmRfcmVhZGwobmMsIE5BTkRfSURIKSA+PiBCSVRTX1BFUl9C WVRFOwoKVGhpcyBsb29rcyB2ZXJ5IHNwZWNpZmljIHRvIHRoZSBzdGF0dXMgY21kLCB3aGljaCBp cyBub3QgYSB2YWxpZAppbXBsZW1lbnRhdGlvbi4gQ2FuIHlvdSB0dXJuIHRoaXMgZnVuY3Rpb24g Z2VuZXJpYyB0byBhbnkgY21kK2RhdGEKYnl0ZXM/ICh0aGUgbnVtYmVyIG9mIGRhdGEgYnl0ZXMg Y291bGQgYmUgZGlmZmVyZW50IHRoYW4gMSkuCgo+ICsKPiArCXJldHVybiByZXQ7Cj4gK30KPiAr Cj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgbmFuZF9vcF9wYXJzZXIgbHMxeF9uYW5kX29wX3BhcnNl ciA9IE5BTkRfT1BfUEFSU0VSKAo+ICsJTkFORF9PUF9QQVJTRVJfUEFUVEVSTigKPiArCQlsczF4 X25hbmRfcmVzZXRfZXhlYywKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2Up LAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9XQUlUUkRZX0VMRU0oZmFsc2UpKSwKPiArCU5BTkRf T1BfUEFSU0VSX1BBVFRFUk4oCj4gKwkJbHMxeF9uYW5kX3JlYWRfaWRfZXhlYywKPiArCQlOQU5E X09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9B RERSX0VMRU0oZmFsc2UsIE1BWF9BRERSX0NZQyksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0RB VEFfSU5fRUxFTShmYWxzZSwgOCkpLAoKUGxlYXNlIHVzZSB0aGUgZGVmaW5pdGlvbiB1c2VkIGFi b3ZlICAgICAgICAgICAgICAgICAgIF4KCj4gKwlOQU5EX09QX1BBUlNFUl9QQVRURVJOKAo+ICsJ CWxzMXhfbmFuZF9lcmFzZV9leGVjLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxFTShm YWxzZSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0FERFJfRUxFTShmYWxzZSwgTUFYX0FERFJf Q1lDKSwKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRf T1BfUEFSU0VSX1BBVF9XQUlUUkRZX0VMRU0oZmFsc2UpKSwKPiArCU5BTkRfT1BfUEFSU0VSX1BB VFRFUk4oCj4gKwkJbHMxeF9uYW5kX3JlYWRfZXhlYywKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRf Q01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9BRERSX0VMRU0oZmFsc2Us IE1BWF9BRERSX0NZQyksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUX0NNRF9FTEVNKGZhbHNlKSwK PiArCQlOQU5EX09QX1BBUlNFUl9QQVRfV0FJVFJEWV9FTEVNKHRydWUpLAo+ICsJCU5BTkRfT1Bf UEFSU0VSX1BBVF9EQVRBX0lOX0VMRU0oZmFsc2UsIDApKSwKPiArCU5BTkRfT1BfUEFSU0VSX1BB VFRFUk4oCj4gKwkJbHMxeF9uYW5kX3dyaXRlX2V4ZWMsCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFU X0NNRF9FTEVNKGZhbHNlKSwKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRfQUREUl9FTEVNKGZhbHNl LCBNQVhfQUREUl9DWUMpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9EQVRBX09VVF9FTEVNKGZh bHNlLCAwKSwKPiArCQlOQU5EX09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5B TkRfT1BfUEFSU0VSX1BBVF9XQUlUUkRZX0VMRU0odHJ1ZSkpLAo+ICsJTkFORF9PUF9QQVJTRVJf UEFUVEVSTigKPiArCQlsczF4X25hbmRfcmVhZF9zdGF0dXNfZXhlYywKPiArCQlOQU5EX09QX1BB UlNFUl9QQVRfQ01EX0VMRU0oZmFsc2UpLAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVF9EQVRBX0lO X0VMRU0oZmFsc2UsIDEpKSwKPiArCSk7Cj4gKwo+ICtzdGF0aWMgaW50IGxzMXhfbmFuZF9leGVj X29wKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsCj4gKwkJCSAgICAgY29uc3Qgc3RydWN0IG5hbmRf b3BlcmF0aW9uICpvcCwgYm9vbCBjaGVja19vbmx5KQo+ICt7Cj4gKwlyZXR1cm4gbmFuZF9vcF9w YXJzZXJfZXhlY19vcChjaGlwLCAmbHMxeF9uYW5kX29wX3BhcnNlciwgb3AsCj4gKwkJCQkgICAg ICBjaGVja19vbmx5KTsKPiArfQo+ICsKPiArc3RhdGljIGludCBsczF4X25hbmRfcmVhZF9zdWJw YWdlKHN0cnVjdCBuYW5kX2NoaXAgKmNoaXAsCj4gKwkJCQkgIHVuc2lnbmVkIGludCBkYXRhX29m ZnMsIHVuc2lnbmVkIGludCByZWFkbGVuLAo+ICsJCQkJICB1bnNpZ25lZCBjaGFyICpidWZwb2ks IGludCBwYWdlKQo+ICt7CgpUaGVyZSBpcyBub3RoaW5nIHNwZWNpZmljIHRvIHlvdXIgY29udHJv bGxlciBpbiB0aGF0IGhlbHBlciwgd2h5IGRvIHlvdQpuZWVkIGl0PwoKPiArCXN0cnVjdCBtdGRf aW5mbyAqbXRkID0gbmFuZF90b19tdGQoY2hpcCk7Cj4gKwlpbnQgc3RhcnRfc3RlcCwgZW5kX3N0 ZXAsIG51bV9zdGVwcywgcmV0Owo+ICsJY2hhciAqcDsKPiArCWludCBkYXRhX2NvbF9hZGRyLCBp Owo+ICsJaW50IGRhdGFmcmFnX2xlbiwgZWNjZnJhZ19sZW4sIGFsaWduZWRfbGVuLCBhbGlnbmVk X3BvczsKPiArCWludCBidXN3ID0gKGNoaXAtPm9wdGlvbnMgJiBOQU5EX0JVU1dJRFRIXzE2KSA/ IDIgOiAxOwo+ICsJaW50IGluZGV4LCBzZWN0aW9uID0gMDsKPiArCXVuc2lnbmVkIGludCBtYXhf Yml0ZmxpcHMgPSAwOwo+ICsJc3RydWN0IG10ZF9vb2JfcmVnaW9uIG9vYnJlZ2lvbiA9IHsgfTsK PiArCj4gKwkvKiBSZWFkIHRoZSB3aG9sZSBwYWdlIGFuZCBPT0IgZGF0YSAqLwo+ICsJcmV0ID0g Y2hpcC0+ZWNjLnJlYWRfcGFnZV9yYXcoY2hpcCwgYnVmcG9pLCAxLCBwYWdlKTsKPiArCWlmIChy ZXQpCj4gKwkJcmV0dXJuIHJldDsKPiArCj4gKwkvKiBDb2x1bW4gYWRkcmVzcyB3aXRoaW4gdGhl IHBhZ2UgYWxpZ25lZCB0byBFQ0Mgc2l6ZSAoMjU2Ynl0ZXMpICovCj4gKwlzdGFydF9zdGVwID0g ZGF0YV9vZmZzIC8gY2hpcC0+ZWNjLnNpemU7Cj4gKwllbmRfc3RlcCA9IChkYXRhX29mZnMgKyBy ZWFkbGVuIC0gMSkgLyBjaGlwLT5lY2Muc2l6ZTsKPiArCW51bV9zdGVwcyA9IGVuZF9zdGVwIC0g c3RhcnRfc3RlcCArIDE7Cj4gKwlpbmRleCA9IHN0YXJ0X3N0ZXAgKiBjaGlwLT5lY2MuYnl0ZXM7 Cj4gKwo+ICsJLyogRGF0YSBzaXplIGFsaWduZWQgdG8gRUNDIGVjYy5zaXplICovCj4gKwlkYXRh ZnJhZ19sZW4gPSBudW1fc3RlcHMgKiBjaGlwLT5lY2Muc2l6ZTsKPiArCWVjY2ZyYWdfbGVuID0g bnVtX3N0ZXBzICogY2hpcC0+ZWNjLmJ5dGVzOwo+ICsKPiArCWRhdGFfY29sX2FkZHIgPSBzdGFy dF9zdGVwICogY2hpcC0+ZWNjLnNpemU7Cj4gKwkvKiBJZiB3ZSByZWFkIG5vdCBhIHBhZ2UgYWxp Z25lZCBkYXRhICovCj4gKwlwID0gYnVmcG9pICsgZGF0YV9jb2xfYWRkcjsKPiArCj4gKwkvKiBD YWxjdWxhdGUgRUNDICovCj4gKwlmb3IgKGkgPSAwOyBpIDwgZWNjZnJhZ19sZW47IGkgKz0gY2hp cC0+ZWNjLmJ5dGVzLCBwICs9IGNoaXAtPmVjYy5zaXplKQo+ICsJCWNoaXAtPmVjYy5jYWxjdWxh dGUoY2hpcCwgcCwgJmNoaXAtPmVjYy5jYWxjX2J1ZltpXSk7Cj4gKwo+ICsJcmV0ID0gbXRkX29v YmxheW91dF9maW5kX2VjY3JlZ2lvbihtdGQsIGluZGV4LCAmc2VjdGlvbiwgJm9vYnJlZ2lvbik7 Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJYWxpZ25lZF9wb3MgPSBvb2Jy ZWdpb24ub2Zmc2V0ICYgfihidXN3IC0gMSk7Cj4gKwlhbGlnbmVkX2xlbiA9IGVjY2ZyYWdfbGVu Owo+ICsJaWYgKG9vYnJlZ2lvbi5vZmZzZXQgJiAoYnVzdyAtIDEpKQo+ICsJCWFsaWduZWRfbGVu Kys7Cj4gKwlpZiAoKG9vYnJlZ2lvbi5vZmZzZXQgKyAobnVtX3N0ZXBzICogY2hpcC0+ZWNjLmJ5 dGVzKSkgJiAoYnVzdyAtIDEpKQo+ICsJCWFsaWduZWRfbGVuKys7Cj4gKwo+ICsJbWVtY3B5KCZj aGlwLT5vb2JfcG9pW2FsaWduZWRfcG9zXSwKPiArCSAgICAgICBidWZwb2kgKyBtdGQtPndyaXRl c2l6ZSArIGFsaWduZWRfcG9zLCBhbGlnbmVkX2xlbik7Cj4gKwo+ICsJcmV0ID0gbXRkX29vYmxh eW91dF9nZXRfZWNjYnl0ZXMobXRkLCBjaGlwLT5lY2MuY29kZV9idWYsCj4gKwkJCQkJIGNoaXAt Pm9vYl9wb2ksIGluZGV4LCBlY2NmcmFnX2xlbik7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiBy ZXQ7Cj4gKwo+ICsJcCA9IGJ1ZnBvaSArIGRhdGFfY29sX2FkZHI7Cj4gKwlmb3IgKGkgPSAwOyBp IDwgZWNjZnJhZ19sZW47IGkgKz0gY2hpcC0+ZWNjLmJ5dGVzLCBwICs9IGNoaXAtPmVjYy5zaXpl KSB7Cj4gKwkJaW50IHN0YXQ7Cj4gKwo+ICsJCXN0YXQgPSBjaGlwLT5lY2MuY29ycmVjdChjaGlw LCBwLCAmY2hpcC0+ZWNjLmNvZGVfYnVmW2ldLAo+ICsJCQkJCSAmY2hpcC0+ZWNjLmNhbGNfYnVm W2ldKTsKPiArCQlpZiAoc3RhdCkKPiArCQkJbHMxeF9uYW5kX2R1bXBfcmVncyhjaGlwKTsKPiAr Cj4gKwkJaWYgKHN0YXQgPT0gLUVCQURNU0cgJiYKPiArCQkgICAgKGNoaXAtPmVjYy5vcHRpb25z ICYgTkFORF9FQ0NfR0VORVJJQ19FUkFTRURfQ0hFQ0spKSB7Cj4gKwkJCS8qIGNoZWNrIGZvciBl bXB0eSBwYWdlcyB3aXRoIGJpdGZsaXBzICovCj4gKwkJCXN0YXQgPSBuYW5kX2NoZWNrX2VyYXNl ZF9lY2NfY2h1bmsocCwgY2hpcC0+ZWNjLnNpemUsCj4gKwkJCQkJCQkmY2hpcC0+ZWNjLmNvZGVf YnVmW2ldLAo+ICsJCQkJCQkJY2hpcC0+ZWNjLmJ5dGVzLAo+ICsJCQkJCQkJTlVMTCwgMCwKPiAr CQkJCQkJCWNoaXAtPmVjYy5zdHJlbmd0aCk7Cj4gKwkJfQo+ICsKPiArCQlpZiAoc3RhdCA8IDAp IHsKPiArCQkJbXRkLT5lY2Nfc3RhdHMuZmFpbGVkKys7Cj4gKwkJfSBlbHNlIHsKPiArCQkJbXRk LT5lY2Nfc3RhdHMuY29ycmVjdGVkICs9IHN0YXQ7Cj4gKwkJCW1heF9iaXRmbGlwcyA9IG1heF90 KHVuc2lnbmVkIGludCwgbWF4X2JpdGZsaXBzLCBzdGF0KTsKPiArCQl9Cj4gKwl9Cj4gKwlyZXR1 cm4gbWF4X2JpdGZsaXBzOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGxzMXhfbmFuZF9hdHRhY2hf Y2hpcChzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwKQo+ICt7Cj4gKwlzdHJ1Y3QgbHMxeF9uYW5kICpu YW5kID0gbmFuZF9nZXRfY29udHJvbGxlcl9kYXRhKGNoaXApOwo+ICsJc3RydWN0IGxzMXhfbmFu ZF9jb250cm9sbGVyICpuYyA9ICZuYW5kLT5uYzsKPiArCXN0cnVjdCBwbGF0X2xzMXhfbmFuZCAq cGRhdGEgPSBuYW5kLT5wZGF0YTsKPiArCWludCBob2xkX2N5Y2xlID0gcGRhdGEtPmhvbGRfY3lj bGU7Cj4gKwlpbnQgd2FpdF9jeWNsZSA9IHBkYXRhLT53YWl0X2N5Y2xlOwo+ICsJdTY0IGNoaXBz aXplID0gbmFuZGRldl90YXJnZXRfc2l6ZSgmY2hpcC0+YmFzZSk7Cj4gKwlpbnQgY2VsbF9zaXpl ID0gMDsKPiArCgpZb3Ugc2hvdWxkIHNvbWVob3cgYmUgYWJsZSB0byBjb25maWd1cmUgdGhlIGNv bnRyb2xsZXIgdG8gd29yayBpbgpzb2Z0d2FyZSBtb2RlIG9yIHdpdGhvdXQgRUNDIGZvciBkZWJ1 ZyBwdXJwb3Nlcy4gUGxlYXNlIGFkZCBhbmQgdGVzdAp0aG9zZSB0d28gZmVhdHVyZXMuCgo+ICsJ c3dpdGNoIChjaGlwc2l6ZSkgewo+ICsJY2FzZSBTWl8xMjhNOgo+ICsJCWNlbGxfc2l6ZSA9IDB4 MDsKPiArCQlicmVhazsKPiArCWNhc2UgU1pfMjU2TToKPiArCQljZWxsX3NpemUgPSAweDE7Cj4g KwkJYnJlYWs7Cj4gKwljYXNlIFNaXzUxMk06Cj4gKwkJY2VsbF9zaXplID0gMHgyOwo+ICsJCWJy ZWFrOwo+ICsJY2FzZSBTWl8xRzoKPiArCQljZWxsX3NpemUgPSAweDM7Cj4gKwkJYnJlYWs7Cj4g KwljYXNlIFNaXzJHOgo+ICsJCWNlbGxfc2l6ZSA9IDB4NDsKPiArCQlicmVhazsKPiArCWNhc2Ug U1pfNEc6Cj4gKwkJY2VsbF9zaXplID0gMHg1Owo+ICsJCWJyZWFrOwo+ICsJY2FzZSAoU1pfMkcg KiBTWl80Ryk6CS8qOEcgKi8KPiArCQljZWxsX3NpemUgPSAweDY7Cj4gKwkJYnJlYWs7Cj4gKwlj YXNlIChTWl80RyAqIFNaXzRHKToJLyoxNkcgKi8KPiArCQljZWxsX3NpemUgPSAweDc7Cj4gKwkJ YnJlYWs7Cj4gKwlkZWZhdWx0Ogo+ICsJCWRldl9lcnIobmFuZC0+ZGV2LCAidW5zdXBwb3J0ZWQg Y2hpcCBzaXplOiAlbGx1IE1CXG4iLAo+ICsJCQljaGlwc2l6ZSk7Cj4gKwkJYnJlYWs7Cj4gKwl9 Cj4gKwo+ICsJaWYgKGhvbGRfY3ljbGUgJiYgd2FpdF9jeWNsZSkKPiArCQluYW5kX3dyaXRlbChu YywgTkFORF9USU1JTkcsCj4gKwkJCSAgICAoaG9sZF9jeWNsZSA8PCBCSVRTX1BFUl9CWVRFKSB8 IHdhaXRfY3ljbGUpOwo+ICsJbmFuZF93cml0ZWwobmMsIE5BTkRfUEFSQU0sCj4gKwkJICAgIChu YW5kX3JlYWRsKG5jLCBOQU5EX1BBUkFNKSAmIH5TSVpFX01BU0spIHwgY2VsbF9zaXplIDw8Cj4g KwkJICAgIEJJVFNfUEVSX0JZVEUpOwoKUGxlYXNlIGRvIHRoaXMgaW4gdGhyZWUgc3RlcHMgZm9y IHJlYWRhYmlsaXR5OgoKcGFyYW0gPSBuYW5kX3JlYWRsKCkKcGFyYW0gfD0gY2VsbF9zaXplLi4u Cm5hbmRfd3JpdGVsKCkKCj4gKwo+ICsJY2hpcC0+ZWNjLnJlYWRfcGFnZV9yYXcgPSBuYW5kX21v bm9saXRoaWNfcmVhZF9wYWdlX3JhdzsKPiArCWNoaXAtPmVjYy53cml0ZV9wYWdlX3JhdyA9IG5h bmRfbW9ub2xpdGhpY193cml0ZV9wYWdlX3JhdzsKCk5pY2UgOikKCj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgbmFuZF9jb250cm9sbGVyX29wcyBsczF4 X25jX29wcyA9IHsKPiArCS5leGVjX29wID0gbHMxeF9uYW5kX2V4ZWNfb3AsCj4gKwkuYXR0YWNo X2NoaXAgPSBsczF4X25hbmRfYXR0YWNoX2NoaXAsCj4gK307Cj4gKwo+ICtzdGF0aWMgdm9pZCBs czF4X25hbmRfY29udHJvbGxlcl9jbGVhbnVwKHN0cnVjdCBsczF4X25hbmQgKm5hbmQpCj4gK3sK PiArCWlmIChuYW5kLT5uYy5kbWFfY2hhbikKPiArCQlkbWFfcmVsZWFzZV9jaGFubmVsKG5hbmQt Pm5jLmRtYV9jaGFuKTsKPiArfQo+ICsKPiArc3RhdGljIGludCBsczF4X25hbmRfY29udHJvbGxl cl9pbml0KHN0cnVjdCBsczF4X25hbmQgKm5hbmQsCj4gKwkJCQkgICAgIHN0cnVjdCBwbGF0Zm9y bV9kZXZpY2UgKnBkZXYpCj4gK3sKPiArCXN0cnVjdCBsczF4X25hbmRfY29udHJvbGxlciAqbmMg PSAmbmFuZC0+bmM7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXYgPSAmcGRldi0+ZGV2Owo+ICsJc3Ry dWN0IGRtYV9zbGF2ZV9jb25maWcgY2ZnOwo+ICsJc3RydWN0IHJlc291cmNlICpyZXM7Cj4gKwlp bnQgcmV0Owo+ICsKPiArCW5jLT5yZWdfYmFzZSA9IGRldm1fcGxhdGZvcm1faW9yZW1hcF9yZXNv dXJjZShwZGV2LCAwKTsKPiArCWlmIChJU19FUlIobmMtPnJlZ19iYXNlKSkKPiArCQlyZXR1cm4g UFRSX0VSUihuYy0+cmVnX2Jhc2UpOwo+ICsKPiArCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJj ZShwZGV2LCBJT1JFU09VUkNFX0RNQSwgMCk7Cj4gKwlpZiAoIXJlcykgewo+ICsJCWRldl9lcnIo ZGV2LCAiZmFpbGVkIHRvIGdldCBETUEgaW5mb3JtYXRpb24hXG4iKTsKPiArCQlyZXR1cm4gLUVO WElPOwo+ICsJfQo+ICsKPiArCW5jLT5kbWFfY2hhbiA9IGRtYV9yZXF1ZXN0X2NoYW4oZGV2LCBy ZXMtPm5hbWUpOwo+ICsJaWYgKCFuYy0+ZG1hX2NoYW4pIHsKPiArCQlkZXZfZXJyKGRldiwgImZh aWxlZCB0byByZXF1ZXN0IERNQSBjaGFubmVsIVxuIik7Cj4gKwkJcmV0dXJuIC1FQlVTWTsKPiAr CX0KPiArCWRldl9pbmZvKGRldiwgImdvdCAlcyBmb3IgJXMgYWNjZXNzXG4iLAo+ICsJCSBkbWFf Y2hhbl9uYW1lKG5jLT5kbWFfY2hhbiksIGRldl9uYW1lKGRldikpOwo+ICsKPiArCWNmZy5zcmNf YWRkciA9IENQSFlTQUREUihuYy0+cmVnX2Jhc2UgKyBOQU5EX0RNQV9BRERSKTsKPiArCWNmZy5k c3RfYWRkciA9IENQSFlTQUREUihuYy0+cmVnX2Jhc2UgKyBOQU5EX0RNQV9BRERSKTsKPiArCWNm Zy5zcmNfYWRkcl93aWR0aCA9IERNQV9TTEFWRV9CVVNXSURUSF80X0JZVEVTOwo+ICsJY2ZnLmRz dF9hZGRyX3dpZHRoID0gRE1BX1NMQVZFX0JVU1dJRFRIXzRfQllURVM7Cj4gKwlyZXQgPSBkbWFl bmdpbmVfc2xhdmVfY29uZmlnKG5jLT5kbWFfY2hhbiwgJmNmZyk7Cj4gKwlpZiAocmV0KSB7Cj4g KwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gY29uZmlnIERNQSBjaGFubmVsIVxuIik7Cj4gKwkJ ZG1hX3JlbGVhc2VfY2hhbm5lbChuYy0+ZG1hX2NoYW4pOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9 Cj4gKwo+ICsJaW5pdF9jb21wbGV0aW9uKCZuYy0+ZG1hX2NvbXBsZXRlKTsKPiArCj4gKwlyZXR1 cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIGludCBsczF4X25hbmRfY2hpcF9pbml0KHN0cnVjdCBs czF4X25hbmQgKm5hbmQpCj4gK3sKPiArCXN0cnVjdCBuYW5kX2NoaXAgKmNoaXAgPSAmbmFuZC0+ Y2hpcDsKPiArCXN0cnVjdCBtdGRfaW5mbyAqbXRkID0gbmFuZF90b19tdGQoY2hpcCk7Cj4gKwlz dHJ1Y3QgcGxhdF9sczF4X25hbmQgKnBkYXRhID0gbmFuZC0+cGRhdGE7Cj4gKwlpbnQgcmV0ID0g MDsKPiArCj4gKwljaGlwLT5jb250cm9sbGVyID0gJm5hbmQtPmNvbnRyb2xsZXI7Cj4gKwljaGlw LT5vcHRpb25zID0gTkFORF9OT19TVUJQQUdFX1dSSVRFIHwgTkFORF9VU0VTX0RNQSB8IE5BTkRf QlJPS0VOX1hEOwo+ICsJY2hpcC0+YnVmX2FsaWduID0gMTY7Cj4gKwljaGlwLT5lY2MuZW5naW5l X3R5cGUgPSBOQU5EX0VDQ19FTkdJTkVfVFlQRV9TT0ZUOwo+ICsJY2hpcC0+ZWNjLmFsZ28gPSBO QU5EX0VDQ19BTEdPX0hBTU1JTkc7CgpFQ0MgY29uZmlndXJhdGlvbiBzaG91bGQgb25seSBiZSBk b25lIGluIC0+YXR0YWNoX2NoaXAoKS4KCj4gKwluYW5kX3NldF9jb250cm9sbGVyX2RhdGEoY2hp cCwgbmFuZCk7Cj4gKwo+ICsJbXRkLT5kZXYucGFyZW50ID0gbmFuZC0+ZGV2Owo+ICsJbXRkLT5u YW1lID0gImxzMXgtbmFuZCI7Cj4gKwltdGQtPm93bmVyID0gVEhJU19NT0RVTEU7Cj4gKwo+ICsJ cmV0ID0gbmFuZF9zY2FuKGNoaXAsIDEpOwo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0Owo+ ICsKPiArCWNoaXAtPmVjYy5yZWFkX3N1YnBhZ2UgPSBsczF4X25hbmRfcmVhZF9zdWJwYWdlOwoK RG8geW91IHJlYWxseSBuZWVkIHRoaXM/IEl0IGxvb2tzIGxpa2UgeW91ciBpbXBsZW1lbnRhdGlv biBvZgpyZWFkX3N1YnBhZ2UgaXMgdmVyeSBzaW1pbGFyIHRvIHRoZSBvbmUgZnJvbSB0aGUgY29y ZS4KCj4gKwo+ICsJcmV0ID0gbXRkX2RldmljZV9yZWdpc3RlcihtdGQsIHBkYXRhLT5wYXJ0cywg cGRhdGEtPm5yX3BhcnRzKTsKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJyKG5hbmQtPmRldiwg ImZhaWxlZCB0byByZWdpc3RlciBNVEQgZGV2aWNlISAlZFxuIiwgcmV0KTsKPiArCQluYW5kX2Ns ZWFudXAoY2hpcCk7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIHJldDsKPiArfQo+ICsKPiArc3RhdGlj IGludCBsczF4X25hbmRfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ ICsJc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiArCXN0cnVjdCBwbGF0X2xzMXhf bmFuZCAqcGRhdGE7Cj4gKwlzdHJ1Y3QgbHMxeF9uYW5kICpuYW5kOwoKUGxlYXNlIHVzZSBhbm90 aGVyIG5hbWUgZm9yIHRoZSB2YXJpYWJsZSwgIm5hbmQiLyJjaGlwIiBpcyB1c2VkIGJ5IHRoZQpj b3JlIGZvciB0aGUgbmFuZF9jaGlwIHN0cnVjdHVyZSwgZm9yIHlvdXJzIHlvdSBjYW4gbmFtZSBp dCBlZyBsczF4IG9yCmxzbmFuZC4KCj4gKwlpbnQgcmV0Owo+ICsKPiArCXBkYXRhID0gZGV2X2dl dF9wbGF0ZGF0YShkZXYpOwo+ICsJaWYgKCFwZGF0YSkgewo+ICsJCWRldl9lcnIoZGV2LCAicGxh dGZvcm0gZGF0YSBtaXNzaW5nIVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ ICsJbmFuZCA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZigqbmFuZCksIEdGUF9LRVJORUwpOwo+ ICsJaWYgKCFuYW5kKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCW5hbmQtPnBkYXRhID0g cGRhdGE7Cj4gKwluYW5kLT5kZXYgPSBkZXY7Cj4gKwluYW5kLT5jb250cm9sbGVyLm9wcyA9ICZs czF4X25jX29wczsKPiArCW5hbmRfY29udHJvbGxlcl9pbml0KCZuYW5kLT5jb250cm9sbGVyKTsK PiArCj4gKwlyZXQgPSBsczF4X25hbmRfY29udHJvbGxlcl9pbml0KG5hbmQsIHBkZXYpOwoKSSdt IG5vdCBzdXJlIHRoaXMgZGVzZXJ2ZXMgYSBoZWxwZXIgKHNhbWUgZm9yIHRoZSBjaGlwIGluaXQp IGJ1dCB3aHkKbm90LgoKPiArCWlmIChyZXQpCj4gKwkJcmV0dXJuIHJldDsKPiArCj4gKwluYW5k LT5jbGsgPSBkZXZtX2Nsa19nZXQoZGV2LCBwZGV2LT5uYW1lKTsKPiArCWlmIChJU19FUlIobmFu ZC0+Y2xrKSkgewo+ICsJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGdldCAlcyBjbG9jayFcbiIs IHBkZXYtPm5hbWUpOwo+ICsJCXJldHVybiBQVFJfRVJSKG5hbmQtPmNsayk7Cj4gKwl9Cj4gKwlj bGtfcHJlcGFyZV9lbmFibGUobmFuZC0+Y2xrKTsKPiArCj4gKwlyZXQgPSBsczF4X25hbmRfY2hp cF9pbml0KG5hbmQpOwo+ICsJaWYgKHJldCkgewo+ICsJCWNsa19kaXNhYmxlX3VucHJlcGFyZShu YW5kLT5jbGspOwo+ICsJCWdvdG8gZXJyOwo+ICsJfQo+ICsKPiArCXBsYXRmb3JtX3NldF9kcnZk YXRhKHBkZXYsIG5hbmQpOwo+ICsJZGV2X2luZm8oZGV2LCAiTG9vbmdzb24xIE5BTkQgZHJpdmVy IHJlZ2lzdGVyZWRcbiIpOwoKSSBkb24ndCB0aGluayB0aGlzIGlzIHVzZWZ1bCwgeW91IGNhbiBk cm9wIHRoYXQgdHJhY2UuCgo+ICsKPiArCXJldHVybiAwOwo+ICtlcnI6Cj4gKwlsczF4X25hbmRf Y29udHJvbGxlcl9jbGVhbnVwKG5hbmQpOwo+ICsJcmV0dXJuIHJldDsKPiArfQo+ICsKPiArc3Rh dGljIGludCBsczF4X25hbmRfcmVtb3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4g K3sKPiArCXN0cnVjdCBsczF4X25hbmQgKm5hbmQgPSBwbGF0Zm9ybV9nZXRfZHJ2ZGF0YShwZGV2 KTsKPiArCXN0cnVjdCBuYW5kX2NoaXAgKmNoaXAgPSAmbmFuZC0+Y2hpcDsKPiArCj4gKwltdGRf ZGV2aWNlX3VucmVnaXN0ZXIobmFuZF90b19tdGQoY2hpcCkpOwoKcmV0ID0gbXRkX2RldmljZV91 bnJlZ2lzdGVyKCkKV0FSTl9PTihyZXQpOwoKPiArCW5hbmRfY2xlYW51cChjaGlwKTsKPiArCWNs a19kaXNhYmxlX3VucHJlcGFyZShuYW5kLT5jbGspOwo+ICsJbHMxeF9uYW5kX2NvbnRyb2xsZXJf Y2xlYW51cChuYW5kKTsKPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIHN0cnVj dCBwbGF0Zm9ybV9kcml2ZXIgbHMxeF9uYW5kX2RyaXZlciA9IHsKPiArCS5wcm9iZQk9IGxzMXhf bmFuZF9wcm9iZSwKPiArCS5yZW1vdmUJPSBsczF4X25hbmRfcmVtb3ZlLAo+ICsJLmRyaXZlcgk9 IHsKPiArCQkubmFtZQk9ICJsczF4LW5hbmQiLAoKbHMxeC1uYW5kLWNvbnRyb2xsZXIKCj4gKwkJ Lm93bmVyCT0gVEhJU19NT0RVTEUsCj4gKwl9LAo+ICt9Owo+ICsKPiArbW9kdWxlX3BsYXRmb3Jt X2RyaXZlcihsczF4X25hbmRfZHJpdmVyKTsKPiArCj4gK01PRFVMRV9BVVRIT1IoIktlbHZpbiBD aGV1bmcgPGtlZ3VhbmcuemhhbmdAZ21haWwuY29tPiIpOwo+ICtNT0RVTEVfREVTQ1JJUFRJT04o Ikxvb25nc29uMSBOQU5EIEZsYXNoIGRyaXZlciIpOwo+ICtNT0RVTEVfTElDRU5TRSgiR1BMIik7 Cj4gCj4gYmFzZS1jb21taXQ6IGZkMGQ4ZDg1ZjcyMzAwNTJlNjM4YTU2ZDFiZmVhMTcwYzQ4OGU2 YmMKCgoKClRoYW5rcywKTWlxdcOobAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCkxpbnV4IE1URCBkaXNjdXNzaW9uIG1haWxpbmcgbGlzdApo dHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LW10ZC8K