From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: [intel-linux-intel-lts:5.4/yocto 63/1142] drivers/gpu/drm/kmb/kmb_crtc.c:101:6: warning: variable 'vsync_end_offset' set but not used
Date: Fri, 13 Aug 2021 20:31:21 +0800 [thread overview]
Message-ID: <202108132011.411UwfB2-lkp@intel.com> (raw)
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tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: eeb611e5394c56d45c5cc8f7dc484c9f19e93143
commit: 5b522e237ca8396c9f947adca5090316dbec5e4c [63/1142] drm/kmb: Set hardcoded values to LCD_VSYNC_START
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 10.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel/linux-intel-lts/commit/5b522e237ca8396c9f947adca5090316dbec5e4c
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 5b522e237ca8396c9f947adca5090316dbec5e4c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/kmb/kmb_crtc.c: In function 'kmb_crtc_mode_set_nofb':
>> drivers/gpu/drm/kmb/kmb_crtc.c:101:6: warning: variable 'vsync_end_offset' set but not used [-Wunused-but-set-variable]
101 | int vsync_end_offset;
| ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/kmb/kmb_crtc.c:100:6: warning: variable 'vsync_start_offset' set but not used [-Wunused-but-set-variable]
100 | int vsync_start_offset;
| ^~~~~~~~~~~~~~~~~~
vim +/vsync_end_offset +101 drivers/gpu/drm/kmb/kmb_crtc.c
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 94
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 95 static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc)
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 96 {
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 97 struct drm_display_mode *m = &crtc->state->adjusted_mode;
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 98 struct drm_device *dev = crtc->dev;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 99 struct videomode vm;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 @100 int vsync_start_offset;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 @101 int vsync_end_offset;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 102 unsigned int ctrl = 0;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 103
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 104 vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 105 vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 106 vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 107 vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 108 vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 109 vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 110
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 111 vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 112 vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 113
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 114 kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT,
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 115 m->crtc_vdisplay - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 116 kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 117 kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 118 kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 119 kmb_write_lcd(dev->dev_private, LCD_H_ACTIVEWIDTH,
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 120 m->crtc_hdisplay - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 121 kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 122 kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 123 kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
5b522e237ca839 Anitha Chrisanthus 2019-07-12 124 /*this is hardcoded as 0 in the Myriadx code */
5b522e237ca839 Anitha Chrisanthus 2019-07-12 125 kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0);
5b522e237ca839 Anitha Chrisanthus 2019-07-12 126 kmb_write_lcd(dev->dev_private, LCD_VSYNC_END, 0);
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 127
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 128 if (m->flags == DRM_MODE_FLAG_INTERLACE) {
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 129 kmb_write_lcd(dev->dev_private,
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 130 LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 131 kmb_write_lcd(dev->dev_private,
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 132 LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1);
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 133 kmb_write_lcd(dev->dev_private,
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 134 LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1);
5b522e237ca839 Anitha Chrisanthus 2019-07-12 135 kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN,
5b522e237ca839 Anitha Chrisanthus 2019-07-12 136 m->crtc_vdisplay - 1);
5b522e237ca839 Anitha Chrisanthus 2019-07-12 137 /*this is hardcoded as 10 in the Myriadx code*/
5b522e237ca839 Anitha Chrisanthus 2019-07-12 138 kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10);
5b522e237ca839 Anitha Chrisanthus 2019-07-12 139 kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10);
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 140 }
be391352d5d5a3 Anitha Chrisanthus 2019-01-30 141 /* enable VL1 layer as default */
be391352d5d5a3 Anitha Chrisanthus 2019-01-30 142 ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 143 ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 144 | LCD_CTRL_OUTPUT_ENABLED;
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 145 kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl);
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 146
c3b85e057bb630 Anitha Chrisanthus 2019-06-20 147 kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE);
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 148
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 149 /* TBD */
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 150 /* set clocks here */
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 151 }
767c8610f6fcd7 Anitha Chrisanthus 2018-11-29 152
:::::: The code at line 101 was first introduced by commit
:::::: 767c8610f6fcd7b765189fc01eff0131aa6c19d5 drm/kmb: Add support for KeemBay Display
:::::: TO: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
:::::: CC: Li, Yifan <yifan2.li@intel.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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