* [freescale-fslc:pr/416 15241/20667] arch/arm/mach-imx/busfreq_optee.c:108:5: warning: no previous prototype for 'update_freq_optee'
@ 2021-08-22 16:51 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2021-08-22 16:51 UTC (permalink / raw)
To: kbuild-all
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Hi Jason,
First bad commit (maybe != root cause):
tree: https://github.com/Freescale/linux-fslc pr/416
head: 915e71b823c877d351de1cbe650344ef6eace94b
commit: 5bb09de3044acf91e6f8c712c026d5a4bc53b563 [15241/20667] MLK-24874-1: include: uapi: fmd: fix the UAPI_HEADER_TEST/install failure
config: arm-allyesconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/Freescale/linux-fslc/commit/5bb09de3044acf91e6f8c712c026d5a4bc53b563
git remote add freescale-fslc https://github.com/Freescale/linux-fslc
git fetch --no-tags freescale-fslc pr/416
git checkout 5bb09de3044acf91e6f8c712c026d5a4bc53b563
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> arch/arm/mach-imx/busfreq_optee.c:108:5: warning: no previous prototype for 'update_freq_optee' [-Wmissing-prototypes]
108 | int update_freq_optee(int ddr_rate)
| ^~~~~~~~~~~~~~~~~
>> arch/arm/mach-imx/busfreq_optee.c:281:5: warning: no previous prototype for 'init_freq_optee' [-Wmissing-prototypes]
281 | int init_freq_optee(struct platform_device *busfreq_pdev)
| ^~~~~~~~~~~~~~~
vim +/update_freq_optee +108 arch/arm/mach-imx/busfreq_optee.c
7c335a91f0f4c6a Cedric Neveux 2018-10-18 99
7c335a91f0f4c6a Cedric Neveux 2018-10-18 100 /**
7c335a91f0f4c6a Cedric Neveux 2018-10-18 101 * @brief Request OPTEE OS to change the memory bus frequency
7c335a91f0f4c6a Cedric Neveux 2018-10-18 102 * to \a ddr_rate value
7c335a91f0f4c6a Cedric Neveux 2018-10-18 103 *
7c335a91f0f4c6a Cedric Neveux 2018-10-18 104 * @param[in] rate Bus Frequency
7c335a91f0f4c6a Cedric Neveux 2018-10-18 105 *
7c335a91f0f4c6a Cedric Neveux 2018-10-18 106 * @retval 0 Success
7c335a91f0f4c6a Cedric Neveux 2018-10-18 107 */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 @108 int update_freq_optee(int ddr_rate)
7c335a91f0f4c6a Cedric Neveux 2018-10-18 109 {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 110 struct arm_smccc_res res;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 111
7c335a91f0f4c6a Cedric Neveux 2018-10-18 112 uint32_t me = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 113 uint32_t dll_off = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 114 int mode = get_bus_freq_mode();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 115
7c335a91f0f4c6a Cedric Neveux 2018-10-18 116 #ifdef CONFIG_SMP
7c335a91f0f4c6a Cedric Neveux 2018-10-18 117 uint32_t reg = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 118 uint32_t cpu = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 119 uint32_t online_cpus = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 120 uint32_t all_cpus = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 121 #endif
7c335a91f0f4c6a Cedric Neveux 2018-10-18 122
c2e58ab882a1953 Cedric Neveux 2018-11-16 123 pr_info("\nBusfreq OPTEE set from %d to %d start...\n",
7c335a91f0f4c6a Cedric Neveux 2018-10-18 124 curr_ddr_rate, ddr_rate);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 125
7c335a91f0f4c6a Cedric Neveux 2018-10-18 126 if (ddr_rate == curr_ddr_rate)
7c335a91f0f4c6a Cedric Neveux 2018-10-18 127 return 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 128
7c335a91f0f4c6a Cedric Neveux 2018-10-18 129 if (cpu_is_imx6()) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 130 if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO))
7c335a91f0f4c6a Cedric Neveux 2018-10-18 131 dll_off = 1;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 132 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 133
7c335a91f0f4c6a Cedric Neveux 2018-10-18 134 local_irq_disable();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 135
7c335a91f0f4c6a Cedric Neveux 2018-10-18 136 #ifdef CONFIG_SMP
7c335a91f0f4c6a Cedric Neveux 2018-10-18 137 me = smp_processor_id();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 138
7c335a91f0f4c6a Cedric Neveux 2018-10-18 139 /* Make sure all the online cores to be active */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 140 do {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 141 all_cpus = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 142
7c335a91f0f4c6a Cedric Neveux 2018-10-18 143 for_each_online_cpu(cpu)
7c335a91f0f4c6a Cedric Neveux 2018-10-18 144 all_cpus |= (pSync->wfe_status[cpu] << cpu);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 145 } while (all_cpus);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 146
7c335a91f0f4c6a Cedric Neveux 2018-10-18 147 pSync->change_ongoing = 1;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 148 dsb();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 149
7c335a91f0f4c6a Cedric Neveux 2018-10-18 150 for_each_online_cpu(cpu) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 151 if (cpu != me) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 152 online_cpus |= (1 << cpu);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 153 /* Set the interrupt to be pending in the GIC. */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 154 reg = 1 << (irqs_for_wfe[cpu] % 32);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 155 writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
7c335a91f0f4c6a Cedric Neveux 2018-10-18 156 + (irqs_for_wfe[cpu] / 32) * 4);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 157 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 158 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 159
7c335a91f0f4c6a Cedric Neveux 2018-10-18 160 /* Wait for all active CPUs to be in WFE */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 161 do {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 162 all_cpus = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 163
7c335a91f0f4c6a Cedric Neveux 2018-10-18 164 for_each_online_cpu(cpu)
7c335a91f0f4c6a Cedric Neveux 2018-10-18 165 all_cpus |= (pSync->wfe_status[cpu] << cpu);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 166 } while (all_cpus != online_cpus);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 167
7c335a91f0f4c6a Cedric Neveux 2018-10-18 168 #endif
7c335a91f0f4c6a Cedric Neveux 2018-10-18 169
7c335a91f0f4c6a Cedric Neveux 2018-10-18 170 /* Now we can change the DDR frequency. */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 171 /* Call the TEE SiP */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 172 arm_smccc_smc(OPTEE_SMC_FAST_CALL_SIP_VAL(IMX_SIP_BUSFREQ_CHANGE),
7c335a91f0f4c6a Cedric Neveux 2018-10-18 173 ddr_rate, dll_off, 0, 0, 0, 0, 0, &res);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 174
7c335a91f0f4c6a Cedric Neveux 2018-10-18 175 curr_ddr_rate = ddr_rate;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 176
7c335a91f0f4c6a Cedric Neveux 2018-10-18 177 #ifdef CONFIG_SMP
7c335a91f0f4c6a Cedric Neveux 2018-10-18 178 /* DDR frequency change is done */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 179 pSync->change_ongoing = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 180 dsb();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 181
7c335a91f0f4c6a Cedric Neveux 2018-10-18 182 /* wake up all the cores. */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 183 sev();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 184 #endif
7c335a91f0f4c6a Cedric Neveux 2018-10-18 185
7c335a91f0f4c6a Cedric Neveux 2018-10-18 186 local_irq_enable();
7c335a91f0f4c6a Cedric Neveux 2018-10-18 187
c2e58ab882a1953 Cedric Neveux 2018-11-16 188 pr_info("Busfreq OPTEE set to %d done! cpu=%d\n",
c2e58ab882a1953 Cedric Neveux 2018-11-16 189 ddr_rate, me);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 190
7c335a91f0f4c6a Cedric Neveux 2018-10-18 191 return 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 192 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 193
2fc7c702e104bff Cedric Neveux 2018-11-22 194 #ifdef CONFIG_SMP
7c335a91f0f4c6a Cedric Neveux 2018-10-18 195 static int init_freq_optee_smp(struct platform_device *busfreq_pdev)
7c335a91f0f4c6a Cedric Neveux 2018-10-18 196 {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 197 struct device_node *node = 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 198 struct device *dev = &busfreq_pdev->dev;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 199 uint32_t cpu;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 200 int err;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 201 int irq;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 202 struct irq_data *irq_data;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 203 unsigned long wfe_iram_base;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 204
7c335a91f0f4c6a Cedric Neveux 2018-10-18 205 if (cpu_is_imx6()) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 206 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
7c335a91f0f4c6a Cedric Neveux 2018-10-18 207 if (!node) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 208 if (cpu_is_imx6q())
7c335a91f0f4c6a Cedric Neveux 2018-10-18 209 pr_debug("failed to find imx6q-a9-gic device tree data!\n");
7c335a91f0f4c6a Cedric Neveux 2018-10-18 210
7c335a91f0f4c6a Cedric Neveux 2018-10-18 211 return -EINVAL;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 212 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 213 } else {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 214 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic");
7c335a91f0f4c6a Cedric Neveux 2018-10-18 215 if (!node) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 216 pr_debug("failed to find imx7d-a7-gic device tree data!\n");
7c335a91f0f4c6a Cedric Neveux 2018-10-18 217 return -EINVAL;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 218 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 219 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 220
7c335a91f0f4c6a Cedric Neveux 2018-10-18 221 gic_dist_base = of_iomap(node, 0);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 222 WARN(!gic_dist_base, "unable to map gic dist registers\n");
7c335a91f0f4c6a Cedric Neveux 2018-10-18 223
7c335a91f0f4c6a Cedric Neveux 2018-10-18 224 irqs_for_wfe = devm_kzalloc(dev, sizeof(uint32_t) * num_present_cpus(),
7c335a91f0f4c6a Cedric Neveux 2018-10-18 225 GFP_KERNEL);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 226
7c335a91f0f4c6a Cedric Neveux 2018-10-18 227 for_each_online_cpu(cpu) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 228 /*
7c335a91f0f4c6a Cedric Neveux 2018-10-18 229 * set up a reserved interrupt to get all
7c335a91f0f4c6a Cedric Neveux 2018-10-18 230 * the active cores into a WFE state
7c335a91f0f4c6a Cedric Neveux 2018-10-18 231 * before changing the DDR frequency.
7c335a91f0f4c6a Cedric Neveux 2018-10-18 232 */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 233 irq = platform_get_irq(busfreq_pdev, cpu);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 234
7c335a91f0f4c6a Cedric Neveux 2018-10-18 235 if (cpu_is_imx6()) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 236 err = request_irq(irq, wait_in_wfe_irq,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 237 IRQF_PERCPU, "mmdc_1", NULL);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 238 } else {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 239 err = request_irq(irq, wait_in_wfe_irq,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 240 IRQF_PERCPU, "ddrc", NULL);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 241 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 242
7c335a91f0f4c6a Cedric Neveux 2018-10-18 243 if (err) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 244 dev_err(dev,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 245 "Busfreq:request_irq failed %d, err = %d\n",
7c335a91f0f4c6a Cedric Neveux 2018-10-18 246 irq, err);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 247 return err;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 248 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 249
7c335a91f0f4c6a Cedric Neveux 2018-10-18 250 err = irq_set_affinity(irq, cpumask_of(cpu));
7c335a91f0f4c6a Cedric Neveux 2018-10-18 251 if (err) {
7c335a91f0f4c6a Cedric Neveux 2018-10-18 252 dev_err(dev,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 253 "Busfreq: Cannot set irq affinity irq=%d,\n",
7c335a91f0f4c6a Cedric Neveux 2018-10-18 254 irq);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 255 return err;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 256 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 257
7c335a91f0f4c6a Cedric Neveux 2018-10-18 258 irq_data = irq_get_irq_data(irq);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 259 irqs_for_wfe[cpu] = irq_data->hwirq + 32;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 260 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 261
7c335a91f0f4c6a Cedric Neveux 2018-10-18 262 /* Store the variable used to communicate between cores */
7c335a91f0f4c6a Cedric Neveux 2018-10-18 263 pSync = (void *)ddr_freq_change_iram_base;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 264
7c335a91f0f4c6a Cedric Neveux 2018-10-18 265 memset(pSync, 0, sizeof(*pSync));
7c335a91f0f4c6a Cedric Neveux 2018-10-18 266
7c335a91f0f4c6a Cedric Neveux 2018-10-18 267 wfe_iram_base = ddr_freq_change_iram_base + sizeof(*pSync);
7c335a91f0f4c6a Cedric Neveux 2018-10-18 268
7c335a91f0f4c6a Cedric Neveux 2018-10-18 269 if (wfe_iram_base & (FNCPY_ALIGN - 1))
7c335a91f0f4c6a Cedric Neveux 2018-10-18 270 wfe_iram_base += FNCPY_ALIGN -
7c335a91f0f4c6a Cedric Neveux 2018-10-18 271 ((uintptr_t)wfe_iram_base % (FNCPY_ALIGN));
7c335a91f0f4c6a Cedric Neveux 2018-10-18 272
7c335a91f0f4c6a Cedric Neveux 2018-10-18 273 wfe_change_freq = (void *)fncpy((void *)wfe_iram_base,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 274 &imx_smp_wfe_optee,
7c335a91f0f4c6a Cedric Neveux 2018-10-18 275 ((&imx_smp_wfe_end -&imx_smp_wfe_start) *4));
7c335a91f0f4c6a Cedric Neveux 2018-10-18 276
7c335a91f0f4c6a Cedric Neveux 2018-10-18 277 return 0;
7c335a91f0f4c6a Cedric Neveux 2018-10-18 278
7c335a91f0f4c6a Cedric Neveux 2018-10-18 279 }
7c335a91f0f4c6a Cedric Neveux 2018-10-18 280
7c335a91f0f4c6a Cedric Neveux 2018-10-18 @281 int init_freq_optee(struct platform_device *busfreq_pdev)
:::::: The code at line 108 was first introduced by commit
:::::: 7c335a91f0f4c6a7d7d0f8931e1570025222a379 MLK-20023 Move Busfreq support to OPTEE OS
:::::: TO: Cedric Neveux <cedric.neveux@nxp.com>
:::::: CC: Silvano di Ninno <silvano.dininno@nxp.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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2021-08-22 16:51 [freescale-fslc:pr/416 15241/20667] arch/arm/mach-imx/busfreq_optee.c:108:5: warning: no previous prototype for 'update_freq_optee' kernel test robot
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