From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eddie James Date: Mon, 30 Aug 2021 16:46:44 -0500 Subject: [PATCH 2/2] ARM: dts: aspeed: everest: Add I2C bus 15 muxes In-Reply-To: <20210830214644.58539-1-eajames@linux.ibm.com> References: <20210830214644.58539-1-eajames@linux.ibm.com> Message-ID: <20210830214644.58539-2-eajames@linux.ibm.com> List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Add the muxes that are attached on I2C bus 15. Signed-off-by: Eddie James --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 158 +++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 2efd70666738..e7da58595d14 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -96,6 +96,18 @@ aliases { i2c32 = &i2c14mux1chn1; i2c33 = &i2c14mux1chn2; i2c34 = &i2c14mux1chn3; + i2c35 = &i2c15mux0chn0; + i2c36 = &i2c15mux0chn1; + i2c37 = &i2c15mux0chn2; + i2c38 = &i2c15mux0chn3; + i2c39 = &i2c15mux1chn0; + i2c40 = &i2c15mux1chn1; + i2c41 = &i2c15mux1chn2; + i2c42 = &i2c15mux1chn3; + i2c43 = &i2c15mux2chn0; + i2c44 = &i2c15mux2chn1; + i2c45 = &i2c15mux2chn2; + i2c46 = &i2c15mux2chn3; serial4 = &uart5; @@ -2816,6 +2828,152 @@ eeprom at 50 { &i2c15 { status = "okay"; + + i2c-switch at 70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux0chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux0chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux0chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux0chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; + + i2c-switch at 71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux1chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux1chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux1chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux1chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; + + i2c-switch at 72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c15mux2chn0: i2c at 0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux2chn1: i2c at 1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom at 50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c15mux2chn2: i2c at 2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c15mux2chn3: i2c at 3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; }; &ehci1 { -- 2.27.0