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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id x15sm12057669pgt.34.2021.09.14.11.57.24 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Sep 2021 11:57:25 -0700 (PDT) Date: Tue, 14 Sep 2021 11:49:34 -0700 From: Nicolin Chen To: Dmitry Osipenko Cc: thierry.reding@gmail.com, joro@8bytes.org, will@kernel.org, vdumpa@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Message-ID: <20210914184933.GA32705@Asurada-Nvidia> References: <20210914013858.31192-1-nicoleotsuka@gmail.com> <20210914013858.31192-7-nicoleotsuka@gmail.com> <31501a62-3312-9f04-3bb8-790d0481746c@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <31501a62-3312-9f04-3bb8-790d0481746c@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org On Tue, Sep 14, 2021 at 04:29:15PM +0300, Dmitry Osipenko wrote: > 14.09.2021 04:38, Nicolin Chen пишет: > > +static unsigned long pd_pt_index_iova(unsigned int pd_index, unsigned int pt_index) > > +{ > > + return ((dma_addr_t)pd_index & (SMMU_NUM_PDE - 1)) << SMMU_PDE_SHIFT | > > + ((dma_addr_t)pt_index & (SMMU_NUM_PTE - 1)) << SMMU_PTE_SHIFT; > > +} > > We know that IOVA is fixed to u32 for this controller. Can we avoid all > these dma_addr_t castings? It should make code cleaner a tad, IMO. Tegra210 actually supports 34-bit IOVA...