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Mon, 4 Oct 2021 09:43:56 -0500 From: Wayne Lin To: CC: , , , , , , , , , Jimmy Kizito , Jun Lei , Wayne Lin Subject: [PATCH 13/23] drm/amd/display: Implement end of training for hop in DPIA display path Date: Mon, 4 Oct 2021 22:40:40 +0800 Message-ID: <20211004144050.3425351-14-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211004144050.3425351-1-Wayne.Lin@amd.com> References: <20211004144050.3425351-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9866f2c6-ce5b-4d69-3026-08d987456d84 X-MS-TrafficTypeDiagnostic: DM6PR12MB3643: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:110; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Y6eLU4NoEBiPoE0aPZjQEJhiSd2d5vNdsHZ0+lfiYduv78UzUHL8opaBf39hSkeSVYwHHHPpG+j3icccCrhuw8e+7EUEm0bgfWoRoT3WiNtG7IpBlaCDRTB57QydbRTONZizmo4YJIyBSuxClt1XaxDEv5ygO/GR12WsZ5AvFD5Vjw1Sg3E1MipP5SkYiKvpQtDjn2iqwSBuiWSkA82j7nBTOWsEbogt+apxEtGr1wGWFQorqbp7eZavxPhfePqlLYRv4PmiO1ekYYUY6YW+9WUftN+W7Shyk+eNuLzGVTEihGwu05VHOQwH1YyGRQpYrkSBsLxaEtmSQGveTkCqvQ7p8g+HWf/crdnmm2X6IQOQsfg586WLI4lqFsHpDqVgxcPFyzLO1hpkZmGAqGDJUQXMmweqdolOkMYpk5pPy8tTc/Pom71Wqe4GPcUxanMfmJ9BVoOPa3/cHNCLFKRIxx7gcUmVikgDHpGFKyB+QG10CB8wk81as7aCoewebu14BzrJB3WlY0930k8Tx4h7pi2G3fU03fVbr1Cj7g/2KDNuzWpJve9sOANLyaDwQGojZ7IkJh0RIKJwV+ZmfgIIs70Fe7nreQ8BS4j0EvME7JXPB50XBl/ATfhWAi1F3LEtZN1drABGOpp+9h3Yx9qPkVgMMKgIdZQuA5QQEl5+Di9osdR9/77XRaUa/7nIZY7wFePvcqvoAohNLnqIxDJk8311vF8Tvu9aUZHA3j96yYM= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36860700001)(83380400001)(26005)(82310400003)(336012)(47076005)(86362001)(8676002)(5660300002)(426003)(4326008)(186003)(2616005)(8936002)(81166007)(70586007)(70206006)(508600001)(7696005)(356005)(316002)(6916009)(1076003)(6666004)(2906002)(54906003)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2021 14:44:10.8056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9866f2c6-ce5b-4d69-3026-08d987456d84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3643 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jimmy Kizito [Why & How] Clear training pattern sequence for hop in display path once clock recovery and equalization phases of DP tunnel link training completed. Reviewed-by: Jun Lei Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Signed-off-by: Jimmy Kizito --- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 10 ++- .../drm/amd/display/dc/core/dc_link_dpia.c | 77 ++++++++++++++++++- 2 files changed, 82 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 7f6fd0a3bf18..bfba1d2c6a18 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2391,14 +2391,20 @@ bool perform_link_training_with_retries( dc_link_dp_perform_link_training_skip_aux(link, ¤t_setting); return true; } else { - if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) + /** @todo Consolidate USB4 DP and DPx.x training. */ + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { status = dc_link_dpia_perform_link_training(link, ¤t_setting, skip_video_pattern); - else + + /* Transmit idle pattern once training successful. */ + if (status == LINK_TRAINING_SUCCESS) + dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0); + } else { status = dc_link_dp_perform_link_training(link, ¤t_setting, skip_video_pattern); + } if (status == LINK_TRAINING_SUCCESS) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c index fa7539916c77..4b1ad057bd1f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c @@ -730,13 +730,84 @@ static enum link_training_result dpia_training_eq_phase(struct dc_link *link, } /* End training of specified hop in display path. */ +static enum dc_status dpcd_clear_lt_pattern(struct dc_link *link, uint32_t hop) +{ + union dpcd_training_pattern dpcd_pattern = { {0} }; + uint32_t dpcd_tps_offset = DP_TRAINING_PATTERN_SET; + enum dc_status status; + + if (hop != DPRX) + dpcd_tps_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 + + ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (hop - 1)); + + status = core_link_write_dpcd(link, + DP_TRAINING_PATTERN_SET, + &dpcd_pattern.raw, + sizeof(dpcd_pattern.raw)); + + return status; +} + +/* End training of specified hop in display path. + * + * In transparent LTTPR mode: + * - driver clears training pattern for the specified hop in DPCD. + * In non-transparent LTTPR mode: + * - in addition to clearing training pattern, driver issues USB4 tunneling + * (SET_CONFIG) messages to notify DPOA when training is done for first hop + * (DPTX-to-DPIA) and last hop (DPRX). + * + * @param link DPIA link being trained. + * @param hop Hop in display path. DPRX = 0. + */ static enum link_training_result dpia_training_end(struct dc_link *link, uint32_t hop) { - enum link_training_result result; + enum link_training_result result = LINK_TRAINING_SUCCESS; + uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */ + enum dc_status status; - /** @todo Fail until implemented. */ - result = LINK_TRAINING_ABORT; + if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) { + repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + + if (hop == repeater_cnt) { /* DPTX-to-DPIA */ + /* Send SET_CONFIG(SET_TRAINING:0xff) to notify DPOA that + * DPTX-to-DPIA hop trained. No DPCD write needed for first hop. + */ + status = core_link_send_set_config(link, + DPIA_SET_CFG_SET_TRAINING, + DPIA_TS_UFP_DONE); + if (status != DC_OK) + result = LINK_TRAINING_ABORT; + } else { /* DPOA-to-x */ + /* Write 0x0 to TRAINING_PATTERN_SET */ + status = dpcd_clear_lt_pattern(link, hop); + if (status != DC_OK) + result = LINK_TRAINING_ABORT; + } + + /* Notify DPOA that non-transparent link training of DPRX done. */ + if (hop == DPRX && result != LINK_TRAINING_ABORT) { + status = core_link_send_set_config(link, + DPIA_SET_CFG_SET_TRAINING, + DPIA_TS_DPRX_DONE); + if (status != DC_OK) + result = LINK_TRAINING_ABORT; + } + + } else { /* non-LTTPR or transparent LTTPR. */ + /* Write 0x0 to TRAINING_PATTERN_SET */ + status = dpcd_clear_lt_pattern(link, hop); + if (status != DC_OK) + result = LINK_TRAINING_ABORT; + } + + DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) end\n - hop(%d)\n - result(%d)\n - LTTPR mode(%d)\n", + __func__, + link->link_id.enum_id - ENUM_ID_1, + hop, + result, + link->lttpr_mode); return result; } -- 2.25.1