From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org, pali@kernel.org,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v2 01/13] PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros
Date: Tue, 5 Oct 2021 20:09:40 +0200 [thread overview]
Message-ID: <20211005180952.6812-2-kabel@kernel.org> (raw)
In-Reply-To: <20211005180952.6812-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
Define a macro PCI_EXP_DEVCTL_PAYLOAD_* for every possible Max Payload
Size in linux/pci_regs.h, in the same style as PCI_EXP_DEVCTL_READRQ_*.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
include/uapi/linux/pci_regs.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e709ae8235e7..ff6ccbc6efe9 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -504,6 +504,12 @@
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
+#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
+#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
--
2.32.0
next prev parent reply other threads:[~2021-10-05 18:09 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-05 18:09 [PATCH v2 00/13] PCI: aardvark controller fixes Marek Behún
2021-10-05 18:09 ` Marek Behún [this message]
2021-10-05 18:09 ` [PATCH v2 02/13] PCI: aardvark: Fix PCIe Max Payload Size setting Marek Behún
2021-10-05 18:09 ` [PATCH v2 03/13] PCI: aardvark: Don't spam about PIO Response Status Marek Behún
2021-10-05 18:09 ` [PATCH v2 04/13] PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge Marek Behún
2021-10-05 18:09 ` [PATCH v2 05/13] PCI: aardvark: Fix configuring Reference clock Marek Behún
2021-10-05 18:09 ` [PATCH v2 06/13] PCI: aardvark: Do not clear status bits of masked interrupts Marek Behún
2021-10-05 18:09 ` [PATCH v2 07/13] PCI: aardvark: Do not unmask unused interrupts Marek Behún
2021-10-06 9:13 ` Lorenzo Pieralisi
2021-10-06 10:28 ` Marek Behún
2021-10-07 13:27 ` Lorenzo Pieralisi
2021-10-05 18:09 ` [PATCH v2 08/13] PCI: aardvark: Deduplicate code in advk_pcie_rd_conf() Marek Behún
2021-10-05 18:09 ` [PATCH v2 09/13] PCI: aardvark: Implement re-issuing config requests on CRS response Marek Behún
2021-10-05 18:09 ` [PATCH v2 10/13] PCI: aardvark: Simplify initialization of rootcap on virtual bridge Marek Behún
2021-10-05 18:09 ` [PATCH v2 11/13] PCI: aardvark: Fix link training Marek Behún
2021-10-07 11:55 ` Lorenzo Pieralisi
2021-10-07 12:33 ` Marek Behún
2021-10-05 18:09 ` [PATCH v2 12/13] PCI: aardvark: Fix checking for link up via LTSSM state Marek Behún
2021-10-05 18:09 ` [PATCH v2 13/13] PCI: aardvark: Fix reporting Data Link Layer Link Active Marek Behún
2021-10-07 13:38 ` [PATCH v2 00/13] PCI: aardvark controller fixes Lorenzo Pieralisi
2021-10-07 17:36 ` Marek Behún
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