From: "Michael S. Tsirkin" <mst@redhat.com>
To: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: gaosong@loongson.cn, peter.maydell@linaro.org, thuth@redhat.com,
chenhuacai@loongson.cn, philmd@redhat.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
peterx@redhat.com, laurent@vivier.eu, alistair.francis@wdc.com,
maobibo@loongson.cn, david@gibson.dropbear.id.au,
pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk,
bmeng.cn@gmail.com, alex.bennee@linaro.org, f4bug@amsat.org
Subject: Re: [PATCH 23/31] hw/loongarch: Add default bios startup support.
Date: Tue, 19 Oct 2021 12:19:38 -0400 [thread overview]
Message-ID: <20211019121700-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <1634628917-10031-24-git-send-email-yangxiaojuan@loongson.cn>
On Tue, Oct 19, 2021 at 03:35:09PM +0800, Xiaojuan Yang wrote:
> This patch add default bios startup.
> The bios source code will be opened int the near future.
That pretty much rules out including this patchset for now ...
Does not mean people won't review, but please tag the subject RFC
until it's all open source and can be merged.
And I would really appreciate not getting CC'd until it is.
Thanks!
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
> hw/loongarch/Kconfig | 4 +++
> hw/loongarch/fw_cfg.c | 34 ++++++++++++++++++
> hw/loongarch/fw_cfg.h | 16 +++++++++
> hw/loongarch/ls3a5000_virt.c | 60 ++++++++++++++++++++++++-------
> hw/loongarch/meson.build | 1 +
> include/hw/loongarch/loongarch.h | 5 +++
> pc-bios/loongarch_bios.bin | Bin 0 -> 4128768 bytes
> 7 files changed, 108 insertions(+), 12 deletions(-)
> create mode 100644 hw/loongarch/fw_cfg.c
> create mode 100644 hw/loongarch/fw_cfg.h
> create mode 100644 pc-bios/loongarch_bios.bin
>
> diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
> index fe100b01eb..b59cd98a7a 100644
> --- a/hw/loongarch/Kconfig
> +++ b/hw/loongarch/Kconfig
> @@ -13,3 +13,7 @@ config LOONGSON_3A5000
> select LOONGARCH_PCH_MSI
> select LOONGARCH_EXTIOI
> select LS7A_RTC
> + select FW_CFG_LOONGARCH
> +
> +config FW_CFG_LOONGARCH
> + bool
> diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c
> new file mode 100644
> index 0000000000..42229c5c91
> --- /dev/null
> +++ b/hw/loongarch/fw_cfg.c
> @@ -0,0 +1,34 @@
> +/*
> + * QEMU fw_cfg helpers (LOONGARCH specific)
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/loongarch/fw_cfg.h"
> +#include "hw/loongarch/loongarch.h"
> +#include "hw/nvram/fw_cfg.h"
> +#include "sysemu/sysemu.h"
> +
> +static void fw_cfg_boot_set(void *opaque, const char *boot_device,
> + Error **errp)
> +{
> + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
> +}
> +
> +FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms)
> +{
> + FWCfgState *fw_cfg;
> + int max_cpus = ms->smp.max_cpus;
> + int smp_cpus = ms->smp.cpus;
> +
> + fw_cfg = fw_cfg_init_mem_wide(FW_CFG_ADDR, FW_CFG_ADDR + 8, 8, 0, NULL);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
> + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
> +
> + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
> + return fw_cfg;
> +}
> diff --git a/hw/loongarch/fw_cfg.h b/hw/loongarch/fw_cfg.h
> new file mode 100644
> index 0000000000..d51dfb241a
> --- /dev/null
> +++ b/hw/loongarch/fw_cfg.h
> @@ -0,0 +1,16 @@
> +/*
> + * QEMU fw_cfg helpers (Loongarch specific)
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + *
> + * SPDX-License-Identifier: MIT
> + */
> +
> +#ifndef HW_LOONGARCH_FW_CFG_H
> +#define HW_LOONGARCH_FW_CFG_H
> +
> +#include "hw/boards.h"
> +#include "hw/nvram/fw_cfg.h"
> +
> +FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms);
> +#endif
> diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c
> index 79e6605cd8..e8057f7772 100644
> --- a/hw/loongarch/ls3a5000_virt.c
> +++ b/hw/loongarch/ls3a5000_virt.c
> @@ -14,6 +14,8 @@
> #include "hw/char/serial.h"
> #include "sysemu/sysemu.h"
> #include "sysemu/qtest.h"
> +#include "hw/loader.h"
> +#include "elf.h"
> #include "hw/irq.h"
> #include "net/net.h"
> #include "sysemu/runstate.h"
> @@ -24,6 +26,9 @@
> #include "hw/intc/loongarch_pch_msi.h"
> #include "hw/pci-host/ls7a.h"
> #include "hw/misc/unimp.h"
> +#include "hw/loongarch/fw_cfg.h"
> +
> +#define LOONGSON3_BIOSNAME "loongarch_bios.bin"
>
> CPULoongArchState *cpu_states[LOONGARCH_MAX_VCPUS];
>
> @@ -181,8 +186,9 @@ static void ls3a5000_virt_init(MachineState *machine)
> const char *cpu_model = machine->cpu_type;
> LoongArchCPU *cpu;
> CPULoongArchState *env;
> - uint64_t lowram_size = 0, highram_size = 0;
> + uint64_t highram_size = 0;
> MemoryRegion *lowmem = g_new(MemoryRegion, 1);
> + MemoryRegion *highmem = g_new(MemoryRegion, 1);
> char *ramName = NULL;
> ram_addr_t ram_size = machine->ram_size;
> MemoryRegion *address_space_mem = get_system_memory();
> @@ -190,6 +196,10 @@ static void ls3a5000_virt_init(MachineState *machine)
> int i;
> MemoryRegion *iomem = NULL;
> PCIBus *pci_bus = NULL;
> + int bios_size;
> + char *filename;
> + MemoryRegion *bios = g_new(MemoryRegion, 1);
> + ram_addr_t offset = 0;
>
> if (!cpu_model) {
> cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
> @@ -227,21 +237,46 @@ static void ls3a5000_virt_init(MachineState *machine)
> qemu_register_reset(main_cpu_reset, cpu);
> }
>
> + if (ram_size < 1 * GiB) {
> + error_report("ram_size must be greater than 1G due to the bios memory layout");
> + exit(1);
> + }
> +
> ramName = g_strdup_printf("loongarch.lowram");
> - lowram_size = MIN(ram_size, 256 * 0x100000);
> memory_region_init_alias(lowmem, NULL, ramName, machine->ram,
> - 0, lowram_size);
> - memory_region_add_subregion(address_space_mem, 0, lowmem);
> -
> - highram_size = ram_size > lowram_size ? ram_size - 256 * 0x100000 : 0;
> - if (highram_size > 0) {
> - MemoryRegion *highmem = g_new(MemoryRegion, 1);
> - ramName = g_strdup_printf("loongarch.highram");
> - memory_region_init_alias(highmem, NULL, ramName, machine->ram,
> - lowram_size, highram_size);
> - memory_region_add_subregion(address_space_mem, 0x90000000, highmem);
> + 0, 256 * MiB);
> + memory_region_add_subregion(address_space_mem, offset, lowmem);
> + offset += 256 * MiB;
> +
> + highram_size = ram_size - 256 * MiB;
> + ramName = g_strdup_printf("loongarch.highram");
> + memory_region_init_alias(highmem, NULL, ramName, machine->ram,
> + offset, highram_size);
> + memory_region_add_subregion(address_space_mem, 0x90000000, highmem);
> + offset += highram_size;
> +
> + /* load the BIOS image. */
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
> + machine->firmware ?: LOONGSON3_BIOSNAME);
> + if (filename) {
> + bios_size = load_image_targphys(filename, LA_BIOS_BASE, LA_BIOS_SIZE);
> + lsms->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
> + rom_set_fw(lsms->fw_cfg);
> + g_free(filename);
> + } else {
> + bios_size = -1;
> }
>
> + if ((bios_size < 0 || bios_size > LA_BIOS_SIZE) && !qtest_enabled()) {
> + error_report("Could not load LOONGARCH bios '%s'", machine->firmware);
> + exit(1);
> + }
> +
> + memory_region_init_ram(bios, NULL, "loongarch.bios",
> + LA_BIOS_SIZE, &error_fatal);
> + memory_region_set_readonly(bios, true);
> + memory_region_add_subregion(get_system_memory(), LA_BIOS_BASE, bios);
> +
> /*Add PM mmio memory for reboot and shutdown*/
> iomem = g_new(MemoryRegion, 1);
> memory_region_init_io(iomem, NULL, &loongarch_pm_ops, NULL,
> @@ -293,6 +328,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
> mc->default_ram_id = "loongarch.ram";
> mc->max_cpus = LOONGARCH_MAX_VCPUS;
> mc->is_default = 1;
> + mc->default_machine_opts = "firmware=loongarch_bios.bin";
> mc->default_kernel_irqchip_split = false;
> mc->block_default_type = IF_VIRTIO;
> mc->default_boot_order = "c";
> diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
> index 1bd209c9eb..3fabfa72dc 100644
> --- a/hw/loongarch/meson.build
> +++ b/hw/loongarch/meson.build
> @@ -1,5 +1,6 @@
> loongarch_ss = ss.source_set()
> loongarch_ss.add(files('loongarch_int.c'))
> loongarch_ss.add(when: 'CONFIG_LOONGSON_3A5000', if_true: files('ls3a5000_virt.c', 'ipi.c'))
> +loongarch_ss.add(when: 'CONFIG_FW_CFG_LOONGARCH', if_true: files('fw_cfg.c'))
>
> hw_arch += {'loongarch': loongarch_ss}
> diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
> index 210173471d..1316707f49 100644
> --- a/include/hw/loongarch/loongarch.h
> +++ b/include/hw/loongarch/loongarch.h
> @@ -35,6 +35,10 @@
> #define CPUNAME_REG 0x1fe00020
> #define MISC_FUNC_REG 0x1fe00420
> #define FREQ_REG 0x1fe001d0
> +#define FW_CFG_ADDR 0x1e020000
> +
> +#define LA_BIOS_BASE 0x1c000000
> +#define LA_BIOS_SIZE (4 * 1024 * 1024)
>
> typedef struct LoongarchMachineState {
> /*< private >*/
> @@ -42,6 +46,7 @@ typedef struct LoongarchMachineState {
>
> gipiState *gipi;
> qemu_irq *pch_irq;
> + FWCfgState *fw_cfg;
> } LoongarchMachineState;
>
> #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("loongson7a")
> new file mode 100644
> index 0000000000000000000000000000000000000000..ac6a691b00ac4fec9a5f4c32aad3865ac24efbb2
> GIT binary patch
> literal 4128768
> zcmeFaeSB5bmH)qTZUU$YBpL)1^`ZgKNkOsI7FumjAQU@;6`PrcY8-A%fLMccI<`Eh
> z^#F-&r#C#PE#MOuB~;r4@mXsfP6C3Rl7QoPs`iPig0{bg2ggo>59EA5YoFYk+-ssv
>
snipped a ton of binary
> literal 0
> HcmV?d00001
>
> --
> 2.27.0
next prev parent reply other threads:[~2021-10-19 17:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 7:34 [PATCH 00/31] Add Loongarch softmmu support Xiaojuan Yang
2021-10-19 7:34 ` [PATCH 02/31] target/loongarch: Add CSR registers definition Xiaojuan Yang
2021-10-19 19:10 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 03/31] target/loongarch: Set default csr values Xiaojuan Yang
2021-10-19 19:18 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 04/31] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2021-10-19 19:35 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 05/31] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-10-19 20:25 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 08/31] target/loongarch: Add tlb instruction support Xiaojuan Yang
2021-10-20 4:19 ` Richard Henderson
2021-10-29 7:01 ` yangxiaojuan
2021-10-29 17:48 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 09/31] target/loongarch: Add other core instructions support Xiaojuan Yang
2021-10-20 4:45 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 10/31] target/loongarch: Add loongarch interrupt and exception handle Xiaojuan Yang
2021-10-20 4:59 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 11/31] target/loongarch: Add stabletimer support Xiaojuan Yang
2021-10-19 7:34 ` [PATCH 12/31] target/loongarch: Add timer related instructions support Xiaojuan Yang
2021-10-20 5:17 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 13/31] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson Platform Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 14/31] hw/loongarch: Add a virt loongarch 3A5000 board support Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 15/31] hw/loongarch: Add loongarch cpu interrupt support(CPUINTC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 16/31] hw/loongarch: Add loongarch ipi interrupt support(IPI) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 17/31] hw/intc: Add loongarch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 18/31] hw/intc: Add loongarch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 19/31] hw/intc: Add loongarch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 20/31] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2021-10-19 14:52 ` [PATCH 00/31] Add Loongarch softmmu support WANG Xuerui
[not found] ` <7d933f8d.228e.17c9b556e98.Coremail.yangxiaojuan@loongson.cn>
2021-10-20 5:11 ` WANG Xuerui
[not found] ` <1634628917-10031-24-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 16:19 ` Michael S. Tsirkin [this message]
[not found] ` <1634628917-10031-2-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 18:56 ` [PATCH 01/31] target/loongarch: Upate the README for the softmmu Richard Henderson
2021-10-22 2:25 ` yangxiaojuan
[not found] ` <1634628917-10031-7-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 21:11 ` [PATCH 06/31] target/loongarch: Add mmu support for Loongarch CPU Richard Henderson
[not found] ` <1634628917-10031-8-git-send-email-yangxiaojuan@loongson.cn>
2021-10-20 1:36 ` [PATCH 07/31] target/loongarch: Add loongarch csr/iocsr instruction support Richard Henderson
2021-10-29 6:26 ` yangxiaojuan
2021-10-29 17:38 ` Richard Henderson
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