From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C14D9C433F5 for ; Sun, 24 Oct 2021 15:30:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 888F160F21 for ; Sun, 24 Oct 2021 15:30:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 888F160F21 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=se-silbe.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=m2q4StqRJF9vNlITPv3EZXr/Z+ylSkwJFHeXZ0Wt0f0=; b=gfKiKh1Flwc7C/ SV1VtkaZ2u55ND9EnNEYV93VwxDtQE7HZcof2QnFnnYE2I0N1POUvDhWPpZnsa2AXoM7YFkMV+z83 qeDOLdbuhdguwXCrY4ZzT+3i7l3X8o9+lzGFwie6SKgoCtKbY/bYz3NyDOnyizJ4NboMQPXeU2nN8 /PTieYkvKkgkw5wCLNHye8nl2GuxXRq3desgEgzDoylNj0wDbIlxXhJv2Ppe5QAP+q0M9cn4EFEDI /sngPrhKOgzz2PgvEh8djwl5mVuO84xCy8dDb2n6RNxpOx0ezLm4yIJrgqEuR79wqlUTTF1xKBfK/ F22X+YBtvPnzQI6jHuPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mefQa-00EATX-Dp; Sun, 24 Oct 2021 15:28:52 +0000 Received: from bbox.sascha.silbe.org ([46.38.230.149]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mefQW-00EASv-JG for linux-arm-kernel@lists.infradead.org; Sun, 24 Oct 2021 15:28:50 +0000 Received: from brick.sascha.silbe.org (brick.sascha.silbe.org [192.168.1.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "brick.sascha.silbe.org", Issuer "stunnel Pseudo-CA" (verified OK)) by bbox.sascha.silbe.org (Postfix) with ESMTPS id D111F60F18; Sun, 24 Oct 2021 17:28:41 +0200 (CEST) Received: (nullmailer pid 649825 invoked by uid 71000); Sun, 24 Oct 2021 15:28:41 -0000 From: Sascha Silbe To: Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mq: add defines for IOMUXC_SW_PAD_CTL register values Date: Sun, 24 Oct 2021 17:28:32 +0200 Message-Id: <20211024152832.649738-1-x-linux@se-silbe.de> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211024_082848_847774_8C3BE1B3 X-CRM114-Status: GOOD ( 13.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The IOMUXC_SW_PAD_CTL_* registers on i.MX8M Dual/QuadLite/Quad all have the same basic structure. Add defines for a common subset supported by most of the registers. They can be used in Device Tree source files instead of magic values, making the sources a lot more readable and easier to write as well. Signed-off-by: Sascha Silbe --- .../arm64/boot/dts/freescale/imx8mq-pinfunc.h | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) The board I'm using this for is an out-of-tree prototype. If there's interest I can convert the in-tree DTS files. I have don't have any of those boards but comparing the built DTBs before vs. after the change should be sufficient. diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h index 68e8fa1729741..384ceb5422761 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h @@ -7,6 +7,34 @@ #ifndef __DTS_IMX8MQ_PINFUNC_H #define __DTS_IMX8MQ_PINFUNC_H +/* Software Input On bit from IOMUXC_SW_MUX_CTL_PAD_* registers. Magic + * value defined in + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ +#define PAD_SION (1 << 30) +/* input high/low thresholds, 0 = LVCMOS, 1 = LVTTL */ +#define PAD_LVTTL (1 << 8) +/* Schmitt-Trigger, 0 = disabled, 1 = enabled */ +#define PAD_HYS (1 << 7) +/* Internal pull-up resistor, 0 = disabled, 1 = enabled */ +#define PAD_PUE (1 << 6) +/* Open Drain, 0 = push-pull, 1 = open drain */ +#define PAD_ODE (1 << 5) +/* Slew Rate, 50/100/150/200 MHz */ +#define PAD_SRE_50MHZ 0 +#define PAD_SRE_100MHZ (1 << 3) +#define PAD_SRE_150MHZ (2 << 3) +#define PAD_SRE_200MHZ (3 << 3) +/* Drive Strength; names are based on nominal impedance at 3.3V */ +#define PAD_DSE_HIZ 0 +#define PAD_DSE_255OHM 1 +#define PAD_DSE_105OHM 2 +#define PAD_DSE_75OHM 3 +#define PAD_DSE_85OHM 4 +#define PAD_DSE_65OHM 5 +#define PAD_DSE_45OHM 6 +#define PAD_DSE_40OHM 7 + /* * The pin function ID is a tuple of * base-commit: 9c0c4d24ac000e52d55348961d3a3ba42065e0cf prerequisite-patch-id: d2d09cbe2907cd6c1ece0fcc6b576faf1ef8dd37 prerequisite-patch-id: 42e69450ab3e60fd3705232ae05fa1c8acfb467b prerequisite-patch-id: 9360e270fb7fbccc22d2a66c41830746bdb80784 -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8037FC433EF for ; Sun, 24 Oct 2021 15:33:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B10760ED3 for ; Sun, 24 Oct 2021 15:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229564AbhJXPgN (ORCPT ); Sun, 24 Oct 2021 11:36:13 -0400 Received: from bbox.sascha.silbe.org ([46.38.230.149]:56277 "EHLO bbox.sascha.silbe.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229782AbhJXPgM (ORCPT ); Sun, 24 Oct 2021 11:36:12 -0400 X-Greylist: delayed 309 seconds by postgrey-1.27 at vger.kernel.org; Sun, 24 Oct 2021 11:36:12 EDT Received: from brick.sascha.silbe.org (brick.sascha.silbe.org [192.168.1.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "brick.sascha.silbe.org", Issuer "stunnel Pseudo-CA" (verified OK)) by bbox.sascha.silbe.org (Postfix) with ESMTPS id D111F60F18; Sun, 24 Oct 2021 17:28:41 +0200 (CEST) Received: (nullmailer pid 649825 invoked by uid 71000); Sun, 24 Oct 2021 15:28:41 -0000 From: Sascha Silbe To: Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mq: add defines for IOMUXC_SW_PAD_CTL register values Date: Sun, 24 Oct 2021 17:28:32 +0200 Message-Id: <20211024152832.649738-1-x-linux@se-silbe.de> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IOMUXC_SW_PAD_CTL_* registers on i.MX8M Dual/QuadLite/Quad all have the same basic structure. Add defines for a common subset supported by most of the registers. They can be used in Device Tree source files instead of magic values, making the sources a lot more readable and easier to write as well. Signed-off-by: Sascha Silbe --- .../arm64/boot/dts/freescale/imx8mq-pinfunc.h | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) The board I'm using this for is an out-of-tree prototype. If there's interest I can convert the in-tree DTS files. I have don't have any of those boards but comparing the built DTBs before vs. after the change should be sufficient. diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h index 68e8fa1729741..384ceb5422761 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h @@ -7,6 +7,34 @@ #ifndef __DTS_IMX8MQ_PINFUNC_H #define __DTS_IMX8MQ_PINFUNC_H +/* Software Input On bit from IOMUXC_SW_MUX_CTL_PAD_* registers. Magic + * value defined in + * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt + */ +#define PAD_SION (1 << 30) +/* input high/low thresholds, 0 = LVCMOS, 1 = LVTTL */ +#define PAD_LVTTL (1 << 8) +/* Schmitt-Trigger, 0 = disabled, 1 = enabled */ +#define PAD_HYS (1 << 7) +/* Internal pull-up resistor, 0 = disabled, 1 = enabled */ +#define PAD_PUE (1 << 6) +/* Open Drain, 0 = push-pull, 1 = open drain */ +#define PAD_ODE (1 << 5) +/* Slew Rate, 50/100/150/200 MHz */ +#define PAD_SRE_50MHZ 0 +#define PAD_SRE_100MHZ (1 << 3) +#define PAD_SRE_150MHZ (2 << 3) +#define PAD_SRE_200MHZ (3 << 3) +/* Drive Strength; names are based on nominal impedance at 3.3V */ +#define PAD_DSE_HIZ 0 +#define PAD_DSE_255OHM 1 +#define PAD_DSE_105OHM 2 +#define PAD_DSE_75OHM 3 +#define PAD_DSE_85OHM 4 +#define PAD_DSE_65OHM 5 +#define PAD_DSE_45OHM 6 +#define PAD_DSE_40OHM 7 + /* * The pin function ID is a tuple of * base-commit: 9c0c4d24ac000e52d55348961d3a3ba42065e0cf prerequisite-patch-id: d2d09cbe2907cd6c1ece0fcc6b576faf1ef8dd37 prerequisite-patch-id: 42e69450ab3e60fd3705232ae05fa1c8acfb467b prerequisite-patch-id: 9360e270fb7fbccc22d2a66c41830746bdb80784 -- 2.30.2