From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB3E1C433EF for ; Fri, 26 Nov 2021 10:13:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KF5Xt8aSYpElcHm6zwFtrCSvR8Xwxg8o+ggQBeKrDUA=; b=5DIoQXAxlRTnFX Wirh/tqynWPW1C+TOomPPmL6iIV70pzoEtpS9S+zQlcMhs740SCbQwT4psFhBUfYvW3XLvaVLYffM 0djpchHV7rEPPG/P3gGB2krOGuU8Gh6KnntIRx2oeAAGAKEJ6wKniyrl2uWaOl8qs0wx/tWg3vqPS 8bbrf9YO3eX1/KT3rkMMF3Q+mmPdxIOvdkj85ihzh45uFlydKa9PMTBaCRXXyCPI5koh1TthS7cln nKK/o9PupZ/ZJQN3LfWTc1hMGqacZaDDarBb5KcO5G2tGYubM1NUj4NlfdDREGZREFXNglbJvih25 Jo70A4VMwNWm/vzgiMfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqYCa-009u7x-Ka; Fri, 26 Nov 2021 10:11:32 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mqYBU-009thu-FZ for linux-arm-kernel@lists.infradead.org; Fri, 26 Nov 2021 10:10:26 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0575760F94; Fri, 26 Nov 2021 10:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637921424; bh=gr8Qq1PXzr+jBWyOuqOjU2pyuezsoREmhftV0sxS7Jc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EXgS7m4GmzGPTMTBs+wCU7RP9cIxDbNRmkeOQIumHkZ1ABMxnUgPL5w3FDTGbyVTn x8DmpKGBUd2NkieAfOsvDdW/+GyA2L2w1snTG++FnnUrbQP7+uYSNnHcN05uIGpy2c +QissKj6YCWDCZ9U8217EG8Fibi1gQKDx/HfliDbmnZg4kd75zuCKG7SFOX/jZNztZ CDmDcRF5fEKjCaGoQak7txYGAOGiUQUwJLVyifZ2KzT1WjZ7uVwR7qs/YVFW5IdE6f GMBe7tIEZKPNpGJ8E2cQEZrDYGW6N77KI5Rwlsq07/RqTzWBror/eHAMpzrhr+CiD1 pGBLheK0CKHxA== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Russell King , Nicolas Pitre , Arnd Bergmann , Kees Cook , Keith Packard , Linus Walleij , Nick Desaulniers , Tony Lindgren Subject: [RFC PATCH 3/6] ARM: percpu: add SMP_ON_UP support Date: Fri, 26 Nov 2021 11:10:03 +0100 Message-Id: <20211126101006.3410322-4-ardb@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211126101006.3410322-1-ardb@kernel.org> References: <20211126101006.3410322-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4454; h=from:subject; bh=gr8Qq1PXzr+jBWyOuqOjU2pyuezsoREmhftV0sxS7Jc=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBhoLJ6/P1+NX/REAuqy3veamujO2b7U2KGuop9RHwG y8AITxmJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCYaCyegAKCRDDTyI5ktmPJJX3C/ wOKsq3/OyIYJqVxiTgFKVdq+95g/Jcv1+w1Rjh1TTO6WsPHuPrZIR8AB4sQS2dIynllbEPxqEJB/bT pKdcOQoraRD42/TMeZxt2K3D2SYj+6XPg0WGCwvbDu23xZQLJNgCKt2dxVwA3JZHWPvwH1JKQLPGXc BUkcnt+gPxqul2YPFjxXdw42uUjXm1iKiO/i7lhMkjZR644trjT9JETRUvd7h0V0Ugz3nnzhUWfLf+ 2g9rwsDpC2DBwXzkRPhVeBR7Vh0KYjOMjfS9gb081o8WE+UfqhJ7Ytw+lEMQyaKvsT/f88Adc17uCL XCztAz+ME1M82eICVPZyqPGz5av6Ia7LAgREDTSaVVrg8i6Myrt0howeWOTRBGoLJPW166mIMW2UJr eEAmpmng6vrkgQo3gfVcz3HZzri0rrsCGX+wyOIcHqXlPY/vb0pA4UKMX1pPHAJ4/F+1Rra1SMEWwD UcX9BNPNdBhLa5PiUdwvXaQMviHowNiUA+LPC/BRYN9ZE= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211126_021024_613125_2270539F X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Permit the use of the TPIDRPRW system register for carrying the per-CPU offset in generic SMP configurations that also target non-SMP capable ARMv6 cores. This uses the SMP_ON_UP code patching framework to turn all TPIDRPRW accesses into reads/writes of entry #0 in the __per_cpu_offset array. While at it, switch over some existing direct TPIDRPRW accesses in asm code to invocations of a new helper that is patched in the same way when necessary. Note that CPU_V6+SMP without SMP_ON_UP results in a kernel that does not boot on v6 CPUs without SMP extensions, so add this dependency to Kconfig as well. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 21 ++++++++++++++ arch/arm/include/asm/percpu.h | 29 ++++++++++++++++++-- arch/arm/kernel/entry-armv.S | 4 +-- arch/arm/mm/Kconfig | 1 + 4 files changed, 50 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 1b9d4df331aa..c4c1d5b2edf5 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -312,6 +312,27 @@ THUMB( fpreg .req r7 ) #define ALT_UP_B(label) b label #endif + /* + * this_cpu_offset - load the per-CPU offset of this CPU into + * register 'rd' + */ + .macro this_cpu_offset, rd:req +#ifdef CONFIG_SMP +ALT_SMP(mrc p15, 0, \rd, c13, c0, 4) +#ifdef CONFIG_CPU_V6 +ALT_UP_B(.L1_\@) +.L0_\@: + .subsection 1 +.L1_\@: ldr \rd, =__per_cpu_offset + ldr \rd, [\rd] + b .L0_\@ + .previous +#endif +#else + mov \rd, #0 +#endif + .endm + /* * Instruction barrier */ diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h index e2fcb3cfd3de..7b984352e402 100644 --- a/arch/arm/include/asm/percpu.h +++ b/arch/arm/include/asm/percpu.h @@ -5,15 +5,25 @@ #ifndef _ASM_ARM_PERCPU_H_ #define _ASM_ARM_PERCPU_H_ +#include + register unsigned long current_stack_pointer asm ("sp"); /* * Same as asm-generic/percpu.h, except that we store the per cpu offset * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7 */ -#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6) +#ifdef CONFIG_SMP +extern unsigned long __per_cpu_offset[NR_CPUS]; +extern unsigned int smp_on_up; + static inline void set_my_cpu_offset(unsigned long off) { + if (IS_ENABLED(CONFIG_CPU_V6) && !smp_on_up) { + __per_cpu_offset[0] = off; + return; + } + /* Set TPIDRPRW */ asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); } @@ -27,8 +37,21 @@ static inline unsigned long __my_cpu_offset(void) * We want to allow caching the value, so avoid using volatile and * instead use a fake stack read to hazard against barrier(). */ - asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) - : "Q" (*(const unsigned long *)current_stack_pointer)); + asm("0: mrc p15, 0, %0, c13, c0, 4 \n\t" +#ifdef CONFIG_CPU_V6 + "1: \n\t" + " .subsection 1 \n\t" + "2: ldr %0, =__per_cpu_offset \n\t" + " ldr %0, [%0] \n\t" + " b 1b \n\t" + " .previous \n\t" + " .pushsection \".alt.smp.init\", \"a\" \n\t" + " .long 0b - . \n\t" + " b . + (2b - 0b) \n\t" + " .popsection \n\t" +#endif + : "=r" (off) + : "Q" (*(const unsigned long *)current_stack_pointer)); return off; } diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 1e26d69ebbf1..09a9fe501094 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -41,7 +41,7 @@ mov r0, sp #ifdef CONFIG_IRQSTACKS mov_l r2, irq_stack_ptr @ Take base address - mrc p15, 0, r3, c13, c0, 4 @ Get CPU offset + this_cpu_offset r3 #ifdef CONFIG_UNWINDER_ARM mov fpreg, sp @ Preserve original SP #else @@ -884,7 +884,7 @@ __bad_stack: THUMB( bx pc ) THUMB( nop ) THUMB( .arm ) - mrc p15, 0, ip, c13, c0, 4 @ Get per-CPU offset + this_cpu_offset ip .globl overflow_stack_ptr .reloc 0f, R_ARM_ALU_PC_G0_NC, overflow_stack_ptr diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 58afba346729..a91ff22c6c2e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -386,6 +386,7 @@ config CPU_V6 select CPU_PABRT_V6 select CPU_THUMB_CAPABLE select CPU_TLB_V6 if MMU + select SMP_ON_UP if SMP # ARMv6k config CPU_V6K -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel