From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAA92C433FE for ; Mon, 29 Nov 2021 23:02:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236996AbhK2XGM (ORCPT ); Mon, 29 Nov 2021 18:06:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237254AbhK2XFd (ORCPT ); Mon, 29 Nov 2021 18:05:33 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F7F4C1E0FDC for ; Mon, 29 Nov 2021 10:42:25 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id iq11so13387968pjb.3 for ; Mon, 29 Nov 2021 10:42:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=2IMr/BG9SkG1AxTTzKV9LR6CsVGkTzK2wg6sT7xbgaY=; b=i2UiZHlCr5kh66jgKovJqtSDwEb2zvZxfexnbXArZfogOkqr1VdL0xr+QH8hHpZNAD UWogBpVDNH0qZW09LWftG0RTboPgKxWpk7zkbbZ7b1YUGosK3Z9GLtTJbRy+do4ubj4f vyMTAc6SKaESup1+uewCAFSHV7J16IKwMQuGs4VE+PDiuZHlI/BlNqP1fIhg6R+iMANv gWeo0sgX/88ZQumi4hWq0oK3GEo7GVjfE28oRP7FVPOErIa98EL9fbRdD5157O4/I68n pkxOgbTHTvOj5rVTNVL6p1/8Kga5MdvArqoOa8eg9bCLuV52PrVR++zre1fqOASEOZH3 dszg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=2IMr/BG9SkG1AxTTzKV9LR6CsVGkTzK2wg6sT7xbgaY=; b=uewwI3BHfopVOcQuTncUPucbP6QPYaKA+jTLrbRW84y0fwI4J9KCVR0vBeh64CRLSf Hg93pokfvJBJSWOU40k4WF1hD3Oiu40yHVcEJOYrJbS7SrjYWbRe7JURzKr/Ze11kLum tTtLFZ21xk1y0wdSqKKeuLPeE4rTN1UQpsCtWLd3B3rjHPXsW5wtM8nVpPjGI4c0I/jv YEmoAV9BwI+HuPVwGJGEhsiaZ1U9svOUrDA7JowXw4xbeQXru73YDwC8doK6VP7tEpZH bgfr9A6RNJ1oxVZXNtZcUrNfdkuDY4w0IFJXz8ClnkqOmC3FoV7aFgW67B4UgEs6BOSg FByA== X-Gm-Message-State: AOAM533LUshPdRnDSWE9kTzKVSTJXV+aSX1x0Bz7vec5wUS78xxpFqMX EpwSI7EtuJRKZnDbaoTyFsXikos62jYnmg== X-Google-Smtp-Source: ABdhPJwWwOxc8+HeQFmuo3O0W96Alxb/yDMazm3THHZSgFU8EAd83s4bQidn0D5Qk/sOGgIXOT8P7w== X-Received: by 2002:a17:902:7c02:b0:143:9d6a:8e42 with SMTP id x2-20020a1709027c0200b001439d6a8e42mr61675120pll.80.1638211344267; Mon, 29 Nov 2021 10:42:24 -0800 (PST) Received: from p14s (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id v10sm18800459pfu.123.2021.11.29.10.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:42:23 -0800 (PST) Date: Mon, 29 Nov 2021 11:42:19 -0700 From: Mathieu Poirier To: Tanmay Shah Cc: Bjorn Andersson , Rob Herring , Michal Simek , Laurent Pinchart , Ben Levinsky , Bill Mills , Sergei Korneichuk , linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 6/6] drivers: remoteproc: Add Xilinx r5 remoteproc driver Message-ID: <20211129184219.GC676889@p14s> References: <20211123062050.1442712-1-tanmay.shah@xilinx.com> <20211123062050.1442712-7-tanmay.shah@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211123062050.1442712-7-tanmay.shah@xilinx.com> Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org On Mon, Nov 22, 2021 at 10:20:50PM -0800, Tanmay Shah wrote: > This driver enables r5f dual core Real time Processing Unit subsystem > available on Xilinx Zynq Ultrascale MPSoC Platform. RPU subsystem > (cluster) can be configured in different modes e.g. split mode in which > two r5f cores work independent of each other and lock-step mode in which > both r5f cores execute same code clock-for-clock and notify if the > result is different. > > The Xilinx r5 Remoteproc Driver boots the RPU cores via calls to the Xilinx > Platform Management Unit that handles the R5 configuration, memory access > and R5 lifecycle management. The interface to this manager is done in this > driver via zynqmp_pm_* function calls. > > Signed-off-by: Ben Levinsky > Signed-off-by: Tanmay Shah > --- > drivers/remoteproc/Kconfig | 12 + > drivers/remoteproc/Makefile | 1 + > drivers/remoteproc/xlnx_r5_remoteproc.c | 959 ++++++++++++++++++++++++ > 3 files changed, 972 insertions(+) > create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c ...and this patch gives me complation warnings: CC drivers/remoteproc/xlnx_r5_remoteproc.o kernel-review/drivers/remoteproc/xlnx_r5_remoteproc.c: In function ‘add_tcm_carveout_lockstep_mode’: kernel-review/drivers/remoteproc/xlnx_r5_remoteproc.c:412:28: warning: unused variable ‘cluster’ [-Wunused-variable] 412 | struct zynqmp_r5_cluster *cluster; | ^~~~~~~ kernel-review/drivers/remoteproc/xlnx_r5_remoteproc.c:411:26: warning: unused variable ‘parent_pdev’ [-Wunused-variable] 411 | struct platform_device *parent_pdev; | ^~~~~~~~~~~ The above leads me to believe this patchset was not compiled before it was sent out. Being new to this I can understand that checkpatch.pl was omitted (albeit amply documented) but obvious compilation warnings can't be excused. As such I am dropping this set and will not review another version until January. Mathieu > > diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig > index f30d00a3aabe..27f66910d8d3 100644 > --- a/drivers/remoteproc/Kconfig > +++ b/drivers/remoteproc/Kconfig > @@ -315,6 +315,18 @@ config TI_K3_R5_REMOTEPROC > It's safe to say N here if you're not interested in utilizing > a slave processor. > > +config XLNX_R5_REMOTEPROC > + tristate "Xilinx R5 remoteproc support" > + depends on PM && ARCH_ZYNQMP > + depends on ZYNQMP_FIRMWARE > + select RPMSG_VIRTIO > + select ZYNQMP_IPI_MBOX > + help > + Say y or m here to support Xilinx R5 remote processors via the remote > + processor framework. > + > + It's safe to say N if not interested in using RPU r5f cores. > + > endif # REMOTEPROC > > endmenu > diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile > index bb26c9e4ef9c..334a8bed4c14 100644 > --- a/drivers/remoteproc/Makefile > +++ b/drivers/remoteproc/Makefile > @@ -35,3 +35,4 @@ obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o > obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o > obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o > obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o > +obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o > diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c > new file mode 100644 > index 000000000000..c2167fd3869d > --- /dev/null > +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c > @@ -0,0 +1,959 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * ZynqMP R5 Remote Processor driver > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "remoteproc_internal.h" > + > +/* settings for RPU cluster mode */ > +enum zynqmp_r5_cluster_mode { > + SPLIT_MODE = 0, // RPU cluster mode when cores run as separate processor > + LOCKSTEP_MODE = 1, // cores execute same code in lockstep,clk-for-clk > + SINGLE_CPU_MODE = 2, // core0 is held in reset and only core1 runs > +}; > + > +/** > + * struct mem_bank_data - Memory Bank description > + * > + * @addr: Start address of memory bank > + * @size: Size of Memory bank > + * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off > + * @bank_name: name of the bank for remoteproc framework > + */ > +struct mem_bank_data { > + phys_addr_t addr; > + size_t size; > + enum pm_node_id pm_domain_id; > + char *bank_name; > +}; > + > +static const struct mem_bank_data zynqmp_tcm_banks[] = { > + {0xffe00000UL, 0x10000UL, PD_R5_0_ATCM, "atcm0"}, /* TCM 64KB each */ > + {0xffe20000UL, 0x10000UL, PD_R5_0_BTCM, "btcm0"}, > + {0xffe90000UL, 0x10000UL, PD_R5_1_ATCM, "atcm1"}, > + {0xffeb0000UL, 0x10000UL, PD_R5_1_BTCM, "btcm1"}, > +}; > + > +/** > + * struct zynqmp_r5_core - ZynqMP R5 core structure > + * > + * @dev: device of RPU instance > + * @np: device node of RPU instance > + * @tcm_bank_count: number TCM banks accessible to this RPU > + * @tcm_banks: array of each TCM bank data > + * @res_mem_count: number of Reserved Memory regions per core > + * @res_mem: array of reserved memory regions > + * @rproc: rproc handle > + * @pm_domain_id: RPU CPU power domain id > + */ > +struct zynqmp_r5_core { > + struct device *dev; > + struct device_node *np; > + int tcm_bank_count; > + struct mem_bank_data *tcm_banks; > + int res_mem_count; > + struct reserved_mem *res_mem; > + struct rproc *rproc; > + enum pm_node_id pm_domain_id; > +}; > + > +/** > + * struct zynqmp_r5_cluster - ZynqMP R5 cluster structure > + * > + * @dev: r5f subsystem cluster device node > + * @mode: cluster mode of type zynqmp_r5_cluster_mode > + * @core_count: number of r5 cores used for this cluster mode > + * @r5_cores: Array of r5 cores of type struct zynqmp_r5_core > + */ > +struct zynqmp_r5_cluster { > + struct device *dev; > + enum zynqmp_r5_cluster_mode mode; > + int core_count; > + struct zynqmp_r5_core *r5_cores; > +}; > + > +/* > + * zynqmp_r5_set_mode - set RPU operation mode > + * > + * set RPU operation mode > + * > + * Return: 0 for success, negative value for failure > + */ > +static int zynqmp_r5_set_mode(struct zynqmp_r5_core *r5_core, > + enum zynqmp_r5_cluster_mode rpu_mode) > +{ > + enum rpu_tcm_comb tcm_mode; > + int ret, reg_val; > + > + reg_val = (rpu_mode == LOCKSTEP_MODE ? 0 : 1); > + > + ret = zynqmp_pm_set_rpu_mode(r5_core->pm_domain_id, reg_val); > + if (ret < 0) { > + pr_err("failed to set RPU mode\n"); > + return ret; > + } > + > + tcm_mode = (rpu_mode == LOCKSTEP_MODE) ? > + PM_RPU_TCM_COMB : PM_RPU_TCM_SPLIT; > + ret = zynqmp_pm_set_tcm_config(r5_core->pm_domain_id, tcm_mode); > + if (ret < 0) > + pr_err("failed to configure TCM\n"); > + > + return ret; > +} > + > +/* > + * zynqmp_r5_rproc_start > + * @rproc: single R5 core's corresponding rproc instance > + * > + * Start R5 Core from designated boot address. > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int zynqmp_r5_rproc_start(struct rproc *rproc) > +{ > + struct zynqmp_r5_core *r5_core = rproc->priv; > + enum rpu_boot_mem bootmem; > + int ret; > + > + if (!r5_core) { > + pr_err("can't get r5 core\n"); > + return -EINVAL; > + } > + > + bootmem = (rproc->bootaddr >= 0xFFFC0000) ? > + PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC; > + > + dev_dbg(r5_core->dev, "RPU boot addr 0x%llx from %s.", rproc->bootaddr, > + bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM"); > + > + ret = zynqmp_pm_request_wake(r5_core->pm_domain_id, 1, > + bootmem, ZYNQMP_PM_REQUEST_ACK_NO); > + if (ret) > + pr_err("failed to start RPU = %d\n", r5_core->pm_domain_id); > + return ret; > +} > + > +/* > + * zynqmp_r5_rproc_stop > + * @rproc: single R5 core's corresponding rproc instance > + * > + * Power down R5 Core. > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int zynqmp_r5_rproc_stop(struct rproc *rproc) > +{ > + struct zynqmp_r5_core *r5_core = rproc->priv; > + int ret; > + > + ret = zynqmp_pm_force_pwrdwn(r5_core->pm_domain_id, > + ZYNQMP_PM_REQUEST_ACK_BLOCKING); > + if (ret) > + pr_err("failed to stop remoteproc RPU %d\n", ret); > + > + return ret; > +} > + > +/* > + * zynqmp_r5_rproc_mem_map > + * @rproc: single R5 core's corresponding rproc instance > + * @mem: mem entry to map > + * > + * Callback to map va for memory-region's carveout. > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int zynqmp_r5_rproc_mem_map(struct rproc *rproc, > + struct rproc_mem_entry *mem) > +{ > + void __iomem *va; > + > + va = ioremap_wc(mem->dma, mem->len); > + if (IS_ERR_OR_NULL(va)) > + return -ENOMEM; > + > + mem->va = (void *)va; > + > + return 0; > +} > + > +/* > + * zynqmp_r5_rproc_mem_unmap > + * @rproc: single R5 core's corresponding rproc instance > + * @mem: mem entry to unmap > + * > + * Unmap memory-region carveout > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int zynqmp_r5_rproc_mem_unmap(struct rproc *rproc, > + struct rproc_mem_entry *mem) > +{ > + iounmap((void __iomem *)mem->va); > + return 0; > +} > + > +/* > + * add_mem_regions > + * @rproc: single R5 core's corresponding rproc instance > + * > + * Construct rproc mem carveouts from carveout provided in > + * memory-region property > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int add_mem_regions(struct rproc *rproc) > +{ > + struct device *dev; > + struct rproc_mem_entry *mem; > + struct reserved_mem *rmem; > + struct zynqmp_r5_core *r5_core; > + int i; > + > + r5_core = rproc->priv; > + dev = r5_core->dev; > + > + /* Register associated reserved memory regions */ > + for (i = 0; i < r5_core->res_mem_count; i++) { > + rmem = &r5_core->res_mem[i]; > + mem = rproc_mem_entry_init(dev, NULL, > + (dma_addr_t)rmem->base, > + rmem->size, rmem->base, > + zynqmp_r5_rproc_mem_map, > + zynqmp_r5_rproc_mem_unmap, > + rmem->name); > + if (IS_ERR_OR_NULL(mem)) > + return -ENOMEM; > + > + rproc_add_carveout(rproc, mem); > + } > + > + return 0; > +} > + > +/* > + * zynqmp_r5_rproc_mem_unmap > + * @rproc: single R5 core's corresponding rproc instance > + * @mem: mem entry to unmap > + * > + * Unmap TCM banks when powering down R5 core. > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int tcm_mem_unmap(struct rproc *rproc, struct rproc_mem_entry *mem) > +{ > + struct zynqmp_r5_core *r5_core; > + int i; > + enum pm_node_id pm_domain_id; > + > + r5_core = rproc->priv; > + if (!r5_core) { > + pr_err("r5 core is not available\n"); > + return -EINVAL; > + } > + > + iounmap((void __iomem *)mem->va); > + > + for (i = 0; i < r5_core->tcm_bank_count; i++) { > + pm_domain_id = r5_core->tcm_banks[i].pm_domain_id; > + if (zynqmp_pm_release_node(pm_domain_id)) > + pr_warn("can't turn off TCM bank %d", pm_domain_id); > + } > + > + return 0; > +} > + > +/* > + * tcm_mem_map > + * @rproc: single R5 core's corresponding rproc instance > + * @mem: mem entry to initialize the va and da fields of > + * > + * Given TCM bank entry, this callback will set device address for R5 > + * running on TCM and also setup virtual address for TCM bank > + * remoteproc carveout. > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int tcm_mem_map(struct rproc *rproc, > + struct rproc_mem_entry *mem) > +{ > + void __iomem *va; > + > + va = ioremap_wc(mem->dma, mem->len); > + if (IS_ERR_OR_NULL(va)) > + return -ENOMEM; > + > + /* Update memory entry va */ > + mem->va = (void *)va; > + > + /* clear TCMs */ > + memset_io(va, 0, mem->len); > + > + /* > + * The R5s expect their TCM banks to be at address 0x0 and 0x2000, > + * while on the Linux side they are at 0xffexxxxx. > + * > + * Zero out the high 12 bits of the address. This will give > + * expected values for TCM Banks 0A and 0B (0x0 and 0x20000). > + */ > + mem->da &= 0x000fffff; > + > + /* > + * TCM Banks 1A and 1B still have to be translated. > + * > + * Below handle these two banks' absolute addresses (0xffe90000 and > + * 0xffeb0000) and convert to the expected relative addresses > + * (0x0 and 0x20000). > + */ > + if (mem->da == 0x90000 || mem->da == 0xB0000) > + mem->da -= 0x90000; > + > + /* if translated TCM bank address is not valid report error */ > + if (mem->da != 0x0 && mem->da != 0x20000) { > + dev_err(&rproc->dev, "invalid TCM address: %x\n", mem->da); > + return -EINVAL; > + } > + return 0; > +} > + > +static int add_tcm_carveout_split_mode(struct rproc *rproc) > +{ > + int i, num_banks, ret; > + struct rproc_mem_entry *mem; > + enum pm_node_id pm_domain_id; > + u32 bank_addr; > + size_t bank_size = 0; > + char *bank_name; > + struct device *dev; > + struct zynqmp_r5_core *r5_core; > + > + r5_core = (struct zynqmp_r5_core *)rproc->priv; > + if (!r5_core) > + return -EINVAL; > + > + dev = r5_core->dev; > + > + /* go through zynqmp banks for r5 node */ > + num_banks = r5_core->tcm_bank_count; > + if (num_banks <= 0) { > + dev_err(dev, "need to specify TCM banks\n"); > + return -EINVAL; > + } > + > + for (i = 0; i < num_banks; i++) { > + bank_addr = (u32)r5_core->tcm_banks[i].addr; > + bank_name = r5_core->tcm_banks[i].bank_name; > + bank_size = r5_core->tcm_banks[i].size; > + pm_domain_id = r5_core->tcm_banks[i].pm_domain_id; > + > + ret = zynqmp_pm_request_node(pm_domain_id, > + ZYNQMP_PM_CAPABILITY_ACCESS, 0, > + ZYNQMP_PM_REQUEST_ACK_BLOCKING); > + if (ret < 0) { > + dev_err(dev, "failed to turn on TCM %d", pm_domain_id); > + return ret; > + } > + > + dev_dbg(dev, "TCM carveout split mode %s addr=%x, size=0x%lx", > + bank_name, bank_addr, bank_size); > + > + /* add carveout */ > + mem = rproc_mem_entry_init(dev, NULL, bank_addr, > + bank_size, bank_addr, > + tcm_mem_map, tcm_mem_unmap, > + bank_name); > + if (IS_ERR_OR_NULL(mem)) { > + /* Turn off all TCM banks turned on before */ > + do { > + pm_domain_id = r5_core->tcm_banks[i].pm_domain_id; > + ret = zynqmp_pm_release_node((u32)pm_domain_id); > + if (ret) > + dev_warn(dev, > + "fail to release node: %x, %x\n", > + (u32)pm_domain_id, ret); > + } while (i--); > + return -ENOMEM; > + } > + > + rproc_add_carveout(rproc, mem); > + } > + > + return 0; > +} > + > +static int add_tcm_carveout_lockstep_mode(struct rproc *rproc) > +{ > + int i, num_banks, ret; > + struct rproc_mem_entry *mem; > + enum pm_node_id pm_domain_id; > + u32 bank_addr; > + size_t bank_size = 0; > + char *bank_name; > + struct device *dev; > + struct platform_device *parent_pdev; > + struct zynqmp_r5_cluster *cluster; > + struct zynqmp_r5_core *r5_core; > + > + r5_core = (struct zynqmp_r5_core *)rproc->priv; > + if (!r5_core) > + return -EINVAL; > + > + dev = r5_core->dev; > + if (!dev) { > + pr_err("r5 core device unavailable\n"); > + return -ENODEV; > + } > + > + /* go through zynqmp banks for r5 node */ > + num_banks = r5_core->tcm_bank_count; > + if (num_banks <= 0) { > + dev_err(dev, "need to specify TCM banks\n"); > + return -EINVAL; > + } > + > + bank_addr = (u32)r5_core->tcm_banks[0].addr; > + bank_name = r5_core->tcm_banks[0].bank_name; > + for (i = 0; i < num_banks; i++) { > + bank_size += r5_core->tcm_banks[i].size; > + pm_domain_id = r5_core->tcm_banks[i].pm_domain_id; > + > + ret = zynqmp_pm_request_node(pm_domain_id, > + ZYNQMP_PM_CAPABILITY_ACCESS, 0, > + ZYNQMP_PM_REQUEST_ACK_BLOCKING); > + if (ret < 0) { > + dev_err(dev, "failed to turn on TCM %d", pm_domain_id); > + return ret; > + } > + } > + > + dev_dbg(dev, "TCM add carveout lockstep mode %s addr=0x%x, size=0x%lx", > + bank_name, bank_addr, bank_size); > + > + /* add carveout */ > + mem = rproc_mem_entry_init(dev, NULL, bank_addr, > + bank_size, bank_addr, > + tcm_mem_map, tcm_mem_unmap, > + bank_name); > + if (IS_ERR_OR_NULL(mem)) { > + for (i = 0; i < num_banks; i++) { > + pm_domain_id = r5_core->tcm_banks[i].pm_domain_id; > + ret = zynqmp_pm_release_node((u32)pm_domain_id); > + if (ret) > + dev_warn(dev, > + "fail to release node: %x ret: %x\n", > + (u32)pm_domain_id, ret); > + } > + return -ENOMEM; > + } > + > + rproc_add_carveout(rproc, mem); > + > + return 0; > +} > + > +/* > + * add_tcm_banks() > + * @rproc: single R5 core's corresponding rproc instance > + * > + * Given R5 node in remoteproc instance > + * allocate remoteproc carveout for TCM memory > + * needed for firmware to be loaded > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int add_tcm_banks(struct rproc *rproc) > +{ > + struct device *dev; > + struct platform_device *parent_pdev; > + struct zynqmp_r5_cluster *cluster; > + struct zynqmp_r5_core *r5_core; > + > + r5_core = (struct zynqmp_r5_core *)rproc->priv; > + if (!r5_core) > + return -EINVAL; > + > + dev = r5_core->dev; > + if (!dev) { > + pr_err("r5 core device unavailable\n"); > + return -ENODEV; > + } > + > + parent_pdev = to_platform_device(dev->parent); > + if (!parent_pdev) { > + dev_err(dev, "parent platform dev unavailable\n"); > + return -ENODEV; > + } > + > + cluster = platform_get_drvdata(parent_pdev); > + if (!cluster) { > + dev_err(&parent_pdev->dev, "Invalid driver data\n"); > + return -EINVAL; > + } > + > + if (cluster->mode == SPLIT_MODE) > + return add_tcm_carveout_split_mode(rproc); > + else if (cluster->mode == LOCKSTEP_MODE) > + return add_tcm_carveout_lockstep_mode(rproc); > + > + dev_err(cluster->dev, "invalid cluster mode\n"); > + return -EINVAL; > +} > + > +/* > + * zynqmp_r5_parse_fw() > + * @rproc: single R5 core's corresponding rproc instance > + * @fw: ptr to firmware to be loaded onto r5 core > + * > + * When loading firmware, ensure the necessary carveouts are in remoteproc > + * > + * return 0 on success, otherwise non-zero value on failure > + */ > +static int zynqmp_r5_parse_fw(struct rproc *rproc, const struct firmware *fw) > +{ > + int ret; > + struct zynqmp_r5_core *r5_core; > + struct device *dev; > + > + r5_core = rproc->priv; > + if (!r5_core) { > + dev_err(&rproc->dev, "r5 core not available\n"); > + return -EINVAL; > + } > + > + dev = r5_core->dev; > + > + ret = add_tcm_banks(rproc); > + if (ret) { > + dev_err(dev, "failed to get TCM banks, err %d\n", ret); > + return ret; > + } > + > + ret = add_mem_regions(rproc); > + if (ret) > + dev_warn(dev, "failed to get reserve mem regions %d\n", ret); > + > + ret = rproc_elf_load_rsc_table(rproc, fw); > + if (ret == -EINVAL) { > + /* > + * resource table only required for IPC. > + * if not present, this is not necessarily an error; > + * for example, loading r5 hello world application > + * so simply inform user and keep going. > + */ > + dev_info(&rproc->dev, "no resource table found.\n"); > + ret = 0; > + } > + return ret; > +} > + > +static struct rproc_ops zynqmp_r5_rproc_ops = { > + .start = zynqmp_r5_rproc_start, > + .stop = zynqmp_r5_rproc_stop, > + .load = rproc_elf_load_segments, > + .parse_fw = zynqmp_r5_parse_fw, > + .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, > + .sanity_check = rproc_elf_sanity_check, > + .get_boot_addr = rproc_elf_get_boot_addr, > +}; > + > +static void zynqmp_r5_print_dt_node_info(struct zynqmp_r5_cluster *cluster) > +{ > + int i, j, k; > + struct zynqmp_r5_core *r5_core; > + > + dev_dbg(cluster->dev, "Printing dt node info\n"); > + > + pr_debug("cluster mode = %d\n", cluster->mode); > + pr_debug("r5f cluster in %s mode\n", (cluster->mode == 0) ? "SPLIT" : > + cluster->mode == 1 ? "LOCKSTEP" : "SINGLE_CPU"); > + pr_debug("r5f num cores = %d\n", cluster->core_count); > + > + for (i = 0; i < cluster->core_count; i++) { > + r5_core = &cluster->r5_cores[i]; > + if (!r5_core) { > + pr_err("can't get r5_core\n"); > + continue; > + } > + > + pr_debug("r5 core %d nodes\n", i); > + pr_debug("TCM banks = %d\n", r5_core->tcm_bank_count); > + for (k = 0; k < r5_core->tcm_bank_count; k++) { > + pr_debug("tcm %d addr=0x%llx size=0x%lx, pm_id=%d, %s\n", > + k, r5_core->tcm_banks[k].addr, > + r5_core->tcm_banks[k].size, > + r5_core->tcm_banks[k].pm_domain_id, > + r5_core->tcm_banks[k].bank_name); > + } > + > + pr_debug("reserve mem regions = %d\n", r5_core->res_mem_count); > + > + for (j = 0; j < r5_core->res_mem_count; j++) { > + pr_debug("mem %d addr=0x%llx, size=0x%llx, name=%s\n", > + j, r5_core->res_mem[j].base, > + r5_core->res_mem[j].size, > + r5_core->res_mem[j].name); > + } > + } > +} > + > +/** > + * zynqmp_r5_add_rproc_core() - Probes ZynqMP R5 processor device node > + * this is called for each individual R5 core to > + * set up mailbox, Xilinx platform manager unique ID, > + * add to rproc core > + * > + * @r5_core: zynqmp_r5_core r5 core object to initialize > + * > + * Return: 0 for success, negative value for failure. > + */ > +static int zynqmp_r5_add_rproc_core(struct zynqmp_r5_core *r5_core) > +{ > + int ret; > + struct rproc *r5_rproc; > + struct device *dev; > + > + dev = r5_core->dev; > + > + /* Set up DMA mask */ > + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); > + if (ret) > + return ret; > + > + /* Allocate remoteproc instance */ > + r5_rproc = devm_rproc_alloc(dev, dev_name(dev), &zynqmp_r5_rproc_ops, > + NULL, sizeof(struct zynqmp_r5_core)); > + if (IS_ERR_OR_NULL(r5_rproc)) > + return -ENOMEM; > + > + r5_rproc->auto_boot = false; > + r5_rproc->priv = r5_core; > + > + /* Add R5 remoteproc */ > + ret = devm_rproc_add(dev, r5_rproc); > + if (ret) { > + pr_err("failed to add r5 remoteproc\n"); > + return ret; > + } > + > + return 0; > +} > + > +static int zynqmp_r5_get_tcm_node(struct zynqmp_r5_cluster *cluster) > +{ > + int tcm_bank_count, tcm_node; > + int i = 0, j; > + struct zynqmp_r5_core *r5_core; > + const struct mem_bank_data *tcm = zynqmp_tcm_banks; > + struct device *dev = cluster->dev; > + > + /* ToDo: Use predefined TCM address space values from driver until > + * system-dt spec is not final fot TCM > + */ > + tcm_bank_count = ARRAY_SIZE(zynqmp_tcm_banks); > + > + /* count per core tcm banks */ > + tcm_bank_count = tcm_bank_count / cluster->core_count; > + > + /* r5 core 0 will use all of TCM banks in lockstep mode. > + * In split mode, r5 core0 will use 128k and r5 core1 will use another > + * 128k. Assign TCM banks to each core accordingly > + */ > + tcm_node = 0; > + for (j = 0; j < cluster->core_count; j++) { > + r5_core = &cluster->r5_cores[j]; > + r5_core->tcm_banks = devm_kzalloc(dev, sizeof(struct mem_bank_data) * > + tcm_bank_count, GFP_KERNEL); > + if (IS_ERR_OR_NULL(r5_core->tcm_banks)) > + return -ENOMEM; > + > + for (i = 0; i < tcm_bank_count; i++) { > + /* Use pre-defined TCM reg values. > + * Eventually this should be replaced by values > + * parsed from dts. > + */ > + r5_core->tcm_banks[i].addr = tcm[tcm_node].addr; > + r5_core->tcm_banks[i].size = tcm[tcm_node].size; > + r5_core->tcm_banks[i].pm_domain_id = tcm[tcm_node].pm_domain_id; > + r5_core->tcm_banks[i].bank_name = tcm[tcm_node].bank_name; > + tcm_node++; > + } > + > + r5_core->tcm_bank_count = tcm_bank_count; > + } > + > + return 0; > +} > + > +static int zynqmp_r5_get_mem_region_node(struct zynqmp_r5_core *r5_core) > +{ > + int res_mem_count, i; > + struct device *dev; > + struct device_node *np, *rmem_np; > + struct reserved_mem *rmem; > + > + dev = r5_core->dev; > + > + np = r5_core->np; > + if (IS_ERR_OR_NULL(np)) { > + pr_err("invalid device node of r5 core\n"); > + return -EINVAL; > + } > + > + res_mem_count = of_property_count_elems_of_size(np, "memory-region", > + sizeof(phandle)); > + if (res_mem_count <= 0) { > + dev_warn(dev, "failed to get memory-region property %d\n", > + res_mem_count); > + return -EINVAL; > + } > + > + r5_core->res_mem = devm_kzalloc(dev, > + res_mem_count * sizeof(struct reserved_mem), > + GFP_KERNEL); > + if (!r5_core->res_mem) { > + dev_err(dev, "failed to allocate mem region memory\n"); > + return -ENOMEM; > + } > + > + for (i = 0; i < res_mem_count; i++) { > + rmem_np = of_parse_phandle(np, "memory-region", i); > + if (!rmem_np) > + return -EINVAL; > + > + rmem = of_reserved_mem_lookup(rmem_np); > + if (!rmem) { > + of_node_put(rmem_np); > + return -EINVAL; > + } > + > + memcpy(&r5_core->res_mem[i], rmem, > + sizeof(struct reserved_mem)); > + of_node_put(rmem_np); > + } > + > + r5_core->res_mem_count = res_mem_count; > + > + return 0; > +} > + > +static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster) > +{ > + int ret, i; > + struct zynqmp_r5_core *r5_core; > + struct device *dev = cluster->dev; > + > + ret = zynqmp_r5_get_tcm_node(cluster); > + if (ret < 0) { > + dev_err(dev, "can't get tcm node, err %d\n", ret); > + return ret; > + } > + > + for (i = 0; i < cluster->core_count; i++) { > + r5_core = &cluster->r5_cores[i]; > + if (!r5_core) { > + pr_err("invalid r5 core\n"); > + return -EINVAL; > + } > + > + ret = zynqmp_r5_get_mem_region_node(r5_core); > + if (ret) > + dev_warn(dev, "memory-region prop failed %d\n", ret); > + > + ret = of_property_read_u32_index(r5_core->np, "power-domains", > + 1, &r5_core->pm_domain_id); > + if (ret) { > + dev_err(dev, "failed to get power-domains property\n"); > + return ret; > + } > + > + ret = zynqmp_r5_set_mode(r5_core, cluster->mode); > + if (ret) > + return ret; > + > + ret = zynqmp_r5_add_rproc_core(r5_core); > + if (ret) { > + dev_err(dev, "failed to init r5 core %d\n", i); > + return ret; > + } > + } > + > + return 0; > +} > + > +static int zynqmp_r5_cluster_init(struct zynqmp_r5_cluster *cluster) > +{ > + struct device *dev = cluster->dev; > + struct device_node *dev_node = dev_of_node(dev); > + struct device_node *child; > + struct platform_device *child_pdev; > + int core_count = 0, ret, i; > + enum zynqmp_r5_cluster_mode cluster_mode = LOCKSTEP_MODE; > + struct zynqmp_r5_core *r5_cores; > + > + ret = of_property_read_u32(dev_node, "xlnx,cluster-mode", &cluster_mode); > + > + /* on success returns 0, if not defined then returns -EINVAL, > + * In that case, default is LOCKSTEP mode > + */ > + if (ret != -EINVAL && ret != 0) { > + dev_err(dev, "Invalid xlnx,cluster-mode property\n"); > + return -EINVAL; > + } > + > + if (cluster_mode == SINGLE_CPU_MODE) { > + dev_err(dev, "driver does not support single cpu mode\n"); > + return -EINVAL; > + } else if ((cluster_mode != SPLIT_MODE && > + cluster_mode != LOCKSTEP_MODE)) { > + dev_err(dev, "Invalid cluster mode\n"); > + return -EINVAL; > + } > + > + core_count = of_get_available_child_count(dev_node); > + if (core_count <= 0) { > + dev_err(dev, "Invalid number of r5 cores %d", core_count); > + return -EINVAL; > + } else if (cluster_mode == SPLIT_MODE && core_count != 2) { > + dev_err(dev, "Invalid number of r5 cores for split mode\n"); > + return -EINVAL; > + } else if (cluster_mode == LOCKSTEP_MODE && core_count == 2) { > + dev_warn(dev, "Only r5 core0 will be used\n"); > + core_count = 1; > + } > + > + r5_cores = devm_kzalloc(dev, sizeof(struct zynqmp_r5_core) * > + core_count, GFP_KERNEL); > + if (IS_ERR_OR_NULL(r5_cores)) { > + dev_err(dev, "can't allocate memory for cores\n"); > + return -ENOMEM; > + } > + > + i = 0; > + for_each_available_child_of_node(dev_node, child) { > + child_pdev = of_find_device_by_node(child); > + if (!child_pdev) > + return -ENODEV; > + > + r5_cores[i].dev = &child_pdev->dev; > + if (!r5_cores[i].dev) { > + pr_err("can't get device for r5 core %d\n", i); > + return -ENODEV; > + } > + > + r5_cores[i].np = dev_of_node(r5_cores[i].dev); > + if (!r5_cores[i].np) { > + pr_err("can't get device node for r5 core %d\n", i); > + return -ENODEV; > + } > + > + i++; > + if (i == core_count) > + break; > + } > + > + cluster->mode = cluster_mode; > + cluster->core_count = core_count; > + cluster->r5_cores = r5_cores; > + > + ret = zynqmp_r5_core_init(cluster); > + if (ret < 0) { > + dev_err(dev, "failed to init r5 core err %d\n", ret); > + return ret; > + } > + > + zynqmp_r5_print_dt_node_info(cluster); > + > + return 0; > +} > + > +static void zynqmp_r5_cluster_exit(void *data) > +{ > + struct platform_device *pdev = (struct platform_device *)data; > + > + platform_set_drvdata(pdev, NULL); > + > + pr_info("Exit r5f subsystem driver\n"); > +} > + > +/* > + * zynqmp_r5_remoteproc_probe() > + * > + * @pdev: domain platform device for R5 cluster > + * > + * called when driver is probed, for each R5 core specified in DT, > + * setup as needed to do remoteproc-related operations > + * > + * Return: 0 for success, negative value for failure. > + */ > +static int zynqmp_r5_remoteproc_probe(struct platform_device *pdev) > +{ > + int ret; > + struct zynqmp_r5_cluster *cluster; > + struct device *dev = &pdev->dev; > + > + cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL); > + if (IS_ERR_OR_NULL(cluster)) > + return -ENOMEM; > + > + cluster->dev = dev; > + > + ret = devm_of_platform_populate(dev); > + if (ret) { > + dev_err(dev, "failed to populate platform dev %d\n", ret); > + return ret; > + } > + > + /* wire in so each core can be cleaned up at driver remove */ > + platform_set_drvdata(pdev, cluster); > + > + ret = devm_add_action_or_reset(dev, zynqmp_r5_cluster_exit, pdev); > + if (ret) > + return ret; > + > + ret = zynqmp_r5_cluster_init(cluster); > + if (ret) { > + dev_err(dev, "Invalid r5f subsystem device tree\n"); > + return ret; > + } > + > + dev_info(dev, "Xilinx r5f remoteproc driver probe success\n"); > + return 0; > +} > + > +/* Match table for OF platform binding */ > +static const struct of_device_id zynqmp_r5_remoteproc_match[] = { > + { .compatible = "xlnx,zynqmp-r5fss", }, > + { /* end of list */ }, > +}; > +MODULE_DEVICE_TABLE(of, zynqmp_r5_remoteproc_match); > + > +static struct platform_driver zynqmp_r5_remoteproc_driver = { > + .probe = zynqmp_r5_remoteproc_probe, > + .driver = { > + .name = "zynqmp_r5_remoteproc", > + .of_match_table = zynqmp_r5_remoteproc_match, > + }, > +}; > +module_platform_driver(zynqmp_r5_remoteproc_driver); > + > +MODULE_DESCRIPTION("Xilinx R5F remote processor driver"); > +MODULE_AUTHOR("Xilinx Inc."); > +MODULE_LICENSE("GPL v2"); > -- > 2.25.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4DEBC4332F for ; Mon, 29 Nov 2021 18:44:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UaOCaO7n1pqmep5RYa8VxsBZ+VlKu0X9r0FXAGj/TNQ=; b=Au87BKDkC5BGQW l9hcXB+898WFMBac7YNCcU7F1JYGI/fBOnDJc7Ox2LuKgND9rzal+j1yC2eqIzdKEF8myUhUjKMLH Ha3urvggBz++AonDW7rbKFTDb4tMSAS1Ilz3YzHAbU/3+eS4ByouWgOnN6NV95b5XDMZyjCp9JmNS qX9Od81/+Df9FmL8Q5Pa/1o4Kx3ExUGZ7B0LLGevr3Zo5WQJ9LEgiPR00QqGXVCBiWdxbMyAI6MlJ nUyoBqNzmSLsiD/J/NjgG5afJ53JjjefRHR6ynPB/eL2UUTRvsvjWCf7qXOJotTYRpSjaaokIAhFH CmgDdHk1NevtH3Jvy+Tg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrlbk-001qN5-1h; Mon, 29 Nov 2021 18:42:32 +0000 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrlbe-001qLe-51 for linux-arm-kernel@lists.infradead.org; Mon, 29 Nov 2021 18:42:29 +0000 Received: by mail-pl1-x632.google.com with SMTP id p18so12876383plf.13 for ; Mon, 29 Nov 2021 10:42:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=2IMr/BG9SkG1AxTTzKV9LR6CsVGkTzK2wg6sT7xbgaY=; b=i2UiZHlCr5kh66jgKovJqtSDwEb2zvZxfexnbXArZfogOkqr1VdL0xr+QH8hHpZNAD UWogBpVDNH0qZW09LWftG0RTboPgKxWpk7zkbbZ7b1YUGosK3Z9GLtTJbRy+do4ubj4f vyMTAc6SKaESup1+uewCAFSHV7J16IKwMQuGs4VE+PDiuZHlI/BlNqP1fIhg6R+iMANv gWeo0sgX/88ZQumi4hWq0oK3GEo7GVjfE28oRP7FVPOErIa98EL9fbRdD5157O4/I68n pkxOgbTHTvOj5rVTNVL6p1/8Kga5MdvArqoOa8eg9bCLuV52PrVR++zre1fqOASEOZH3 dszg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=2IMr/BG9SkG1AxTTzKV9LR6CsVGkTzK2wg6sT7xbgaY=; b=cwns2vEPPXkelAseMejqsEVf3qR5uOUk/U/cmqr81Al2Zh0ZJ6hqwxg8tK4ow/ACkY ybjFmA+9DVjUMQFfkTIe2d+Fgr4o7+31LzaQNZ0M0DhICi8fvjOYftZ3L0LW00bJ/gRY InhbmcLPXJA9P0FUWTPhv/KwKHrZ+V6PAT4ECFND16kBNspxjkrVMANDeY7oHV7yrlPb KqhuhLnB4UD0sChuarOidhBitTfbVbfm/hEuH1JrsJkd8IbE2Ps1s59FKLtdeVlhx1xA adCCKvye+AMVc4L+vprIfPqPX2hjzaMi48i88YGhM4ZTyFKMliR/q/PPXGQktg8vgCJS wi0Q== X-Gm-Message-State: AOAM531cuxo4ny3WxZjdpG1bUWI6uesevJ6GlsAWKgnHVP97SOsGs1DW +RqjCsGFucPNfa6ABTaodR8e2g== X-Google-Smtp-Source: ABdhPJwWwOxc8+HeQFmuo3O0W96Alxb/yDMazm3THHZSgFU8EAd83s4bQidn0D5Qk/sOGgIXOT8P7w== X-Received: by 2002:a17:902:7c02:b0:143:9d6a:8e42 with SMTP id x2-20020a1709027c0200b001439d6a8e42mr61675120pll.80.1638211344267; Mon, 29 Nov 2021 10:42:24 -0800 (PST) Received: from p14s (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id v10sm18800459pfu.123.2021.11.29.10.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 10:42:23 -0800 (PST) Date: Mon, 29 Nov 2021 11:42:19 -0700 From: Mathieu Poirier To: Tanmay Shah Cc: Bjorn Andersson , Rob Herring , Michal Simek , Laurent Pinchart , Ben Levinsky , Bill Mills , Sergei Korneichuk , linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 6/6] drivers: remoteproc: Add Xilinx r5 remoteproc driver Message-ID: <20211129184219.GC676889@p14s> References: <20211123062050.1442712-1-tanmay.shah@xilinx.com> <20211123062050.1442712-7-tanmay.shah@xilinx.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211123062050.1442712-7-tanmay.shah@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_104226_282514_3E42FBE4 X-CRM114-Status: GOOD ( 40.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCBOb3YgMjIsIDIwMjEgYXQgMTA6MjA6NTBQTSAtMDgwMCwgVGFubWF5IFNoYWggd3Jv dGU6Cj4gVGhpcyBkcml2ZXIgZW5hYmxlcyByNWYgZHVhbCBjb3JlIFJlYWwgdGltZSBQcm9jZXNz aW5nIFVuaXQgc3Vic3lzdGVtCj4gYXZhaWxhYmxlIG9uIFhpbGlueCBaeW5xIFVsdHJhc2NhbGUg TVBTb0MgUGxhdGZvcm0uIFJQVSBzdWJzeXN0ZW0KPiAoY2x1c3RlcikgY2FuIGJlIGNvbmZpZ3Vy ZWQgaW4gZGlmZmVyZW50IG1vZGVzIGUuZy4gc3BsaXQgbW9kZSBpbiB3aGljaAo+IHR3byByNWYg Y29yZXMgd29yayBpbmRlcGVuZGVudCBvZiBlYWNoIG90aGVyIGFuZCBsb2NrLXN0ZXAgbW9kZSBp biB3aGljaAo+IGJvdGggcjVmIGNvcmVzIGV4ZWN1dGUgc2FtZSBjb2RlIGNsb2NrLWZvci1jbG9j ayBhbmQgbm90aWZ5IGlmIHRoZQo+IHJlc3VsdCBpcyBkaWZmZXJlbnQuCj4gCj4gVGhlIFhpbGlu eCByNSBSZW1vdGVwcm9jIERyaXZlciBib290cyB0aGUgUlBVIGNvcmVzIHZpYSBjYWxscyB0byB0 aGUgWGlsaW54Cj4gUGxhdGZvcm0gTWFuYWdlbWVudCBVbml0IHRoYXQgaGFuZGxlcyB0aGUgUjUg Y29uZmlndXJhdGlvbiwgbWVtb3J5IGFjY2Vzcwo+IGFuZCBSNSBsaWZlY3ljbGUgbWFuYWdlbWVu dC4gVGhlIGludGVyZmFjZSB0byB0aGlzIG1hbmFnZXIgaXMgZG9uZSBpbiB0aGlzCj4gZHJpdmVy IHZpYSB6eW5xbXBfcG1fKiBmdW5jdGlvbiBjYWxscy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBCZW4g TGV2aW5za3kgPGJlbi5sZXZpbnNreUB4aWxpbnguY29tPgo+IFNpZ25lZC1vZmYtYnk6IFRhbm1h eSBTaGFoIDx0YW5tYXkuc2hhaEB4aWxpbnguY29tPgo+IC0tLQo+ICBkcml2ZXJzL3JlbW90ZXBy b2MvS2NvbmZpZyAgICAgICAgICAgICAgfCAgMTIgKwo+ICBkcml2ZXJzL3JlbW90ZXByb2MvTWFr ZWZpbGUgICAgICAgICAgICAgfCAgIDEgKwo+ICBkcml2ZXJzL3JlbW90ZXByb2MveGxueF9yNV9y ZW1vdGVwcm9jLmMgfCA5NTkgKysrKysrKysrKysrKysrKysrKysrKysrCj4gIDMgZmlsZXMgY2hh bmdlZCwgOTcyIGluc2VydGlvbnMoKykKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvcmVt b3RlcHJvYy94bG54X3I1X3JlbW90ZXByb2MuYwoKLi4uYW5kIHRoaXMgcGF0Y2ggZ2l2ZXMgbWUg Y29tcGxhdGlvbiB3YXJuaW5nczoKCiAgQ0MgICAgICBkcml2ZXJzL3JlbW90ZXByb2MveGxueF9y NV9yZW1vdGVwcm9jLm8Ka2VybmVsLXJldmlldy9kcml2ZXJzL3JlbW90ZXByb2MveGxueF9yNV9y ZW1vdGVwcm9jLmM6IEluIGZ1bmN0aW9uIOKAmGFkZF90Y21fY2FydmVvdXRfbG9ja3N0ZXBfbW9k ZeKAmToKa2VybmVsLXJldmlldy9kcml2ZXJzL3JlbW90ZXByb2MveGxueF9yNV9yZW1vdGVwcm9j LmM6NDEyOjI4OiB3YXJuaW5nOiB1bnVzZWQgdmFyaWFibGUg4oCYY2x1c3RlcuKAmSBbLVd1bnVz ZWQtdmFyaWFibGVdCiAgNDEyIHwgIHN0cnVjdCB6eW5xbXBfcjVfY2x1c3RlciAqY2x1c3RlcjsK ICAgICAgfCAgICAgICAgICAgICAgICAgICAgICAgICAgICBefn5+fn5+Cmtlcm5lbC1yZXZpZXcv ZHJpdmVycy9yZW1vdGVwcm9jL3hsbnhfcjVfcmVtb3RlcHJvYy5jOjQxMToyNjogd2FybmluZzog dW51c2VkIHZhcmlhYmxlIOKAmHBhcmVudF9wZGV24oCZIFstV3VudXNlZC12YXJpYWJsZV0KICA0 MTEgfCAgc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGFyZW50X3BkZXY7CiAgICAgIHwgICAgICAg ICAgICAgICAgICAgICAgICAgIF5+fn5+fn5+fn5+CgpUaGUgYWJvdmUgbGVhZHMgbWUgdG8gYmVs aWV2ZSB0aGlzIHBhdGNoc2V0IHdhcyBub3QgY29tcGlsZWQgYmVmb3JlIGl0IHdhcyBzZW50Cm91 dC4KCkJlaW5nIG5ldyB0byB0aGlzIEkgY2FuIHVuZGVyc3RhbmQgdGhhdCBjaGVja3BhdGNoLnBs IHdhcyBvbWl0dGVkIChhbGJlaXQgYW1wbHkKZG9jdW1lbnRlZCkgYnV0IG9idmlvdXMgY29tcGls YXRpb24gd2FybmluZ3MgY2FuJ3QgYmUgZXhjdXNlZC4gIEFzIHN1Y2ggSQphbSBkcm9wcGluZyB0 aGlzIHNldCBhbmQgd2lsbCBub3QgcmV2aWV3IGFub3RoZXIgdmVyc2lvbiB1bnRpbCBKYW51YXJ5 LgoKTWF0aGlldQoKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9yZW1vdGVwcm9jL0tjb25maWcg Yi9kcml2ZXJzL3JlbW90ZXByb2MvS2NvbmZpZwo+IGluZGV4IGYzMGQwMGEzYWFiZS4uMjdmNjY5 MTBkOGQzIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcmVtb3RlcHJvYy9LY29uZmlnCj4gKysrIGIv ZHJpdmVycy9yZW1vdGVwcm9jL0tjb25maWcKPiBAQCAtMzE1LDYgKzMxNSwxOCBAQCBjb25maWcg VElfSzNfUjVfUkVNT1RFUFJPQwo+ICAJICBJdCdzIHNhZmUgdG8gc2F5IE4gaGVyZSBpZiB5b3Un cmUgbm90IGludGVyZXN0ZWQgaW4gdXRpbGl6aW5nCj4gIAkgIGEgc2xhdmUgcHJvY2Vzc29yLgo+ ICAKPiArY29uZmlnIFhMTlhfUjVfUkVNT1RFUFJPQwo+ICsJdHJpc3RhdGUgIlhpbGlueCBSNSBy ZW1vdGVwcm9jIHN1cHBvcnQiCj4gKwlkZXBlbmRzIG9uIFBNICYmIEFSQ0hfWllOUU1QCj4gKwlk ZXBlbmRzIG9uIFpZTlFNUF9GSVJNV0FSRQo+ICsJc2VsZWN0IFJQTVNHX1ZJUlRJTwo+ICsJc2Vs ZWN0IFpZTlFNUF9JUElfTUJPWAo+ICsJaGVscAo+ICsJICBTYXkgeSBvciBtIGhlcmUgdG8gc3Vw cG9ydCBYaWxpbnggUjUgcmVtb3RlIHByb2Nlc3NvcnMgdmlhIHRoZSByZW1vdGUKPiArCSAgcHJv Y2Vzc29yIGZyYW1ld29yay4KPiArCj4gKwkgIEl0J3Mgc2FmZSB0byBzYXkgTiBpZiBub3QgaW50 ZXJlc3RlZCBpbiB1c2luZyBSUFUgcjVmIGNvcmVzLgo+ICsKPiAgZW5kaWYgIyBSRU1PVEVQUk9D Cj4gIAo+ICBlbmRtZW51Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcmVtb3RlcHJvYy9NYWtlZmls ZSBiL2RyaXZlcnMvcmVtb3RlcHJvYy9NYWtlZmlsZQo+IGluZGV4IGJiMjZjOWU0ZWY5Yy4uMzM0 YThiZWQ0YzE0IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcmVtb3RlcHJvYy9NYWtlZmlsZQo+ICsr KyBiL2RyaXZlcnMvcmVtb3RlcHJvYy9NYWtlZmlsZQo+IEBAIC0zNSwzICszNSw0IEBAIG9iai0k KENPTkZJR19TVF9TTElNX1JFTU9URVBST0MpCSs9IHN0X3NsaW1fcnByb2Mubwo+ICBvYmotJChD T05GSUdfU1RNMzJfUlBST0MpCQkrPSBzdG0zMl9ycHJvYy5vCj4gIG9iai0kKENPTkZJR19USV9L M19EU1BfUkVNT1RFUFJPQykJKz0gdGlfazNfZHNwX3JlbW90ZXByb2Mubwo+ICBvYmotJChDT05G SUdfVElfSzNfUjVfUkVNT1RFUFJPQykJKz0gdGlfazNfcjVfcmVtb3RlcHJvYy5vCj4gK29iai0k KENPTkZJR19YTE5YX1I1X1JFTU9URVBST0MpCSs9IHhsbnhfcjVfcmVtb3RlcHJvYy5vCj4gZGlm ZiAtLWdpdCBhL2RyaXZlcnMvcmVtb3RlcHJvYy94bG54X3I1X3JlbW90ZXByb2MuYyBiL2RyaXZl cnMvcmVtb3RlcHJvYy94bG54X3I1X3JlbW90ZXByb2MuYwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0 Cj4gaW5kZXggMDAwMDAwMDAwMDAwLi5jMjE2N2ZkMzg2OWQKPiAtLS0gL2Rldi9udWxsCj4gKysr IGIvZHJpdmVycy9yZW1vdGVwcm9jL3hsbnhfcjVfcmVtb3RlcHJvYy5jCj4gQEAgLTAsMCArMSw5 NTkgQEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKPiArLyoKPiArICog WnlucU1QIFI1IFJlbW90ZSBQcm9jZXNzb3IgZHJpdmVyCj4gKyAqCj4gKyAqLwo+ICsKPiArI2lu Y2x1ZGUgPGR0LWJpbmRpbmdzL3Bvd2VyL3hsbngtenlucW1wLXBvd2VyLmg+Cj4gKyNpbmNsdWRl IDxsaW51eC9maXJtd2FyZS94bG54LXp5bnFtcC5oPgo+ICsjaW5jbHVkZSA8bGludXgvaW50ZXJy dXB0Lmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2xp c3QuaD4KPiArI2luY2x1ZGUgPGxpbnV4L21haWxib3hfY2xpZW50Lmg+Cj4gKyNpbmNsdWRlIDxs aW51eC9tYWlsYm94L3p5bnFtcC1pcGktbWVzc2FnZS5oPgo+ICsjaW5jbHVkZSA8bGludXgvbW9k dWxlLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9vZl9hZGRyZXNzLmg+Cj4gKyNpbmNsdWRlIDxsaW51 eC9vZl9wbGF0Zm9ybS5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2ZfcmVzZXJ2ZWRfbWVtLmg+Cj4g KyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZpY2UuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3Jl bW90ZXByb2MuaD4KPiArI2luY2x1ZGUgPGxpbnV4L3NrYnVmZi5oPgo+ICsjaW5jbHVkZSA8bGlu dXgvc3lzZnMuaD4KPiArCj4gKyNpbmNsdWRlICJyZW1vdGVwcm9jX2ludGVybmFsLmgiCj4gKwo+ ICsvKiBzZXR0aW5ncyBmb3IgUlBVIGNsdXN0ZXIgbW9kZSAqLwo+ICtlbnVtIHp5bnFtcF9yNV9j bHVzdGVyX21vZGUgewo+ICsJU1BMSVRfTU9ERSA9IDAsIC8vIFJQVSBjbHVzdGVyIG1vZGUgd2hl biBjb3JlcyBydW4gYXMgc2VwYXJhdGUgcHJvY2Vzc29yCj4gKwlMT0NLU1RFUF9NT0RFID0gMSwg Ly8gY29yZXMgZXhlY3V0ZSBzYW1lIGNvZGUgaW4gbG9ja3N0ZXAsY2xrLWZvci1jbGsKPiArCVNJ TkdMRV9DUFVfTU9ERSA9IDIsIC8vIGNvcmUwIGlzIGhlbGQgaW4gcmVzZXQgYW5kIG9ubHkgY29y ZTEgcnVucwo+ICt9Owo+ICsKPiArLyoqCj4gKyAqIHN0cnVjdCBtZW1fYmFua19kYXRhIC0gTWVt b3J5IEJhbmsgZGVzY3JpcHRpb24KPiArICoKPiArICogQGFkZHI6IFN0YXJ0IGFkZHJlc3Mgb2Yg bWVtb3J5IGJhbmsKPiArICogQHNpemU6IFNpemUgb2YgTWVtb3J5IGJhbmsKPiArICogQHBtX2Rv bWFpbl9pZDogUG93ZXItZG9tYWlucyBpZCBvZiBtZW1vcnkgYmFuayBmb3IgZmlybXdhcmUgdG8g dHVybiBvbi9vZmYKPiArICogQGJhbmtfbmFtZTogbmFtZSBvZiB0aGUgYmFuayBmb3IgcmVtb3Rl cHJvYyBmcmFtZXdvcmsKPiArICovCj4gK3N0cnVjdCBtZW1fYmFua19kYXRhIHsKPiArCXBoeXNf YWRkcl90IGFkZHI7Cj4gKwlzaXplX3Qgc2l6ZTsKPiArCWVudW0gcG1fbm9kZV9pZCBwbV9kb21h aW5faWQ7Cj4gKwljaGFyICpiYW5rX25hbWU7Cj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IG1lbV9iYW5rX2RhdGEgenlucW1wX3RjbV9iYW5rc1tdID0gewo+ICsJezB4ZmZlMDAwMDBV TCwgMHgxMDAwMFVMLCBQRF9SNV8wX0FUQ00sICJhdGNtMCJ9LCAvKiBUQ00gNjRLQiBlYWNoICov Cj4gKwl7MHhmZmUyMDAwMFVMLCAweDEwMDAwVUwsIFBEX1I1XzBfQlRDTSwgImJ0Y20wIn0sCj4g Kwl7MHhmZmU5MDAwMFVMLCAweDEwMDAwVUwsIFBEX1I1XzFfQVRDTSwgImF0Y20xIn0sCj4gKwl7 MHhmZmViMDAwMFVMLCAweDEwMDAwVUwsIFBEX1I1XzFfQlRDTSwgImJ0Y20xIn0sCj4gK307Cj4g Kwo+ICsvKioKPiArICogc3RydWN0IHp5bnFtcF9yNV9jb3JlIC0gWnlucU1QIFI1IGNvcmUgc3Ry dWN0dXJlCj4gKyAqCj4gKyAqIEBkZXY6IGRldmljZSBvZiBSUFUgaW5zdGFuY2UKPiArICogQG5w OiBkZXZpY2Ugbm9kZSBvZiBSUFUgaW5zdGFuY2UKPiArICogQHRjbV9iYW5rX2NvdW50OiBudW1i ZXIgVENNIGJhbmtzIGFjY2Vzc2libGUgdG8gdGhpcyBSUFUKPiArICogQHRjbV9iYW5rczogYXJy YXkgb2YgZWFjaCBUQ00gYmFuayBkYXRhCj4gKyAqIEByZXNfbWVtX2NvdW50OiBudW1iZXIgb2Yg UmVzZXJ2ZWQgTWVtb3J5IHJlZ2lvbnMgcGVyIGNvcmUKPiArICogQHJlc19tZW06IGFycmF5IG9m IHJlc2VydmVkIG1lbW9yeSByZWdpb25zCj4gKyAqIEBycHJvYzogcnByb2MgaGFuZGxlCj4gKyAq IEBwbV9kb21haW5faWQ6IFJQVSBDUFUgcG93ZXIgZG9tYWluIGlkCj4gKyAqLwo+ICtzdHJ1Y3Qg enlucW1wX3I1X2NvcmUgewo+ICsJc3RydWN0IGRldmljZSAqZGV2Owo+ICsJc3RydWN0IGRldmlj ZV9ub2RlICpucDsKPiArCWludCB0Y21fYmFua19jb3VudDsKPiArCXN0cnVjdCBtZW1fYmFua19k YXRhICp0Y21fYmFua3M7Cj4gKwlpbnQgcmVzX21lbV9jb3VudDsKPiArCXN0cnVjdCByZXNlcnZl ZF9tZW0gKnJlc19tZW07Cj4gKwlzdHJ1Y3QgcnByb2MgKnJwcm9jOwo+ICsJZW51bSBwbV9ub2Rl X2lkIHBtX2RvbWFpbl9pZDsKPiArfTsKPiArCj4gKy8qKgo+ICsgKiBzdHJ1Y3QgenlucW1wX3I1 X2NsdXN0ZXIgLSBaeW5xTVAgUjUgY2x1c3RlciBzdHJ1Y3R1cmUKPiArICoKPiArICogQGRldjog cjVmIHN1YnN5c3RlbSBjbHVzdGVyIGRldmljZSBub2RlCj4gKyAqIEBtb2RlOiBjbHVzdGVyIG1v ZGUgb2YgdHlwZSB6eW5xbXBfcjVfY2x1c3Rlcl9tb2RlCj4gKyAqIEBjb3JlX2NvdW50OiBudW1i ZXIgb2YgcjUgY29yZXMgdXNlZCBmb3IgdGhpcyBjbHVzdGVyIG1vZGUKPiArICogQHI1X2NvcmVz OiBBcnJheSBvZiByNSBjb3JlcyBvZiB0eXBlIHN0cnVjdCB6eW5xbXBfcjVfY29yZQo+ICsgKi8K PiArc3RydWN0IHp5bnFtcF9yNV9jbHVzdGVyIHsKPiArCXN0cnVjdCBkZXZpY2UgKmRldjsKPiAr CWVudW0gIHp5bnFtcF9yNV9jbHVzdGVyX21vZGUgbW9kZTsKPiArCWludCBjb3JlX2NvdW50Owo+ ICsJc3RydWN0IHp5bnFtcF9yNV9jb3JlICpyNV9jb3JlczsKPiArfTsKPiArCj4gKy8qCj4gKyAq IHp5bnFtcF9yNV9zZXRfbW9kZSAtIHNldCBSUFUgb3BlcmF0aW9uIG1vZGUKPiArICoKPiArICog c2V0IFJQVSBvcGVyYXRpb24gbW9kZQo+ICsgKgo+ICsgKiBSZXR1cm46IDAgZm9yIHN1Y2Nlc3Ms IG5lZ2F0aXZlIHZhbHVlIGZvciBmYWlsdXJlCj4gKyAqLwo+ICtzdGF0aWMgaW50IHp5bnFtcF9y NV9zZXRfbW9kZShzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKnI1X2NvcmUsCj4gKwkJCSAgICAgIGVu dW0genlucW1wX3I1X2NsdXN0ZXJfbW9kZSBycHVfbW9kZSkKPiArewo+ICsJZW51bSBycHVfdGNt X2NvbWIgdGNtX21vZGU7Cj4gKwlpbnQgcmV0LCByZWdfdmFsOwo+ICsKPiArCXJlZ192YWwgPSAo cnB1X21vZGUgPT0gTE9DS1NURVBfTU9ERSA/IDAgOiAxKTsKPiArCj4gKwlyZXQgPSB6eW5xbXBf cG1fc2V0X3JwdV9tb2RlKHI1X2NvcmUtPnBtX2RvbWFpbl9pZCwgcmVnX3ZhbCk7Cj4gKwlpZiAo cmV0IDwgMCkgewo+ICsJCXByX2VycigiZmFpbGVkIHRvIHNldCBSUFUgbW9kZVxuIik7Cj4gKwkJ cmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwl0Y21fbW9kZSA9IChycHVfbW9kZSA9PSBMT0NLU1RF UF9NT0RFKSA/Cj4gKwkJICAgIFBNX1JQVV9UQ01fQ09NQiA6IFBNX1JQVV9UQ01fU1BMSVQ7Cj4g KwlyZXQgPSB6eW5xbXBfcG1fc2V0X3RjbV9jb25maWcocjVfY29yZS0+cG1fZG9tYWluX2lkLCB0 Y21fbW9kZSk7Cj4gKwlpZiAocmV0IDwgMCkKPiArCQlwcl9lcnIoImZhaWxlZCB0byBjb25maWd1 cmUgVENNXG4iKTsKPiArCj4gKwlyZXR1cm4gcmV0Owo+ICt9Cj4gKwo+ICsvKgo+ICsgKiB6eW5x bXBfcjVfcnByb2Nfc3RhcnQKPiArICogQHJwcm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJlc3Bv bmRpbmcgcnByb2MgaW5zdGFuY2UKPiArICoKPiArICogU3RhcnQgUjUgQ29yZSBmcm9tIGRlc2ln bmF0ZWQgYm9vdCBhZGRyZXNzLgo+ICsgKgo+ICsgKiByZXR1cm4gMCBvbiBzdWNjZXNzLCBvdGhl cndpc2Ugbm9uLXplcm8gdmFsdWUgb24gZmFpbHVyZQo+ICsgKi8KPiArc3RhdGljIGludCB6eW5x bXBfcjVfcnByb2Nfc3RhcnQoc3RydWN0IHJwcm9jICpycHJvYykKPiArewo+ICsJc3RydWN0IHp5 bnFtcF9yNV9jb3JlICpyNV9jb3JlID0gcnByb2MtPnByaXY7Cj4gKwllbnVtIHJwdV9ib290X21l bSBib290bWVtOwo+ICsJaW50IHJldDsKPiArCj4gKwlpZiAoIXI1X2NvcmUpIHsKPiArCQlwcl9l cnIoImNhbid0IGdldCByNSBjb3JlXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KPiAr Cj4gKwlib290bWVtID0gKHJwcm9jLT5ib290YWRkciA+PSAweEZGRkMwMDAwKSA/Cj4gKwkJICAg UE1fUlBVX0JPT1RNRU1fSElWRUMgOiBQTV9SUFVfQk9PVE1FTV9MT1ZFQzsKPiArCj4gKwlkZXZf ZGJnKHI1X2NvcmUtPmRldiwgIlJQVSBib290IGFkZHIgMHglbGx4IGZyb20gJXMuIiwgcnByb2Mt PmJvb3RhZGRyLAo+ICsJCWJvb3RtZW0gPT0gUE1fUlBVX0JPT1RNRU1fSElWRUMgPyAiT0NNIiA6 ICJUQ00iKTsKPiArCj4gKwlyZXQgPSB6eW5xbXBfcG1fcmVxdWVzdF93YWtlKHI1X2NvcmUtPnBt X2RvbWFpbl9pZCwgMSwKPiArCQkJCSAgICAgYm9vdG1lbSwgWllOUU1QX1BNX1JFUVVFU1RfQUNL X05PKTsKPiArCWlmIChyZXQpCj4gKwkJcHJfZXJyKCJmYWlsZWQgdG8gc3RhcnQgUlBVID0gJWRc biIsIHI1X2NvcmUtPnBtX2RvbWFpbl9pZCk7Cj4gKwlyZXR1cm4gcmV0Owo+ICt9Cj4gKwo+ICsv Kgo+ICsgKiB6eW5xbXBfcjVfcnByb2Nfc3RvcAo+ICsgKiBAcnByb2M6IHNpbmdsZSBSNSBjb3Jl J3MgY29ycmVzcG9uZGluZyBycHJvYyBpbnN0YW5jZQo+ICsgKgo+ICsgKiBQb3dlciBkb3duICBS NSBDb3JlLgo+ICsgKgo+ICsgKiByZXR1cm4gMCBvbiBzdWNjZXNzLCBvdGhlcndpc2Ugbm9uLXpl cm8gdmFsdWUgb24gZmFpbHVyZQo+ICsgKi8KPiArc3RhdGljIGludCB6eW5xbXBfcjVfcnByb2Nf c3RvcChzdHJ1Y3QgcnByb2MgKnJwcm9jKQo+ICt7Cj4gKwlzdHJ1Y3QgenlucW1wX3I1X2NvcmUg KnI1X2NvcmUgPSBycHJvYy0+cHJpdjsKPiArCWludCByZXQ7Cj4gKwo+ICsJcmV0ID0genlucW1w X3BtX2ZvcmNlX3B3cmR3bihyNV9jb3JlLT5wbV9kb21haW5faWQsCj4gKwkJCQkgICAgIFpZTlFN UF9QTV9SRVFVRVNUX0FDS19CTE9DS0lORyk7Cj4gKwlpZiAocmV0KQo+ICsJCXByX2VycigiZmFp bGVkIHRvIHN0b3AgcmVtb3RlcHJvYyBSUFUgJWRcbiIsIHJldCk7Cj4gKwo+ICsJcmV0dXJuIHJl dDsKPiArfQo+ICsKPiArLyoKPiArICogenlucW1wX3I1X3Jwcm9jX21lbV9tYXAKPiArICogQHJw cm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJlc3BvbmRpbmcgcnByb2MgaW5zdGFuY2UKPiArICog QG1lbTogbWVtIGVudHJ5IHRvIG1hcAo+ICsgKgo+ICsgKiBDYWxsYmFjayB0byBtYXAgdmEgZm9y IG1lbW9yeS1yZWdpb24ncyBjYXJ2ZW91dC4KPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vz cywgb3RoZXJ3aXNlIG5vbi16ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBp bnQgenlucW1wX3I1X3Jwcm9jX21lbV9tYXAoc3RydWN0IHJwcm9jICpycHJvYywKPiArCQkJCSAg IHN0cnVjdCBycHJvY19tZW1fZW50cnkgKm1lbSkKPiArewo+ICsJdm9pZCBfX2lvbWVtICp2YTsK PiArCj4gKwl2YSA9IGlvcmVtYXBfd2MobWVtLT5kbWEsIG1lbS0+bGVuKTsKPiArCWlmIChJU19F UlJfT1JfTlVMTCh2YSkpCj4gKwkJcmV0dXJuIC1FTk9NRU07Cj4gKwo+ICsJbWVtLT52YSA9ICh2 b2lkICopdmE7Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gKy8qCj4gKyAqIHp5bnFtcF9y NV9ycHJvY19tZW1fdW5tYXAKPiArICogQHJwcm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJlc3Bv bmRpbmcgcnByb2MgaW5zdGFuY2UKPiArICogQG1lbTogbWVtIGVudHJ5IHRvIHVubWFwCj4gKyAq Cj4gKyAqIFVubWFwIG1lbW9yeS1yZWdpb24gY2FydmVvdXQKPiArICoKPiArICogcmV0dXJuIDAg b24gc3VjY2Vzcywgb3RoZXJ3aXNlIG5vbi16ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4g K3N0YXRpYyBpbnQgenlucW1wX3I1X3Jwcm9jX21lbV91bm1hcChzdHJ1Y3QgcnByb2MgKnJwcm9j LAo+ICsJCQkJICAgICBzdHJ1Y3QgcnByb2NfbWVtX2VudHJ5ICptZW0pCj4gK3sKPiArCWlvdW5t YXAoKHZvaWQgX19pb21lbSAqKW1lbS0+dmEpOwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gKy8q Cj4gKyAqIGFkZF9tZW1fcmVnaW9ucwo+ICsgKiBAcnByb2M6IHNpbmdsZSBSNSBjb3JlJ3MgY29y cmVzcG9uZGluZyBycHJvYyBpbnN0YW5jZQo+ICsgKgo+ICsgKiBDb25zdHJ1Y3QgcnByb2MgbWVt IGNhcnZlb3V0cyBmcm9tIGNhcnZlb3V0IHByb3ZpZGVkIGluCj4gKyAqIG1lbW9yeS1yZWdpb24g cHJvcGVydHkKPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vzcywgb3RoZXJ3aXNlIG5vbi16 ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBpbnQgYWRkX21lbV9yZWdpb25z KHN0cnVjdCBycHJvYyAqcnByb2MpCj4gK3sKPiArCXN0cnVjdCBkZXZpY2UgKmRldjsKPiArCXN0 cnVjdCBycHJvY19tZW1fZW50cnkgKm1lbTsKPiArCXN0cnVjdCByZXNlcnZlZF9tZW0gKnJtZW07 Cj4gKwlzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKnI1X2NvcmU7Cj4gKwlpbnQgaTsKPiArCj4gKwly NV9jb3JlID0gcnByb2MtPnByaXY7Cj4gKwlkZXYgPSByNV9jb3JlLT5kZXY7Cj4gKwo+ICsJLyog UmVnaXN0ZXIgYXNzb2NpYXRlZCByZXNlcnZlZCBtZW1vcnkgcmVnaW9ucyAqLwo+ICsJZm9yIChp ID0gMDsgaSA8IHI1X2NvcmUtPnJlc19tZW1fY291bnQ7IGkrKykgewo+ICsJCXJtZW0gPSAmcjVf Y29yZS0+cmVzX21lbVtpXTsKPiArCQltZW0gPSBycHJvY19tZW1fZW50cnlfaW5pdChkZXYsIE5V TEwsCj4gKwkJCQkJICAgKGRtYV9hZGRyX3Qpcm1lbS0+YmFzZSwKPiArCQkJCQkgICBybWVtLT5z aXplLCBybWVtLT5iYXNlLAo+ICsJCQkJCSAgIHp5bnFtcF9yNV9ycHJvY19tZW1fbWFwLAo+ICsJ CQkJCSAgIHp5bnFtcF9yNV9ycHJvY19tZW1fdW5tYXAsCj4gKwkJCQkJICAgcm1lbS0+bmFtZSk7 Cj4gKwkJaWYgKElTX0VSUl9PUl9OVUxMKG1lbSkpCj4gKwkJCXJldHVybiAtRU5PTUVNOwo+ICsK PiArCQlycHJvY19hZGRfY2FydmVvdXQocnByb2MsIG1lbSk7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJu IDA7Cj4gK30KPiArCj4gKy8qCj4gKyAqIHp5bnFtcF9yNV9ycHJvY19tZW1fdW5tYXAKPiArICog QHJwcm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJlc3BvbmRpbmcgcnByb2MgaW5zdGFuY2UKPiAr ICogQG1lbTogbWVtIGVudHJ5IHRvIHVubWFwCj4gKyAqCj4gKyAqIFVubWFwIFRDTSBiYW5rcyB3 aGVuIHBvd2VyaW5nIGRvd24gUjUgY29yZS4KPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vz cywgb3RoZXJ3aXNlIG5vbi16ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBp bnQgdGNtX21lbV91bm1hcChzdHJ1Y3QgcnByb2MgKnJwcm9jLCBzdHJ1Y3QgcnByb2NfbWVtX2Vu dHJ5ICptZW0pCj4gK3sKPiArCXN0cnVjdCB6eW5xbXBfcjVfY29yZSAqcjVfY29yZTsKPiArCWlu dCBpOwo+ICsJZW51bSBwbV9ub2RlX2lkIHBtX2RvbWFpbl9pZDsKPiArCj4gKwlyNV9jb3JlID0g cnByb2MtPnByaXY7Cj4gKwlpZiAoIXI1X2NvcmUpIHsKPiArCQlwcl9lcnIoInI1IGNvcmUgaXMg bm90IGF2YWlsYWJsZVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJaW91 bm1hcCgodm9pZCBfX2lvbWVtICopbWVtLT52YSk7Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8IHI1 X2NvcmUtPnRjbV9iYW5rX2NvdW50OyBpKyspIHsKPiArCQlwbV9kb21haW5faWQgPSByNV9jb3Jl LT50Y21fYmFua3NbaV0ucG1fZG9tYWluX2lkOwo+ICsJCWlmICh6eW5xbXBfcG1fcmVsZWFzZV9u b2RlKHBtX2RvbWFpbl9pZCkpCj4gKwkJCXByX3dhcm4oImNhbid0IHR1cm4gb2ZmIFRDTSBiYW5r ICVkIiwgcG1fZG9tYWluX2lkKTsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiAr LyoKPiArICogdGNtX21lbV9tYXAKPiArICogQHJwcm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJl c3BvbmRpbmcgcnByb2MgaW5zdGFuY2UKPiArICogQG1lbTogbWVtIGVudHJ5IHRvIGluaXRpYWxp emUgdGhlIHZhIGFuZCBkYSBmaWVsZHMgb2YKPiArICoKPiArICogR2l2ZW4gVENNIGJhbmsgZW50 cnksIHRoaXMgY2FsbGJhY2sgd2lsbCBzZXQgZGV2aWNlIGFkZHJlc3MgZm9yIFI1Cj4gKyAqIHJ1 bm5pbmcgb24gVENNIGFuZCBhbHNvIHNldHVwIHZpcnR1YWwgYWRkcmVzcyBmb3IgVENNIGJhbmsK PiArICogcmVtb3RlcHJvYyBjYXJ2ZW91dC4KPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vz cywgb3RoZXJ3aXNlIG5vbi16ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBp bnQgdGNtX21lbV9tYXAoc3RydWN0IHJwcm9jICpycHJvYywKPiArCQkJIHN0cnVjdCBycHJvY19t ZW1fZW50cnkgKm1lbSkKPiArewo+ICsJdm9pZCBfX2lvbWVtICp2YTsKPiArCj4gKwl2YSA9IGlv cmVtYXBfd2MobWVtLT5kbWEsIG1lbS0+bGVuKTsKPiArCWlmIChJU19FUlJfT1JfTlVMTCh2YSkp Cj4gKwkJcmV0dXJuIC1FTk9NRU07Cj4gKwo+ICsJLyogVXBkYXRlIG1lbW9yeSBlbnRyeSB2YSAq Lwo+ICsJbWVtLT52YSA9ICh2b2lkICopdmE7Cj4gKwo+ICsJLyogY2xlYXIgVENNcyAqLwo+ICsJ bWVtc2V0X2lvKHZhLCAwLCBtZW0tPmxlbik7Cj4gKwo+ICsJLyoKPiArCSAqIFRoZSBSNXMgZXhw ZWN0IHRoZWlyIFRDTSBiYW5rcyB0byBiZSBhdCBhZGRyZXNzIDB4MCBhbmQgMHgyMDAwLAo+ICsJ ICogd2hpbGUgb24gdGhlIExpbnV4IHNpZGUgdGhleSBhcmUgYXQgMHhmZmV4eHh4eC4KPiArCSAq Cj4gKwkgKiBaZXJvIG91dCB0aGUgaGlnaCAxMiBiaXRzIG9mIHRoZSBhZGRyZXNzLiBUaGlzIHdp bGwgZ2l2ZQo+ICsJICogZXhwZWN0ZWQgdmFsdWVzIGZvciBUQ00gQmFua3MgMEEgYW5kIDBCICgw eDAgYW5kIDB4MjAwMDApLgo+ICsJICovCj4gKwltZW0tPmRhICY9IDB4MDAwZmZmZmY7Cj4gKwo+ ICsJLyoKPiArCSAqIFRDTSBCYW5rcyAxQSBhbmQgMUIgc3RpbGwgaGF2ZSB0byBiZSB0cmFuc2xh dGVkLgo+ICsJICoKPiArCSAqIEJlbG93IGhhbmRsZSB0aGVzZSB0d28gYmFua3MnIGFic29sdXRl IGFkZHJlc3NlcyAoMHhmZmU5MDAwMCBhbmQKPiArCSAqIDB4ZmZlYjAwMDApIGFuZCBjb252ZXJ0 IHRvIHRoZSBleHBlY3RlZCByZWxhdGl2ZSBhZGRyZXNzZXMKPiArCSAqICgweDAgYW5kIDB4MjAw MDApLgo+ICsJICovCj4gKwlpZiAobWVtLT5kYSA9PSAweDkwMDAwIHx8IG1lbS0+ZGEgPT0gMHhC MDAwMCkKPiArCQltZW0tPmRhIC09IDB4OTAwMDA7Cj4gKwo+ICsJLyogaWYgdHJhbnNsYXRlZCBU Q00gYmFuayBhZGRyZXNzIGlzIG5vdCB2YWxpZCByZXBvcnQgZXJyb3IgKi8KPiArCWlmIChtZW0t PmRhICE9IDB4MCAmJiBtZW0tPmRhICE9IDB4MjAwMDApIHsKPiArCQlkZXZfZXJyKCZycHJvYy0+ ZGV2LCAiaW52YWxpZCBUQ00gYWRkcmVzczogJXhcbiIsIG1lbS0+ZGEpOwo+ICsJCXJldHVybiAt RUlOVkFMOwo+ICsJfQo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgYWRkX3Rj bV9jYXJ2ZW91dF9zcGxpdF9tb2RlKHN0cnVjdCBycHJvYyAqcnByb2MpCj4gK3sKPiArCWludCBp LCBudW1fYmFua3MsIHJldDsKPiArCXN0cnVjdCBycHJvY19tZW1fZW50cnkgKm1lbTsKPiArCWVu dW0gcG1fbm9kZV9pZCBwbV9kb21haW5faWQ7Cj4gKwl1MzIgYmFua19hZGRyOwo+ICsJc2l6ZV90 IGJhbmtfc2l6ZSA9IDA7Cj4gKwljaGFyICpiYW5rX25hbWU7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpk ZXY7Cj4gKwlzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKnI1X2NvcmU7Cj4gKwo+ICsJcjVfY29yZSA9 IChzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKilycHJvYy0+cHJpdjsKPiArCWlmICghcjVfY29yZSkK PiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCj4gKwlkZXYgPSByNV9jb3JlLT5kZXY7Cj4gKwo+ICsJ LyogZ28gdGhyb3VnaCB6eW5xbXAgYmFua3MgZm9yIHI1IG5vZGUgKi8KPiArCW51bV9iYW5rcyA9 IHI1X2NvcmUtPnRjbV9iYW5rX2NvdW50Owo+ICsJaWYgKG51bV9iYW5rcyA8PSAwKSB7Cj4gKwkJ ZGV2X2VycihkZXYsICJuZWVkIHRvIHNwZWNpZnkgVENNIGJhbmtzXG4iKTsKPiArCQlyZXR1cm4g LUVJTlZBTDsKPiArCX0KPiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgbnVtX2JhbmtzOyBpKyspIHsK PiArCQliYW5rX2FkZHIgPSAodTMyKXI1X2NvcmUtPnRjbV9iYW5rc1tpXS5hZGRyOwo+ICsJCWJh bmtfbmFtZSA9IHI1X2NvcmUtPnRjbV9iYW5rc1tpXS5iYW5rX25hbWU7Cj4gKwkJYmFua19zaXpl ID0gcjVfY29yZS0+dGNtX2JhbmtzW2ldLnNpemU7Cj4gKwkJcG1fZG9tYWluX2lkID0gcjVfY29y ZS0+dGNtX2JhbmtzW2ldLnBtX2RvbWFpbl9pZDsKPiArCj4gKwkJcmV0ID0genlucW1wX3BtX3Jl cXVlc3Rfbm9kZShwbV9kb21haW5faWQsCj4gKwkJCQkJICAgICBaWU5RTVBfUE1fQ0FQQUJJTElU WV9BQ0NFU1MsIDAsCj4gKwkJCQkJICAgICBaWU5RTVBfUE1fUkVRVUVTVF9BQ0tfQkxPQ0tJTkcp Owo+ICsJCWlmIChyZXQgPCAwKSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIHR1cm4g b24gVENNICVkIiwgcG1fZG9tYWluX2lkKTsKPiArCQkJcmV0dXJuIHJldDsKPiArCQl9Cj4gKwo+ ICsJCWRldl9kYmcoZGV2LCAiVENNIGNhcnZlb3V0IHNwbGl0IG1vZGUgJXMgYWRkcj0leCwgc2l6 ZT0weCVseCIsCj4gKwkJCWJhbmtfbmFtZSwgYmFua19hZGRyLCBiYW5rX3NpemUpOwo+ICsKPiAr CQkvKiBhZGQgY2FydmVvdXQgKi8KPiArCQltZW0gPSBycHJvY19tZW1fZW50cnlfaW5pdChkZXYs IE5VTEwsIGJhbmtfYWRkciwKPiArCQkJCQkgICBiYW5rX3NpemUsIGJhbmtfYWRkciwKPiArCQkJ CQkgICB0Y21fbWVtX21hcCwgdGNtX21lbV91bm1hcCwKPiArCQkJCQkgICBiYW5rX25hbWUpOwo+ ICsJCWlmIChJU19FUlJfT1JfTlVMTChtZW0pKSB7Cj4gKwkJCS8qIFR1cm4gb2ZmIGFsbCBUQ00g YmFua3MgdHVybmVkIG9uIGJlZm9yZSAqLwo+ICsJCQlkbyB7Cj4gKwkJCQlwbV9kb21haW5faWQg PSByNV9jb3JlLT50Y21fYmFua3NbaV0ucG1fZG9tYWluX2lkOwo+ICsJCQkJcmV0ID0genlucW1w X3BtX3JlbGVhc2Vfbm9kZSgodTMyKXBtX2RvbWFpbl9pZCk7Cj4gKwkJCQlpZiAocmV0KQo+ICsJ CQkJCWRldl93YXJuKGRldiwKPiArCQkJCQkJICJmYWlsIHRvIHJlbGVhc2Ugbm9kZTogJXgsICV4 XG4iLAo+ICsJCQkJCQkgKHUzMilwbV9kb21haW5faWQsIHJldCk7Cj4gKwkJCX0gd2hpbGUgKGkt LSk7Cj4gKwkJCXJldHVybiAtRU5PTUVNOwo+ICsJCX0KPiArCj4gKwkJcnByb2NfYWRkX2NhcnZl b3V0KHJwcm9jLCBtZW0pOwo+ICsJfQo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0 aWMgaW50IGFkZF90Y21fY2FydmVvdXRfbG9ja3N0ZXBfbW9kZShzdHJ1Y3QgcnByb2MgKnJwcm9j KQo+ICt7Cj4gKwlpbnQgaSwgbnVtX2JhbmtzLCByZXQ7Cj4gKwlzdHJ1Y3QgcnByb2NfbWVtX2Vu dHJ5ICptZW07Cj4gKwllbnVtIHBtX25vZGVfaWQgcG1fZG9tYWluX2lkOwo+ICsJdTMyIGJhbmtf YWRkcjsKPiArCXNpemVfdCBiYW5rX3NpemUgPSAwOwo+ICsJY2hhciAqYmFua19uYW1lOwo+ICsJ c3RydWN0IGRldmljZSAqZGV2Owo+ICsJc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGFyZW50X3Bk ZXY7Cj4gKwlzdHJ1Y3QgenlucW1wX3I1X2NsdXN0ZXIgKmNsdXN0ZXI7Cj4gKwlzdHJ1Y3Qgenlu cW1wX3I1X2NvcmUgKnI1X2NvcmU7Cj4gKwo+ICsJcjVfY29yZSA9IChzdHJ1Y3QgenlucW1wX3I1 X2NvcmUgKilycHJvYy0+cHJpdjsKPiArCWlmICghcjVfY29yZSkKPiArCQlyZXR1cm4gLUVJTlZB TDsKPiArCj4gKwlkZXYgPSByNV9jb3JlLT5kZXY7Cj4gKwlpZiAoIWRldikgewo+ICsJCXByX2Vy cigicjUgY29yZSBkZXZpY2UgdW5hdmFpbGFibGVcbiIpOwo+ICsJCXJldHVybiAtRU5PREVWOwo+ ICsJfQo+ICsKPiArCS8qIGdvIHRocm91Z2ggenlucW1wIGJhbmtzIGZvciByNSBub2RlICovCj4g KwludW1fYmFua3MgPSByNV9jb3JlLT50Y21fYmFua19jb3VudDsKPiArCWlmIChudW1fYmFua3Mg PD0gMCkgewo+ICsJCWRldl9lcnIoZGV2LCAibmVlZCB0byBzcGVjaWZ5IFRDTSBiYW5rc1xuIik7 Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJYmFua19hZGRyID0gKHUzMilyNV9j b3JlLT50Y21fYmFua3NbMF0uYWRkcjsKPiArCWJhbmtfbmFtZSA9IHI1X2NvcmUtPnRjbV9iYW5r c1swXS5iYW5rX25hbWU7Cj4gKwlmb3IgKGkgPSAwOyBpIDwgbnVtX2JhbmtzOyBpKyspIHsKPiAr CQliYW5rX3NpemUgKz0gcjVfY29yZS0+dGNtX2JhbmtzW2ldLnNpemU7Cj4gKwkJcG1fZG9tYWlu X2lkID0gcjVfY29yZS0+dGNtX2JhbmtzW2ldLnBtX2RvbWFpbl9pZDsKPiArCj4gKwkJcmV0ID0g enlucW1wX3BtX3JlcXVlc3Rfbm9kZShwbV9kb21haW5faWQsCj4gKwkJCQkJICAgICBaWU5RTVBf UE1fQ0FQQUJJTElUWV9BQ0NFU1MsIDAsCj4gKwkJCQkJICAgICBaWU5RTVBfUE1fUkVRVUVTVF9B Q0tfQkxPQ0tJTkcpOwo+ICsJCWlmIChyZXQgPCAwKSB7Cj4gKwkJCWRldl9lcnIoZGV2LCAiZmFp bGVkIHRvIHR1cm4gb24gVENNICVkIiwgcG1fZG9tYWluX2lkKTsKPiArCQkJcmV0dXJuIHJldDsK PiArCQl9Cj4gKwl9Cj4gKwo+ICsJZGV2X2RiZyhkZXYsICJUQ00gYWRkIGNhcnZlb3V0IGxvY2tz dGVwIG1vZGUgJXMgYWRkcj0weCV4LCBzaXplPTB4JWx4IiwKPiArCQliYW5rX25hbWUsIGJhbmtf YWRkciwgYmFua19zaXplKTsKPiArCj4gKwkvKiBhZGQgY2FydmVvdXQgKi8KPiArCW1lbSA9IHJw cm9jX21lbV9lbnRyeV9pbml0KGRldiwgTlVMTCwgYmFua19hZGRyLAo+ICsJCQkJICAgYmFua19z aXplLCBiYW5rX2FkZHIsCj4gKwkJCQkgICB0Y21fbWVtX21hcCwgdGNtX21lbV91bm1hcCwKPiAr CQkJCSAgIGJhbmtfbmFtZSk7Cj4gKwlpZiAoSVNfRVJSX09SX05VTEwobWVtKSkgewo+ICsJCWZv ciAoaSA9IDA7IGkgPCBudW1fYmFua3M7IGkrKykgewo+ICsJCQlwbV9kb21haW5faWQgPSByNV9j b3JlLT50Y21fYmFua3NbaV0ucG1fZG9tYWluX2lkOwo+ICsJCQlyZXQgPSB6eW5xbXBfcG1fcmVs ZWFzZV9ub2RlKCh1MzIpcG1fZG9tYWluX2lkKTsKPiArCQkJaWYgKHJldCkKPiArCQkJCWRldl93 YXJuKGRldiwKPiArCQkJCQkgImZhaWwgdG8gcmVsZWFzZSBub2RlOiAleCByZXQ6ICV4XG4iLAo+ ICsJCQkJCSAodTMyKXBtX2RvbWFpbl9pZCwgcmV0KTsKPiArCQl9Cj4gKwkJcmV0dXJuIC1FTk9N RU07Cj4gKwl9Cj4gKwo+ICsJcnByb2NfYWRkX2NhcnZlb3V0KHJwcm9jLCBtZW0pOwo+ICsKPiAr CXJldHVybiAwOwo+ICt9Cj4gKwo+ICsvKgo+ICsgKiBhZGRfdGNtX2JhbmtzKCkKPiArICogQHJw cm9jOiBzaW5nbGUgUjUgY29yZSdzIGNvcnJlc3BvbmRpbmcgcnByb2MgaW5zdGFuY2UKPiArICoK PiArICogR2l2ZW4gUjUgbm9kZSBpbiByZW1vdGVwcm9jIGluc3RhbmNlCj4gKyAqIGFsbG9jYXRl IHJlbW90ZXByb2MgY2FydmVvdXQgZm9yIFRDTSBtZW1vcnkKPiArICogbmVlZGVkIGZvciBmaXJt d2FyZSB0byBiZSBsb2FkZWQKPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vzcywgb3RoZXJ3 aXNlIG5vbi16ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBpbnQgYWRkX3Rj bV9iYW5rcyhzdHJ1Y3QgcnByb2MgKnJwcm9jKQo+ICt7Cj4gKwlzdHJ1Y3QgZGV2aWNlICpkZXY7 Cj4gKwlzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwYXJlbnRfcGRldjsKPiArCXN0cnVjdCB6eW5x bXBfcjVfY2x1c3RlciAqY2x1c3RlcjsKPiArCXN0cnVjdCB6eW5xbXBfcjVfY29yZSAqcjVfY29y ZTsKPiArCj4gKwlyNV9jb3JlID0gKHN0cnVjdCB6eW5xbXBfcjVfY29yZSAqKXJwcm9jLT5wcml2 Owo+ICsJaWYgKCFyNV9jb3JlKQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiArCWRldiA9IHI1 X2NvcmUtPmRldjsKPiArCWlmICghZGV2KSB7Cj4gKwkJcHJfZXJyKCJyNSBjb3JlIGRldmljZSB1 bmF2YWlsYWJsZVxuIik7Cj4gKwkJcmV0dXJuIC1FTk9ERVY7Cj4gKwl9Cj4gKwo+ICsJcGFyZW50 X3BkZXYgPSB0b19wbGF0Zm9ybV9kZXZpY2UoZGV2LT5wYXJlbnQpOwo+ICsJaWYgKCFwYXJlbnRf cGRldikgewo+ICsJCWRldl9lcnIoZGV2LCAicGFyZW50IHBsYXRmb3JtIGRldiB1bmF2YWlsYWJs ZVxuIik7Cj4gKwkJcmV0dXJuIC1FTk9ERVY7Cj4gKwl9Cj4gKwo+ICsJY2x1c3RlciA9IHBsYXRm b3JtX2dldF9kcnZkYXRhKHBhcmVudF9wZGV2KTsKPiArCWlmICghY2x1c3Rlcikgewo+ICsJCWRl dl9lcnIoJnBhcmVudF9wZGV2LT5kZXYsICJJbnZhbGlkIGRyaXZlciBkYXRhXG4iKTsKPiArCQly ZXR1cm4gLUVJTlZBTDsKPiArCX0KPiArCj4gKwlpZiAoY2x1c3Rlci0+bW9kZSA9PSBTUExJVF9N T0RFKQo+ICsJCXJldHVybiBhZGRfdGNtX2NhcnZlb3V0X3NwbGl0X21vZGUocnByb2MpOwo+ICsJ ZWxzZSBpZiAoY2x1c3Rlci0+bW9kZSA9PSBMT0NLU1RFUF9NT0RFKQo+ICsJCXJldHVybiBhZGRf dGNtX2NhcnZlb3V0X2xvY2tzdGVwX21vZGUocnByb2MpOwo+ICsKPiArCWRldl9lcnIoY2x1c3Rl ci0+ZGV2LCAiaW52YWxpZCBjbHVzdGVyIG1vZGVcbiIpOwo+ICsJcmV0dXJuIC1FSU5WQUw7Cj4g K30KPiArCj4gKy8qCj4gKyAqIHp5bnFtcF9yNV9wYXJzZV9mdygpCj4gKyAqIEBycHJvYzogc2lu Z2xlIFI1IGNvcmUncyBjb3JyZXNwb25kaW5nIHJwcm9jIGluc3RhbmNlCj4gKyAqIEBmdzogcHRy IHRvIGZpcm13YXJlIHRvIGJlIGxvYWRlZCBvbnRvIHI1IGNvcmUKPiArICoKPiArICogV2hlbiBs b2FkaW5nIGZpcm13YXJlLCBlbnN1cmUgdGhlIG5lY2Vzc2FyeSBjYXJ2ZW91dHMgYXJlIGluIHJl bW90ZXByb2MKPiArICoKPiArICogcmV0dXJuIDAgb24gc3VjY2Vzcywgb3RoZXJ3aXNlIG5vbi16 ZXJvIHZhbHVlIG9uIGZhaWx1cmUKPiArICovCj4gK3N0YXRpYyBpbnQgenlucW1wX3I1X3BhcnNl X2Z3KHN0cnVjdCBycHJvYyAqcnByb2MsIGNvbnN0IHN0cnVjdCBmaXJtd2FyZSAqZncpCj4gK3sK PiArCWludCByZXQ7Cj4gKwlzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKnI1X2NvcmU7Cj4gKwlzdHJ1 Y3QgZGV2aWNlICpkZXY7Cj4gKwo+ICsJcjVfY29yZSA9IHJwcm9jLT5wcml2Owo+ICsJaWYgKCFy NV9jb3JlKSB7Cj4gKwkJZGV2X2VycigmcnByb2MtPmRldiwgInI1IGNvcmUgbm90IGF2YWlsYWJs ZVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJZGV2ID0gcjVfY29yZS0+ ZGV2Owo+ICsKPiArCXJldCA9IGFkZF90Y21fYmFua3MocnByb2MpOwo+ICsJaWYgKHJldCkgewo+ ICsJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGdldCBUQ00gYmFua3MsIGVyciAlZFxuIiwgcmV0 KTsKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCXJldCA9IGFkZF9tZW1fcmVnaW9ucyhy cHJvYyk7Cj4gKwlpZiAocmV0KQo+ICsJCWRldl93YXJuKGRldiwgImZhaWxlZCB0byBnZXQgcmVz ZXJ2ZSBtZW0gcmVnaW9ucyAlZFxuIiwgcmV0KTsKPiArCj4gKwlyZXQgPSBycHJvY19lbGZfbG9h ZF9yc2NfdGFibGUocnByb2MsIGZ3KTsKPiArCWlmIChyZXQgPT0gLUVJTlZBTCkgewo+ICsJCS8q Cj4gKwkJICogcmVzb3VyY2UgdGFibGUgb25seSByZXF1aXJlZCBmb3IgSVBDLgo+ICsJCSAqIGlm IG5vdCBwcmVzZW50LCB0aGlzIGlzIG5vdCBuZWNlc3NhcmlseSBhbiBlcnJvcjsKPiArCQkgKiBm b3IgZXhhbXBsZSwgbG9hZGluZyByNSBoZWxsbyB3b3JsZCBhcHBsaWNhdGlvbgo+ICsJCSAqIHNv IHNpbXBseSBpbmZvcm0gdXNlciBhbmQga2VlcCBnb2luZy4KPiArCQkgKi8KPiArCQlkZXZfaW5m bygmcnByb2MtPmRldiwgIm5vIHJlc291cmNlIHRhYmxlIGZvdW5kLlxuIik7Cj4gKwkJcmV0ID0g MDsKPiArCX0KPiArCXJldHVybiByZXQ7Cj4gK30KPiArCj4gK3N0YXRpYyBzdHJ1Y3QgcnByb2Nf b3BzIHp5bnFtcF9yNV9ycHJvY19vcHMgPSB7Cj4gKwkuc3RhcnQJCT0genlucW1wX3I1X3Jwcm9j X3N0YXJ0LAo+ICsJLnN0b3AJCT0genlucW1wX3I1X3Jwcm9jX3N0b3AsCj4gKwkubG9hZAkJPSBy cHJvY19lbGZfbG9hZF9zZWdtZW50cywKPiArCS5wYXJzZV9mdwk9IHp5bnFtcF9yNV9wYXJzZV9m dywKPiArCS5maW5kX2xvYWRlZF9yc2NfdGFibGUgPSBycHJvY19lbGZfZmluZF9sb2FkZWRfcnNj X3RhYmxlLAo+ICsJLnNhbml0eV9jaGVjawk9IHJwcm9jX2VsZl9zYW5pdHlfY2hlY2ssCj4gKwku Z2V0X2Jvb3RfYWRkcgk9IHJwcm9jX2VsZl9nZXRfYm9vdF9hZGRyLAo+ICt9Owo+ICsKPiArc3Rh dGljIHZvaWQgenlucW1wX3I1X3ByaW50X2R0X25vZGVfaW5mbyhzdHJ1Y3QgenlucW1wX3I1X2Ns dXN0ZXIgKmNsdXN0ZXIpCj4gK3sKPiArCWludCBpLCBqLCBrOwo+ICsJc3RydWN0IHp5bnFtcF9y NV9jb3JlICpyNV9jb3JlOwo+ICsKPiArCWRldl9kYmcoY2x1c3Rlci0+ZGV2LCAiUHJpbnRpbmcg ZHQgbm9kZSBpbmZvXG4iKTsKPiArCj4gKwlwcl9kZWJ1ZygiY2x1c3RlciBtb2RlID0gJWRcbiIs IGNsdXN0ZXItPm1vZGUpOwo+ICsJcHJfZGVidWcoInI1ZiBjbHVzdGVyIGluICVzIG1vZGVcbiIs IChjbHVzdGVyLT5tb2RlID09IDApID8gIlNQTElUIiA6Cj4gKwkJIGNsdXN0ZXItPm1vZGUgPT0g MSA/ICJMT0NLU1RFUCIgOiAiU0lOR0xFX0NQVSIpOwo+ICsJcHJfZGVidWcoInI1ZiBudW0gY29y ZXMgPSAlZFxuIiwgY2x1c3Rlci0+Y29yZV9jb3VudCk7Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8 IGNsdXN0ZXItPmNvcmVfY291bnQ7IGkrKykgewo+ICsJCXI1X2NvcmUgPSAmY2x1c3Rlci0+cjVf Y29yZXNbaV07Cj4gKwkJaWYgKCFyNV9jb3JlKSB7Cj4gKwkJCXByX2VycigiY2FuJ3QgZ2V0IHI1 X2NvcmVcbiIpOwo+ICsJCQljb250aW51ZTsKPiArCQl9Cj4gKwo+ICsJCXByX2RlYnVnKCJyNSBj b3JlICVkIG5vZGVzXG4iLCBpKTsKPiArCQlwcl9kZWJ1ZygiVENNIGJhbmtzID0gJWRcbiIsIHI1 X2NvcmUtPnRjbV9iYW5rX2NvdW50KTsKPiArCQlmb3IgKGsgPSAwOyBrIDwgcjVfY29yZS0+dGNt X2JhbmtfY291bnQ7IGsrKykgewo+ICsJCQlwcl9kZWJ1ZygidGNtICVkIGFkZHI9MHglbGx4IHNp emU9MHglbHgsIHBtX2lkPSVkLCAlc1xuIiwKPiArCQkJCSBrLCByNV9jb3JlLT50Y21fYmFua3Nb a10uYWRkciwKPiArCQkJCSByNV9jb3JlLT50Y21fYmFua3Nba10uc2l6ZSwKPiArCQkJCSByNV9j b3JlLT50Y21fYmFua3Nba10ucG1fZG9tYWluX2lkLAo+ICsJCQkJIHI1X2NvcmUtPnRjbV9iYW5r c1trXS5iYW5rX25hbWUpOwo+ICsJCX0KPiArCj4gKwkJcHJfZGVidWcoInJlc2VydmUgbWVtIHJl Z2lvbnMgPSAlZFxuIiwgcjVfY29yZS0+cmVzX21lbV9jb3VudCk7Cj4gKwo+ICsJCWZvciAoaiA9 IDA7IGogPCByNV9jb3JlLT5yZXNfbWVtX2NvdW50OyBqKyspIHsKPiArCQkJcHJfZGVidWcoIm1l bSAlZCBhZGRyPTB4JWxseCwgc2l6ZT0weCVsbHgsIG5hbWU9JXNcbiIsCj4gKwkJCQkgaiwgcjVf Y29yZS0+cmVzX21lbVtqXS5iYXNlLAo+ICsJCQkJIHI1X2NvcmUtPnJlc19tZW1bal0uc2l6ZSwK PiArCQkJCSByNV9jb3JlLT5yZXNfbWVtW2pdLm5hbWUpOwo+ICsJCX0KPiArCX0KPiArfQo+ICsK PiArLyoqCj4gKyAqIHp5bnFtcF9yNV9hZGRfcnByb2NfY29yZSgpIC0gUHJvYmVzIFp5bnFNUCBS NSBwcm9jZXNzb3IgZGV2aWNlIG5vZGUKPiArICoJCSAgICAgICB0aGlzIGlzIGNhbGxlZCBmb3Ig ZWFjaCBpbmRpdmlkdWFsIFI1IGNvcmUgdG8KPiArICoJCSAgICAgICBzZXQgdXAgbWFpbGJveCwg WGlsaW54IHBsYXRmb3JtIG1hbmFnZXIgdW5pcXVlIElELAo+ICsgKgkJICAgICAgIGFkZCB0byBy cHJvYyBjb3JlCj4gKyAqCj4gKyAqIEByNV9jb3JlOiB6eW5xbXBfcjVfY29yZSByNSBjb3JlIG9i amVjdCB0byBpbml0aWFsaXplCj4gKyAqCj4gKyAqIFJldHVybjogMCBmb3Igc3VjY2VzcywgbmVn YXRpdmUgdmFsdWUgZm9yIGZhaWx1cmUuCj4gKyAqLwo+ICtzdGF0aWMgaW50IHp5bnFtcF9yNV9h ZGRfcnByb2NfY29yZShzdHJ1Y3QgenlucW1wX3I1X2NvcmUgKnI1X2NvcmUpCj4gK3sKPiArCWlu dCByZXQ7Cj4gKwlzdHJ1Y3QgcnByb2MgKnI1X3Jwcm9jOwo+ICsJc3RydWN0IGRldmljZSAqZGV2 Owo+ICsKPiArCWRldiA9IHI1X2NvcmUtPmRldjsKPiArCj4gKwkvKiBTZXQgdXAgRE1BIG1hc2sg Ki8KPiArCXJldCA9IGRtYV9zZXRfY29oZXJlbnRfbWFzayhkZXYsIERNQV9CSVRfTUFTSygzMikp Owo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4gcmV0Owo+ICsKPiArCS8qIEFsbG9jYXRlIHJlbW90 ZXByb2MgaW5zdGFuY2UgKi8KPiArCXI1X3Jwcm9jID0gZGV2bV9ycHJvY19hbGxvYyhkZXYsIGRl dl9uYW1lKGRldiksICZ6eW5xbXBfcjVfcnByb2Nfb3BzLAo+ICsJCQkJICAgIE5VTEwsIHNpemVv ZihzdHJ1Y3QgenlucW1wX3I1X2NvcmUpKTsKPiArCWlmIChJU19FUlJfT1JfTlVMTChyNV9ycHJv YykpCj4gKwkJcmV0dXJuIC1FTk9NRU07Cj4gKwo+ICsJcjVfcnByb2MtPmF1dG9fYm9vdCA9IGZh bHNlOwo+ICsJcjVfcnByb2MtPnByaXYgPSByNV9jb3JlOwo+ICsKPiArCS8qIEFkZCBSNSByZW1v dGVwcm9jICovCj4gKwlyZXQgPSBkZXZtX3Jwcm9jX2FkZChkZXYsIHI1X3Jwcm9jKTsKPiArCWlm IChyZXQpIHsKPiArCQlwcl9lcnIoImZhaWxlZCB0byBhZGQgcjUgcmVtb3RlcHJvY1xuIik7Cj4g KwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGlj IGludCB6eW5xbXBfcjVfZ2V0X3RjbV9ub2RlKHN0cnVjdCB6eW5xbXBfcjVfY2x1c3RlciAqY2x1 c3RlcikKPiArewo+ICsJaW50IHRjbV9iYW5rX2NvdW50LCB0Y21fbm9kZTsKPiArCWludCBpID0g MCwgajsKPiArCXN0cnVjdCB6eW5xbXBfcjVfY29yZSAqcjVfY29yZTsKPiArCWNvbnN0IHN0cnVj dCBtZW1fYmFua19kYXRhICp0Y20gPSB6eW5xbXBfdGNtX2JhbmtzOwo+ICsJc3RydWN0IGRldmlj ZSAqZGV2ID0gY2x1c3Rlci0+ZGV2Owo+ICsKPiArCS8qIFRvRG86IFVzZSBwcmVkZWZpbmVkIFRD TSBhZGRyZXNzIHNwYWNlIHZhbHVlcyBmcm9tIGRyaXZlciB1bnRpbAo+ICsJICogc3lzdGVtLWR0 IHNwZWMgaXMgbm90IGZpbmFsIGZvdCBUQ00KPiArCSAqLwo+ICsJdGNtX2JhbmtfY291bnQgPSBB UlJBWV9TSVpFKHp5bnFtcF90Y21fYmFua3MpOwo+ICsKPiArCS8qIGNvdW50IHBlciBjb3JlIHRj bSBiYW5rcyAqLwo+ICsJdGNtX2JhbmtfY291bnQgPSB0Y21fYmFua19jb3VudCAvIGNsdXN0ZXIt PmNvcmVfY291bnQ7Cj4gKwo+ICsJLyogcjUgY29yZSAwIHdpbGwgdXNlIGFsbCBvZiBUQ00gYmFu a3MgaW4gbG9ja3N0ZXAgbW9kZS4KPiArCSAqIEluIHNwbGl0IG1vZGUsIHI1IGNvcmUwIHdpbGwg dXNlIDEyOGsgYW5kIHI1IGNvcmUxIHdpbGwgdXNlIGFub3RoZXIKPiArCSAqIDEyOGsuIEFzc2ln biBUQ00gYmFua3MgdG8gZWFjaCBjb3JlIGFjY29yZGluZ2x5Cj4gKwkgKi8KPiArCXRjbV9ub2Rl ID0gMDsKPiArCWZvciAoaiA9IDA7IGogPCBjbHVzdGVyLT5jb3JlX2NvdW50OyBqKyspIHsKPiAr CQlyNV9jb3JlID0gJmNsdXN0ZXItPnI1X2NvcmVzW2pdOwo+ICsJCXI1X2NvcmUtPnRjbV9iYW5r cyA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZihzdHJ1Y3QgbWVtX2JhbmtfZGF0YSkgKgo+ICsJ CQkJCQkgIHRjbV9iYW5rX2NvdW50LCBHRlBfS0VSTkVMKTsKPiArCQlpZiAoSVNfRVJSX09SX05V TEwocjVfY29yZS0+dGNtX2JhbmtzKSkKPiArCQkJcmV0dXJuIC1FTk9NRU07Cj4gKwo+ICsJCWZv ciAoaSA9IDA7IGkgPCB0Y21fYmFua19jb3VudDsgaSsrKSB7Cj4gKwkJCS8qIFVzZSBwcmUtZGVm aW5lZCBUQ00gcmVnIHZhbHVlcy4KPiArCQkJICogRXZlbnR1YWxseSB0aGlzIHNob3VsZCBiZSBy ZXBsYWNlZCBieSB2YWx1ZXMKPiArCQkJICogcGFyc2VkIGZyb20gZHRzLgo+ICsJCQkgKi8KPiAr CQkJcjVfY29yZS0+dGNtX2JhbmtzW2ldLmFkZHIgPSB0Y21bdGNtX25vZGVdLmFkZHI7Cj4gKwkJ CXI1X2NvcmUtPnRjbV9iYW5rc1tpXS5zaXplID0gdGNtW3RjbV9ub2RlXS5zaXplOwo+ICsJCQly NV9jb3JlLT50Y21fYmFua3NbaV0ucG1fZG9tYWluX2lkID0gdGNtW3RjbV9ub2RlXS5wbV9kb21h aW5faWQ7Cj4gKwkJCXI1X2NvcmUtPnRjbV9iYW5rc1tpXS5iYW5rX25hbWUgPSB0Y21bdGNtX25v ZGVdLmJhbmtfbmFtZTsKPiArCQkJdGNtX25vZGUrKzsKPiArCQl9Cj4gKwo+ICsJCXI1X2NvcmUt PnRjbV9iYW5rX2NvdW50ID0gdGNtX2JhbmtfY291bnQ7Cj4gKwl9Cj4gKwo+ICsJcmV0dXJuIDA7 Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgenlucW1wX3I1X2dldF9tZW1fcmVnaW9uX25vZGUoc3Ry dWN0IHp5bnFtcF9yNV9jb3JlICpyNV9jb3JlKQo+ICt7Cj4gKwlpbnQgcmVzX21lbV9jb3VudCwg aTsKPiArCXN0cnVjdCBkZXZpY2UgKmRldjsKPiArCXN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAsICpy bWVtX25wOwo+ICsJc3RydWN0IHJlc2VydmVkX21lbSAqcm1lbTsKPiArCj4gKwlkZXYgPSByNV9j b3JlLT5kZXY7Cj4gKwo+ICsJbnAgPSByNV9jb3JlLT5ucDsKPiArCWlmIChJU19FUlJfT1JfTlVM TChucCkpIHsKPiArCQlwcl9lcnIoImludmFsaWQgZGV2aWNlIG5vZGUgb2YgcjUgY29yZVxuIik7 Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJcmVzX21lbV9jb3VudCA9IG9mX3By b3BlcnR5X2NvdW50X2VsZW1zX29mX3NpemUobnAsICJtZW1vcnktcmVnaW9uIiwKPiArCQkJCQkJ CXNpemVvZihwaGFuZGxlKSk7Cj4gKwlpZiAocmVzX21lbV9jb3VudCA8PSAwKSB7Cj4gKwkJZGV2 X3dhcm4oZGV2LCAiZmFpbGVkIHRvIGdldCBtZW1vcnktcmVnaW9uIHByb3BlcnR5ICVkXG4iLAo+ ICsJCQkgcmVzX21lbV9jb3VudCk7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJ cjVfY29yZS0+cmVzX21lbSA9IGRldm1fa3phbGxvYyhkZXYsCj4gKwkJCQkJcmVzX21lbV9jb3Vu dCAqIHNpemVvZihzdHJ1Y3QgcmVzZXJ2ZWRfbWVtKSwKPiArCQkJCQlHRlBfS0VSTkVMKTsKPiAr CWlmICghcjVfY29yZS0+cmVzX21lbSkgewo+ICsJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGFs bG9jYXRlIG1lbSByZWdpb24gbWVtb3J5XG4iKTsKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCX0K PiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgcmVzX21lbV9jb3VudDsgaSsrKSB7Cj4gKwkJcm1lbV9u cCA9IG9mX3BhcnNlX3BoYW5kbGUobnAsICJtZW1vcnktcmVnaW9uIiwgaSk7Cj4gKwkJaWYgKCFy bWVtX25wKQo+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiArCj4gKwkJcm1lbSA9IG9mX3Jlc2VydmVk X21lbV9sb29rdXAocm1lbV9ucCk7Cj4gKwkJaWYgKCFybWVtKSB7Cj4gKwkJCW9mX25vZGVfcHV0 KHJtZW1fbnApOwo+ICsJCQlyZXR1cm4gLUVJTlZBTDsKPiArCQl9Cj4gKwo+ICsJCW1lbWNweSgm cjVfY29yZS0+cmVzX21lbVtpXSwgcm1lbSwKPiArCQkgICAgICAgc2l6ZW9mKHN0cnVjdCByZXNl cnZlZF9tZW0pKTsKPiArCQlvZl9ub2RlX3B1dChybWVtX25wKTsKPiArCX0KPiArCj4gKwlyNV9j b3JlLT5yZXNfbWVtX2NvdW50ID0gcmVzX21lbV9jb3VudDsKPiArCj4gKwlyZXR1cm4gMDsKPiAr fQo+ICsKPiArc3RhdGljIGludCB6eW5xbXBfcjVfY29yZV9pbml0KHN0cnVjdCB6eW5xbXBfcjVf Y2x1c3RlciAqY2x1c3RlcikKPiArewo+ICsJaW50IHJldCwgaTsKPiArCXN0cnVjdCB6eW5xbXBf cjVfY29yZSAqcjVfY29yZTsKPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IGNsdXN0ZXItPmRldjsK PiArCj4gKwlyZXQgPSB6eW5xbXBfcjVfZ2V0X3RjbV9ub2RlKGNsdXN0ZXIpOwo+ICsJaWYgKHJl dCA8IDApIHsKPiArCQlkZXZfZXJyKGRldiwgImNhbid0IGdldCB0Y20gbm9kZSwgZXJyICVkXG4i LCByZXQpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJZm9yIChpID0gMDsgaSA8IGNs dXN0ZXItPmNvcmVfY291bnQ7IGkrKykgewo+ICsJCXI1X2NvcmUgPSAmY2x1c3Rlci0+cjVfY29y ZXNbaV07Cj4gKwkJaWYgKCFyNV9jb3JlKSB7Cj4gKwkJCXByX2VycigiaW52YWxpZCByNSBjb3Jl XG4iKTsKPiArCQkJcmV0dXJuIC1FSU5WQUw7Cj4gKwkJfQo+ICsKPiArCQlyZXQgPSB6eW5xbXBf cjVfZ2V0X21lbV9yZWdpb25fbm9kZShyNV9jb3JlKTsKPiArCQlpZiAocmV0KQo+ICsJCQlkZXZf d2FybihkZXYsICJtZW1vcnktcmVnaW9uIHByb3AgZmFpbGVkICVkXG4iLCByZXQpOwo+ICsKPiAr CQlyZXQgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMl9pbmRleChyNV9jb3JlLT5ucCwgInBvd2VyLWRv bWFpbnMiLAo+ICsJCQkJCQkgMSwgJnI1X2NvcmUtPnBtX2RvbWFpbl9pZCk7Cj4gKwkJaWYgKHJl dCkgewo+ICsJCQlkZXZfZXJyKGRldiwgImZhaWxlZCB0byBnZXQgcG93ZXItZG9tYWlucyBwcm9w ZXJ0eVxuIik7Cj4gKwkJCXJldHVybiByZXQ7Cj4gKwkJfQo+ICsKPiArCQlyZXQgPSB6eW5xbXBf cjVfc2V0X21vZGUocjVfY29yZSwgY2x1c3Rlci0+bW9kZSk7Cj4gKwkJaWYgKHJldCkKPiArCQkJ cmV0dXJuIHJldDsKPiArCj4gKwkJcmV0ID0genlucW1wX3I1X2FkZF9ycHJvY19jb3JlKHI1X2Nv cmUpOwo+ICsJCWlmIChyZXQpIHsKPiArCQkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gaW5pdCBy NSBjb3JlICVkXG4iLCBpKTsKPiArCQkJcmV0dXJuIHJldDsKPiArCQl9Cj4gKwl9Cj4gKwo+ICsJ cmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgenlucW1wX3I1X2NsdXN0ZXJfaW5pdChz dHJ1Y3QgenlucW1wX3I1X2NsdXN0ZXIgKmNsdXN0ZXIpCj4gK3sKPiArCXN0cnVjdCBkZXZpY2Ug KmRldiA9IGNsdXN0ZXItPmRldjsKPiArCXN0cnVjdCBkZXZpY2Vfbm9kZSAqZGV2X25vZGUgPSBk ZXZfb2Zfbm9kZShkZXYpOwo+ICsJc3RydWN0IGRldmljZV9ub2RlICpjaGlsZDsKPiArCXN0cnVj dCBwbGF0Zm9ybV9kZXZpY2UgKmNoaWxkX3BkZXY7Cj4gKwlpbnQgY29yZV9jb3VudCA9IDAsIHJl dCwgaTsKPiArCWVudW0genlucW1wX3I1X2NsdXN0ZXJfbW9kZSBjbHVzdGVyX21vZGUgPSBMT0NL U1RFUF9NT0RFOwo+ICsJc3RydWN0IHp5bnFtcF9yNV9jb3JlICpyNV9jb3JlczsKPiArCj4gKwly ZXQgPSBvZl9wcm9wZXJ0eV9yZWFkX3UzMihkZXZfbm9kZSwgInhsbngsY2x1c3Rlci1tb2RlIiwg JmNsdXN0ZXJfbW9kZSk7Cj4gKwo+ICsJLyogb24gc3VjY2VzcyByZXR1cm5zIDAsIGlmIG5vdCBk ZWZpbmVkIHRoZW4gcmV0dXJucyAtRUlOVkFMLAo+ICsJICogSW4gdGhhdCBjYXNlLCBkZWZhdWx0 IGlzIExPQ0tTVEVQIG1vZGUKPiArCSAqLwo+ICsJaWYgKHJldCAhPSAtRUlOVkFMICYmIHJldCAh PSAwKSB7Cj4gKwkJZGV2X2VycihkZXYsICJJbnZhbGlkIHhsbngsY2x1c3Rlci1tb2RlIHByb3Bl cnR5XG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KPiArCj4gKwlpZiAoY2x1c3Rlcl9t b2RlID09IFNJTkdMRV9DUFVfTU9ERSkgewo+ICsJCWRldl9lcnIoZGV2LCAiZHJpdmVyIGRvZXMg bm90IHN1cHBvcnQgc2luZ2xlIGNwdSBtb2RlXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiAr CX0gZWxzZSBpZiAoKGNsdXN0ZXJfbW9kZSAhPSBTUExJVF9NT0RFICYmCj4gKwkJICAgY2x1c3Rl cl9tb2RlICE9IExPQ0tTVEVQX01PREUpKSB7Cj4gKwkJZGV2X2VycihkZXYsICJJbnZhbGlkIGNs dXN0ZXIgbW9kZVxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICsJY29yZV9j b3VudCA9IG9mX2dldF9hdmFpbGFibGVfY2hpbGRfY291bnQoZGV2X25vZGUpOwo+ICsJaWYgKGNv cmVfY291bnQgPD0gMCkgewo+ICsJCWRldl9lcnIoZGV2LCAiSW52YWxpZCBudW1iZXIgb2YgcjUg Y29yZXMgJWQiLCBjb3JlX2NvdW50KTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0gZWxzZSBp ZiAoY2x1c3Rlcl9tb2RlID09IFNQTElUX01PREUgJiYgY29yZV9jb3VudCAhPSAyKSB7Cj4gKwkJ ZGV2X2VycihkZXYsICJJbnZhbGlkIG51bWJlciBvZiByNSBjb3JlcyBmb3Igc3BsaXQgbW9kZVxu Iik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9IGVsc2UgaWYgKGNsdXN0ZXJfbW9kZSA9PSBM T0NLU1RFUF9NT0RFICYmIGNvcmVfY291bnQgPT0gMikgewo+ICsJCWRldl93YXJuKGRldiwgIk9u bHkgcjUgY29yZTAgd2lsbCBiZSB1c2VkXG4iKTsKPiArCQljb3JlX2NvdW50ID0gMTsKPiArCX0K PiArCj4gKwlyNV9jb3JlcyA9IGRldm1fa3phbGxvYyhkZXYsIHNpemVvZihzdHJ1Y3QgenlucW1w X3I1X2NvcmUpICoKPiArCQkJCQkJIGNvcmVfY291bnQsIEdGUF9LRVJORUwpOwo+ICsJaWYgKElT X0VSUl9PUl9OVUxMKHI1X2NvcmVzKSkgewo+ICsJCWRldl9lcnIoZGV2LCAiY2FuJ3QgYWxsb2Nh dGUgbWVtb3J5IGZvciBjb3Jlc1xuIik7Cj4gKwkJcmV0dXJuIC1FTk9NRU07Cj4gKwl9Cj4gKwo+ ICsJaSA9IDA7Cj4gKwlmb3JfZWFjaF9hdmFpbGFibGVfY2hpbGRfb2Zfbm9kZShkZXZfbm9kZSwg Y2hpbGQpIHsKPiArCQljaGlsZF9wZGV2ID0gb2ZfZmluZF9kZXZpY2VfYnlfbm9kZShjaGlsZCk7 Cj4gKwkJaWYgKCFjaGlsZF9wZGV2KQo+ICsJCQlyZXR1cm4gLUVOT0RFVjsKPiArCj4gKwkJcjVf Y29yZXNbaV0uZGV2ID0gJmNoaWxkX3BkZXYtPmRldjsKPiArCQlpZiAoIXI1X2NvcmVzW2ldLmRl dikgewo+ICsJCQlwcl9lcnIoImNhbid0IGdldCBkZXZpY2UgZm9yIHI1IGNvcmUgJWRcbiIsIGkp Owo+ICsJCQlyZXR1cm4gLUVOT0RFVjsKPiArCQl9Cj4gKwo+ICsJCXI1X2NvcmVzW2ldLm5wID0g ZGV2X29mX25vZGUocjVfY29yZXNbaV0uZGV2KTsKPiArCQlpZiAoIXI1X2NvcmVzW2ldLm5wKSB7 Cj4gKwkJCXByX2VycigiY2FuJ3QgZ2V0IGRldmljZSBub2RlIGZvciByNSBjb3JlICVkXG4iLCBp KTsKPiArCQkJcmV0dXJuIC1FTk9ERVY7Cj4gKwkJfQo+ICsKPiArCQlpKys7Cj4gKwkJaWYgKGkg PT0gY29yZV9jb3VudCkKPiArCQkJYnJlYWs7Cj4gKwl9Cj4gKwo+ICsJY2x1c3Rlci0+bW9kZSA9 IGNsdXN0ZXJfbW9kZTsKPiArCWNsdXN0ZXItPmNvcmVfY291bnQgPSBjb3JlX2NvdW50Owo+ICsJ Y2x1c3Rlci0+cjVfY29yZXMgPSByNV9jb3JlczsKPiArCj4gKwlyZXQgPSB6eW5xbXBfcjVfY29y ZV9pbml0KGNsdXN0ZXIpOwo+ICsJaWYgKHJldCA8IDApIHsKPiArCQlkZXZfZXJyKGRldiwgImZh aWxlZCB0byBpbml0IHI1IGNvcmUgZXJyICVkXG4iLCByZXQpOwo+ICsJCXJldHVybiByZXQ7Cj4g Kwl9Cj4gKwo+ICsJenlucW1wX3I1X3ByaW50X2R0X25vZGVfaW5mbyhjbHVzdGVyKTsKPiArCj4g KwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgenlucW1wX3I1X2NsdXN0ZXJfZXhp dCh2b2lkICpkYXRhKQo+ICt7Cj4gKwlzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2ID0gKHN0 cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKilkYXRhOwo+ICsKPiArCXBsYXRmb3JtX3NldF9kcnZkYXRh KHBkZXYsIE5VTEwpOwo+ICsKPiArCXByX2luZm8oIkV4aXQgcjVmIHN1YnN5c3RlbSBkcml2ZXJc biIpOwo+ICt9Cj4gKwo+ICsvKgo+ICsgKiB6eW5xbXBfcjVfcmVtb3RlcHJvY19wcm9iZSgpCj4g KyAqCj4gKyAqIEBwZGV2OiBkb21haW4gcGxhdGZvcm0gZGV2aWNlIGZvciBSNSBjbHVzdGVyCj4g KyAqCj4gKyAqIGNhbGxlZCB3aGVuIGRyaXZlciBpcyBwcm9iZWQsIGZvciBlYWNoIFI1IGNvcmUg c3BlY2lmaWVkIGluIERULAo+ICsgKiBzZXR1cCBhcyBuZWVkZWQgdG8gZG8gcmVtb3RlcHJvYy1y ZWxhdGVkIG9wZXJhdGlvbnMKPiArICoKPiArICogUmV0dXJuOiAwIGZvciBzdWNjZXNzLCBuZWdh dGl2ZSB2YWx1ZSBmb3IgZmFpbHVyZS4KPiArICovCj4gK3N0YXRpYyBpbnQgenlucW1wX3I1X3Jl bW90ZXByb2NfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJaW50 IHJldDsKPiArCXN0cnVjdCB6eW5xbXBfcjVfY2x1c3RlciAqY2x1c3RlcjsKPiArCXN0cnVjdCBk ZXZpY2UgKmRldiA9ICZwZGV2LT5kZXY7Cj4gKwo+ICsJY2x1c3RlciA9IGRldm1fa3phbGxvYyhk ZXYsIHNpemVvZigqY2x1c3RlciksIEdGUF9LRVJORUwpOwo+ICsJaWYgKElTX0VSUl9PUl9OVUxM KGNsdXN0ZXIpKQo+ICsJCXJldHVybiAtRU5PTUVNOwo+ICsKPiArCWNsdXN0ZXItPmRldiA9IGRl djsKPiArCj4gKwlyZXQgPSBkZXZtX29mX3BsYXRmb3JtX3BvcHVsYXRlKGRldik7Cj4gKwlpZiAo cmV0KSB7Cj4gKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gcG9wdWxhdGUgcGxhdGZvcm0gZGV2 ICVkXG4iLCByZXQpOwo+ICsJCXJldHVybiByZXQ7Cj4gKwl9Cj4gKwo+ICsJLyogd2lyZSBpbiBz byBlYWNoIGNvcmUgY2FuIGJlIGNsZWFuZWQgdXAgYXQgZHJpdmVyIHJlbW92ZSAqLwo+ICsJcGxh dGZvcm1fc2V0X2RydmRhdGEocGRldiwgY2x1c3Rlcik7Cj4gKwo+ICsJcmV0ID0gZGV2bV9hZGRf YWN0aW9uX29yX3Jlc2V0KGRldiwgenlucW1wX3I1X2NsdXN0ZXJfZXhpdCwgcGRldik7Cj4gKwlp ZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJcmV0ID0genlucW1wX3I1X2NsdXN0ZXJf aW5pdChjbHVzdGVyKTsKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJyKGRldiwgIkludmFsaWQg cjVmIHN1YnN5c3RlbSBkZXZpY2UgdHJlZVxuIik7Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0KPiAr Cj4gKwlkZXZfaW5mbyhkZXYsICJYaWxpbnggcjVmIHJlbW90ZXByb2MgZHJpdmVyIHByb2JlIHN1 Y2Nlc3NcbiIpOwo+ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gKy8qIE1hdGNoIHRhYmxlIGZvciBP RiBwbGF0Zm9ybSBiaW5kaW5nICovCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lk IHp5bnFtcF9yNV9yZW1vdGVwcm9jX21hdGNoW10gPSB7Cj4gKwl7IC5jb21wYXRpYmxlID0gInhs bngsenlucW1wLXI1ZnNzIiwgfSwKPiArCXsgLyogZW5kIG9mIGxpc3QgKi8gfSwKPiArfTsKPiAr TU9EVUxFX0RFVklDRV9UQUJMRShvZiwgenlucW1wX3I1X3JlbW90ZXByb2NfbWF0Y2gpOwo+ICsK PiArc3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgenlucW1wX3I1X3JlbW90ZXByb2NfZHJp dmVyID0gewo+ICsJLnByb2JlID0genlucW1wX3I1X3JlbW90ZXByb2NfcHJvYmUsCj4gKwkuZHJp dmVyID0gewo+ICsJCS5uYW1lID0gInp5bnFtcF9yNV9yZW1vdGVwcm9jIiwKPiArCQkub2ZfbWF0 Y2hfdGFibGUgPSB6eW5xbXBfcjVfcmVtb3RlcHJvY19tYXRjaCwKPiArCX0sCj4gK307Cj4gK21v ZHVsZV9wbGF0Zm9ybV9kcml2ZXIoenlucW1wX3I1X3JlbW90ZXByb2NfZHJpdmVyKTsKPiArCj4g K01PRFVMRV9ERVNDUklQVElPTigiWGlsaW54IFI1RiByZW1vdGUgcHJvY2Vzc29yIGRyaXZlciIp Owo+ICtNT0RVTEVfQVVUSE9SKCJYaWxpbnggSW5jLiIpOwo+ICtNT0RVTEVfTElDRU5TRSgiR1BM IHYyIik7Cj4gLS0gCj4gMi4yNS4xCj4gCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==