Re: [PATCH v6 3/5] clk: qcom: Add SDX65 GCC support

[Vamsi Krishna Lanka <quic_vamslank@quicinc.com>]

On Thu, Dec 02, 2021 at 04:20:09PM -0800, Stephen Boyd wrote:
> Quoting quic_vamslank@quicinc.com (2021-12-01 16:21:33)
> > +static struct clk_branch gcc_gp3_clk = {
> > +       .halt_reg = 0x39000,
> > +       .halt_check = BRANCH_HALT,
> > +       .clkr = {
> > +               .enable_reg = 0x39000,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "gcc_gp3_clk",
> > +                       .parent_data = &(const struct clk_parent_data){
> > +                               .hw = &gcc_gp3_clk_src.clkr.hw,
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_SET_RATE_PARENT,
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> > +
> > +static struct clk_branch gcc_pcie_0_clkref_en = {
> > +       .halt_reg = 0x88004,
> > +       /* The clock controller does not handle the status bit for
> 
> Please leave /* on it's own line for multiline comments.

Will do.

> 
> > +        * the clocks with gdscs(powerdomains) in hw controlled mode
> > +        * and hence avoid checking for the status bit of those clocks
> > +        * by setting the BRANCH_HALT_DELAY flag */
> 
> And */ too

Will do.

> 
> > +       .halt_check = BRANCH_HALT_DELAY,
> > +       .clkr = {
> > +               .enable_reg = 0x88004,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "gcc_pcie_0_clkref_en",
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};

Thanks,
Vamsi