From: Lang Yu <lang.yu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>,
Lang Yu <lang.yu@amd.com>, Lijo Lazar <lijo.lazar@amd.com>,
Huang Rui <ray.huang@amd.com>
Subject: [PATCH 2/2] drm/amdgpu: only hw fini SMU fisrt for ASICs need that
Date: Wed, 8 Dec 2021 17:26:42 +0800 [thread overview]
Message-ID: <20211208092642.173385-2-lang.yu@amd.com> (raw)
In-Reply-To: <20211208092642.173385-1-lang.yu@amd.com>
We found some headaches on ASICs don't need that,
so remove that for them.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Lang Yu <lang.yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 47 +++++++++++++++-------
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3c5afa45173c..b5b32a582c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2656,6 +2656,36 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
return 0;
}
+/**
+ * amdgpu_device_smu_fini_early - smu hw_fini wrapper
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * For ASICs need to disable SMC first
+ */
+static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
+{
+ int i, r;
+
+ if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
+ return;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.hw)
+ continue;
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
+ r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
+ /* XXX handle errors */
+ if (r) {
+ DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ }
+ adev->ip_blocks[i].status.hw = false;
+ break;
+ }
+ }
+}
+
static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
{
int i, r;
@@ -2676,21 +2706,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
- /* need to disable SMC first */
- for (i = 0; i < adev->num_ip_blocks; i++) {
- if (!adev->ip_blocks[i].status.hw)
- continue;
- if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
- r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
- /* XXX handle errors */
- if (r) {
- DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
- adev->ip_blocks[i].version->funcs->name, r);
- }
- adev->ip_blocks[i].status.hw = false;
- break;
- }
- }
+ /* Workaroud for ASICs need to disable SMC first */
+ amdgpu_device_smu_fini_early(adev);
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.hw)
--
2.25.1
next prev parent reply other threads:[~2021-12-08 9:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 9:26 [PATCH 1/2] drm/amdgpu: remove power on/off SDMA in SMU hw_init/fini() Lang Yu
2021-12-08 9:26 ` Lang Yu [this message]
2021-12-08 10:09 ` [PATCH 2/2] drm/amdgpu: only hw fini SMU fisrt for ASICs need that Wang, Yang(Kevin)
2021-12-08 10:06 ` [PATCH 1/2] drm/amdgpu: remove power on/off SDMA in SMU hw_init/fini() Wang, Yang(Kevin)
2021-12-08 10:58 ` Lang Yu
2021-12-08 11:11 ` Wang, Yang(Kevin)
2021-12-21 8:41 ` Josef Johansson
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