From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A2E1C433EF for ; Fri, 10 Dec 2021 17:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243095AbhLJR0B (ORCPT ); Fri, 10 Dec 2021 12:26:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233629AbhLJR0A (ORCPT ); Fri, 10 Dec 2021 12:26:00 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21A25C0617A1 for ; Fri, 10 Dec 2021 09:22:25 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id y14-20020a17090a2b4e00b001a5824f4918so9898096pjc.4 for ; Fri, 10 Dec 2021 09:22:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=wXxIFl9RShCE91zPfAkRMM2xkNysozE7SyLpZ9J+nMQ=; b=EpE/rgKdOcYRenD95ZbWiQrngH8Tl15OH1snNOs8EPxs3GgWkEvorwVblkx2wsBJUg WA+LTAFlx2XwAeZr3dV3mIAIjR9vXel5L/1w3zL8PpIYRc6aoBxfFrNowMuiolR8T7hU 7EpFi6deY8yIV1h0OjLPFhXPScAQYwqYMi2tndjchJBe921C8lJDx8fk4UTYBGT2gGyB JOz7BhUosg66vAmhJkHA2QSfqnU0tkxSYJYnARFGaLBCwvuNKkuTRXCd3tCqu1cSCC+J PlMrXVfKzQKW9+/1/BkY5DQXDsC5eqvUWki3FrzIo9wgpEPzQRjehGuL+1vDtm+SPOaI GTAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=wXxIFl9RShCE91zPfAkRMM2xkNysozE7SyLpZ9J+nMQ=; b=X8tq2jRIhwtPbgJCWNoyIdgM2N0KPlpq2ghDxQs4u68CjfVQcf2c0Fwr/h5RwF+gWl DDFqsIzd8C3vymNYL/0CwEWn/RrEtjzmlaDynCie6NL5CP2StdNXlLbs68JJKHTXmtSU 0pYVS2eUJ06kZ0E5OeMC/fAdHftaqYazhDgrvcI4Pfk9qQogkgUZOpsCo8UreLNyi9pU EanddxC9FAkhreUgKXuXQ3GGDeOZud6zS5MM2Q9xVqXdr5Xuphw43F7n2lW6m/z0fAcR s/LAwUAs69JTkoKTI23D/lzULkl7t/ddzLS/aab4p7Cyj/wP4ZYtbokuZj9s9ZNJSZv4 z5Ng== X-Gm-Message-State: AOAM530GCZ+eVyiV7ONrfRUJ9cbFiDIoxhjqFJTiW6uPEp4G9wVPctTa 4sEt31leUMCQ+Kl87IgLHotusg== X-Google-Smtp-Source: ABdhPJx7Vdr5SMDMisR3Ceovs6RgrPHB/lYT7Zy/5wLyTyte6MMYQevltUY2u+OivAZiAKVpeaB1Pw== X-Received: by 2002:a17:90b:4f49:: with SMTP id pj9mr24773259pjb.159.1639156944110; Fri, 10 Dec 2021 09:22:24 -0800 (PST) Received: from p14s (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id h66sm3110587pgc.34.2021.12.10.09.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 09:22:23 -0800 (PST) Date: Fri, 10 Dec 2021 10:22:20 -0700 From: Mathieu Poirier To: James Clark Cc: Suzuki K Poulose , coresight@lists.linaro.org, Mike Leach , Leo Yan , John Garry , Will Deacon , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH 2/3] coresight: Fail to open with return stacks if they are unavailable Message-ID: <20211210172220.GA1238770@p14s> References: <20211208160907.749482-1-james.clark@arm.com> <20211208160907.749482-2-james.clark@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Hi James, On Thu, Dec 09, 2021 at 11:13:55AM +0000, James Clark wrote: > > > On 09/12/2021 11:00, Suzuki K Poulose wrote: > > On 08/12/2021 16:09, James Clark wrote: > >> Maintain consistency with the other options by failing to open when they > >> aren't supported. For example ETM_OPT_TS, ETM_OPT_CTXTID2 and the newly > >> added ETM_OPT_BRANCH_BROADCAST all return with -EINVAL if they are > >> requested but not supported by hardware. > >> > >> The consequence of not doing this is that the user may not be > >> aware that they are not enabling the feature as it is silently disabled. > >> > >> Signed-off-by: James Clark > >> --- > >>   drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++---- > >>   1 file changed, 9 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> index d2bafb50c66a..0a9bb943a5e5 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> @@ -674,10 +674,15 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > >>       } > >>         /* return stack - enable if selected and supported */ > >> -    if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) > >> -        /* bit[12], Return stack enable bit */ > >> -        config->cfg |= BIT(12); > >> - > >> +    if (attr->config & BIT(ETM_OPT_RETSTK)) { > >> +        if (!drvdata->retstack) { > >> +            ret = -EINVAL; > >> +            goto out; > >> +        } else { > >> +            /* bit[12], Return stack enable bit */ > >> +            config->cfg |= BIT(12); > >> +        } > > > > nit: While at this, please could you change the hard coded value > > to ETM4_CFG_BIT_RETSTK ? > > > I started changing them all because I had trouble searching for bits by name but then > I thought it would snowball into a bigger change so I undid it. > > I think I'll just go and do it now if it's an issue here. I can apply this set right away and you send another patch to fix all hard coded bitfields or you can send another revision with all 4 patches included in it (bitfields fix plus these 3). Just let me know what you want to do. And next time please add a cover letter. Thanks, Mathieu > > > Otherwise, looks good to me > > > > Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1A27C433EF for ; Fri, 10 Dec 2021 17:24:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1TcsvOzk0vHIjxTAEkvNCOxv6qma1IX84cDDyFLHST4=; b=A+73WdtxtSWZVU bU3tQPYRaejkiuPw3qfcVodnRseg+kUFo2r6eHrlDzPCfACAMOutZMsBeSzFxAuOvur4LGlN0WOWN 8z/waFzqUPlumxtIb9mdZ8I9KJ/G8j/cMmkBOA+9LvnuMRu4UYKibWJB0UZijXHMZ4SXq/EyZ/epm n8+pcywmnJP+d2nMM1sr/Gamt5evJADhtcsNF4MxyY7dgucX1GlXNC6UDXNJoC2RtM45c2xRyMHyC nExquWSEC9gRqFEub78MRIHiPlus+sj2f4xuVEL33/nhfrY+gF7fXGPmfk4ByHcnidEWK52oYv7us Yx/ZGiNbMEHrKN9iYhkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjbJ-002o5Z-Th; Fri, 10 Dec 2021 17:22:30 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvjbF-002o4P-ES for linux-arm-kernel@lists.infradead.org; Fri, 10 Dec 2021 17:22:26 +0000 Received: by mail-pj1-x102f.google.com with SMTP id np3so7285971pjb.4 for ; Fri, 10 Dec 2021 09:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=wXxIFl9RShCE91zPfAkRMM2xkNysozE7SyLpZ9J+nMQ=; b=EpE/rgKdOcYRenD95ZbWiQrngH8Tl15OH1snNOs8EPxs3GgWkEvorwVblkx2wsBJUg WA+LTAFlx2XwAeZr3dV3mIAIjR9vXel5L/1w3zL8PpIYRc6aoBxfFrNowMuiolR8T7hU 7EpFi6deY8yIV1h0OjLPFhXPScAQYwqYMi2tndjchJBe921C8lJDx8fk4UTYBGT2gGyB JOz7BhUosg66vAmhJkHA2QSfqnU0tkxSYJYnARFGaLBCwvuNKkuTRXCd3tCqu1cSCC+J PlMrXVfKzQKW9+/1/BkY5DQXDsC5eqvUWki3FrzIo9wgpEPzQRjehGuL+1vDtm+SPOaI GTAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=wXxIFl9RShCE91zPfAkRMM2xkNysozE7SyLpZ9J+nMQ=; b=ewT6CJC1BXNe3RKtYbIFsNKQRPnbxrHsjfT1e5R9zIGkeRLk6pEUv0YlbNdVy0tpz4 samfGs46yN+mC3WrWkfs5eoAlNYwCV4bqG0kZH/OEtOD903jFptjhj3FrztRUvvzPL/Q /M7TsGG3dyHwhyGz+5gJtE8U/izqHYGhmg7O6Imp/LPEGrQiU0Zdsu5bBfl0KxEchrCm e1HWq4kQzT/k/YvFxDGXG63GIQq0nM1V4GpIFvjeUVsm9c5Kpawvr3Bspnis3i30auSB 9VMoAnDHfDUXsSqkIHYZki4REUMeA03Vfxq+1pfBmxIxUlheBMkacx+vJkCtpankkKZv qXBw== X-Gm-Message-State: AOAM532E8921SgPXabKVFr0AdSIiVsFrvcYr7zp/5eShjN7UWwEEuQm3 LoDpFlXwDWFVFNpHYTNfNiWW9A== X-Google-Smtp-Source: ABdhPJx7Vdr5SMDMisR3Ceovs6RgrPHB/lYT7Zy/5wLyTyte6MMYQevltUY2u+OivAZiAKVpeaB1Pw== X-Received: by 2002:a17:90b:4f49:: with SMTP id pj9mr24773259pjb.159.1639156944110; Fri, 10 Dec 2021 09:22:24 -0800 (PST) Received: from p14s (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id h66sm3110587pgc.34.2021.12.10.09.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 09:22:23 -0800 (PST) Date: Fri, 10 Dec 2021 10:22:20 -0700 From: Mathieu Poirier To: James Clark Cc: Suzuki K Poulose , coresight@lists.linaro.org, Mike Leach , Leo Yan , John Garry , Will Deacon , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: Re: [PATCH 2/3] coresight: Fail to open with return stacks if they are unavailable Message-ID: <20211210172220.GA1238770@p14s> References: <20211208160907.749482-1-james.clark@arm.com> <20211208160907.749482-2-james.clark@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_092225_527642_ACB8DD8B X-CRM114-Status: GOOD ( 29.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On Thu, Dec 09, 2021 at 11:13:55AM +0000, James Clark wrote: > = > = > On 09/12/2021 11:00, Suzuki K Poulose wrote: > > On 08/12/2021 16:09, James Clark wrote: > >> Maintain consistency with the other options by failing to open when th= ey > >> aren't supported. For example ETM_OPT_TS, ETM_OPT_CTXTID2 and the newly > >> added ETM_OPT_BRANCH_BROADCAST all return with -EINVAL if they are > >> requested but not supported by hardware. > >> > >> The consequence of not doing this is that the user may not be > >> aware that they are not enabling the feature as it is silently disable= d. > >> > >> Signed-off-by: James Clark > >> --- > >> =A0 drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++-= --- > >> =A0 1 file changed, 9 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/driv= ers/hwtracing/coresight/coresight-etm4x-core.c > >> index d2bafb50c66a..0a9bb943a5e5 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > >> @@ -674,10 +674,15 @@ static int etm4_parse_event_config(struct coresi= ght_device *csdev, > >> =A0=A0=A0=A0=A0 } > >> =A0 =A0=A0=A0=A0=A0 /* return stack - enable if selected and supported= */ > >> -=A0=A0=A0 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retsta= ck) > >> -=A0=A0=A0=A0=A0=A0=A0 /* bit[12], Return stack enable bit */ > >> -=A0=A0=A0=A0=A0=A0=A0 config->cfg |=3D BIT(12); > >> - > >> +=A0=A0=A0 if (attr->config & BIT(ETM_OPT_RETSTK)) { > >> +=A0=A0=A0=A0=A0=A0=A0 if (!drvdata->retstack) { > >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 ret =3D -EINVAL; > >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 goto out; > >> +=A0=A0=A0=A0=A0=A0=A0 } else { > >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* bit[12], Return stack enable bit= */ > >> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 config->cfg |=3D BIT(12); > >> +=A0=A0=A0=A0=A0=A0=A0 } > > = > > nit: While at this, please could you change the hard coded value > > to ETM4_CFG_BIT_RETSTK ? > > = > I started changing them all because I had trouble searching for bits by n= ame but then > I thought it would snowball into a bigger change so I undid it. > = > I think I'll just go and do it now if it's an issue here. I can apply this set right away and you send another patch to fix all hard = coded bitfields or you can send another revision with all 4 patches included in it (bitfields fix plus these 3). Just let me know what you want to do. And n= ext time please add a cover letter. Thanks, Mathieu > = > > Otherwise, looks good to me > > = > > Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel