From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============0281071599722186569==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [intel-lts:5.4/yocto 14111/18531] drivers/mtd/spi-nor/core.c:3383:34: sparse: sparse: cast to restricted __le32 Date: Sat, 11 Dec 2021 04:36:42 +0800 Message-ID: <202112110458.Vu91dnou-lkp@intel.com> List-Id: --===============0281071599722186569== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto head: 93b630f89c8d94187fd181ae4cbca13b4b47201c commit: 4541b62447f9a65c9192597304d5f6cd11664386 [14111/18531] mtd: spi-nor= : Prepare core / manufacturer code split config: sh-randconfig-s032-20211206 (https://download.01.org/0day-ci/archiv= e/20211211/202112110458.Vu91dnou-lkp(a)intel.com/config) compiler: sh4-linux-gcc (GCC) 11.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/= make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # apt-get install sparse # sparse version: v0.6.4-dirty # https://github.com/intel/linux-intel-lts/commit/4541b62447f9a65c9= 192597304d5f6cd11664386 git remote add intel-lts https://github.com/intel/linux-intel-lts.g= it git fetch --no-tags intel-lts 5.4/yocto git checkout 4541b62447f9a65c9192597304d5f6cd11664386 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=3D$HOME/0day COMPILER=3Dgcc-11.2.0 make.cross= C=3D1 CF=3D'-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=3Dbuild_dir ARCH=3Ds= h SHELL=3D/bin/bash drivers/mtd/spi-nor/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot sparse warnings: (new ones prefixed by >>) >> drivers/mtd/spi-nor/core.c:3383:34: sparse: sparse: cast to restricted _= _le32 >> drivers/mtd/spi-nor/core.c:3651:38: sparse: sparse: dubious: x | !y drivers/mtd/spi-nor/core.c:3837:27: sparse: sparse: cast to restricted _= _le32 drivers/mtd/spi-nor/core.c:3931:29: sparse: sparse: cast to restricted _= _le32 drivers/mtd/spi-nor/core.c:4071:13: sparse: sparse: cast to restricted _= _le32 vim +3383 drivers/mtd/spi-nor/core.c 2aaa5f7e0c07a0 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 33= 24 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 25 /** f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 26 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Tabl= e. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 27 * @nor: pointer to a 'struct spi_nor' f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 28 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describi= ng f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 29 * the Basic Flash Parameter Table length and version f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 30 * @params: pointer to the 'struct spi_nor_flash_parameter' to be f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 31 * filled f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 32 * f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 33 * The Basic Flash Parameter Table is the main and only mandatory table= as f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 34 * defined by the SFDP (JESD216) specification. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 35 * It provides us with the total size (memory density) of the data arra= y and f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 36 * the number of address bytes for Fast Read, Page Program and Sector E= rase f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 37 * commands. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 38 * For Fast READ commands, it also gives the number of mode clock cycle= s and f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 39 * wait states (regrouped in the number of dummy clock cycles) for each f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 40 * supported instruction op code. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 41 * For Page Program, the page size is now available since JESD216 rev A= , however f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 42 * the supported instruction op codes are still not provided. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 43 * For Sector Erase commands, this table stores the supported instructi= on op f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 44 * codes and the associated sector sizes. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 45 * Finally, the Quad Enable Requirements (QER) are also available since= JESD216 f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 46 * rev A. The QER bits encode the manufacturer dependent procedure to be f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 47 * executed to set the Quad Enable (QE) bit in some internal register o= f the f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 48 * Quad SPI memory. Indeed the QE bit, when it exists, must be set befo= re f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 49 * sending any Quad SPI command to the memory. Actually, setting the QE= bit f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 50 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functi= ons IO2 f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 51 * and IO3 hence enabling 4 (Quad) I/O lines. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 52 * f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 53 * Return: 0 on success, -errno otherwise. f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 54 */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 55 static int spi_nor_parse_bfpt(struct spi_nor *nor, f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 56 const struct sfdp_parameter_header *bfpt_header, f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 57 struct spi_nor_flash_parameter *params) f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 58 { c46872170a54c9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2019-08-23 33= 59 struct spi_nor_erase_map *map =3D ¶ms->erase_map; 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 33= 60 struct spi_nor_erase_type *erase_type =3D map->erase_type; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 61 struct sfdp_bfpt bfpt; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 62 size_t len; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 63 int i, cmd, err; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 64 u32 addr; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 65 u16 half; 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 33= 66 u8 erase_mask; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 67 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 68 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 69 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 70 return -EINVAL; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 71 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 72 /* Read the Basic Flash Parameter Table. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 73 len =3D min_t(size_t, sizeof(bfpt), f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 74 bfpt_header->length * sizeof(u32)); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 75 addr =3D SFDP_PARAM_HEADER_PTP(bfpt_header); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 76 memset(&bfpt, 0, sizeof(bfpt)); bfa4133795e5a0 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-09-06 33= 77 err =3D spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 78 if (err < 0) f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 79 return err; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 80 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 81 /* Fix endianness of the BFPT DWORDs. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 82 for (i =3D 0; i < BFPT_DWORD_MAX; i++) f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 @33= 83 bfpt.dwords[i] =3D le32_to_cpu(bfpt.dwords[i]); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 84 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 85 /* Number of address bytes. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 86 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 87 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 88 nor->addr_width =3D 3; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 89 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 90 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 91 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 92 nor->addr_width =3D 4; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 93 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 94 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 95 default: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 96 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 97 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 98 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 33= 99 /* Flash Memory Density (in bits). */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 00 params->size =3D bfpt.dwords[BFPT_DWORD(2)]; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 01 if (params->size & BIT(31)) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 02 params->size &=3D ~BIT(31); b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 03 = b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 04 /* b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 05 * Prevent overflows on params->size. Anyway, a NOR of 2^64 b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 06 * bits is unlikely to exist so this error probably means b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 07 * the BFPT we are reading is corrupted/wrong. b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 08 */ b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 09 if (params->size > 63) b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 10 return -EINVAL; b8f3911610529b drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 34= 11 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 12 params->size =3D 1ULL << params->size; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 13 } else { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 14 params->size++; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 15 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 16 params->size >>=3D 3; /* Convert to bytes. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 17 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 18 /* Fast Read settings. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 19 for (i =3D 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 20 const struct sfdp_bfpt_read *rd =3D &sfdp_bfpt_reads[i]; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 21 struct spi_nor_read_command *read; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 22 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 23 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 24 params->hwcaps.mask &=3D ~rd->hwcaps; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 25 continue; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 26 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 27 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 28 params->hwcaps.mask |=3D rd->hwcaps; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 29 cmd =3D spi_nor_hwcaps_read2cmd(rd->hwcaps); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 30 read =3D ¶ms->reads[cmd]; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 31 half =3D bfpt.dwords[rd->settings_dword] >> rd->settings_shift; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 32 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 33 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 34 = 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 35 /* 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 36 * Sector Erase settings. Reinitialize the uniform erase map using the 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 37 * Erase Types defined in the bfpt table. 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 38 */ 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 39 erase_mask =3D 0; c46872170a54c9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2019-08-23 34= 40 memset(¶ms->erase_map, 0, sizeof(params->erase_map)); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 41 for (i =3D 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 42 const struct sfdp_bfpt_erase *er =3D &sfdp_bfpt_erases[i]; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 43 u32 erasesize; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 44 u8 opcode; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 45 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 46 half =3D bfpt.dwords[er->dword] >> er->shift; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 47 erasesize =3D half & 0xff; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 48 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 49 /* erasesize =3D=3D 0 means this Erase Type is not supported. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 50 if (!erasesize) f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 51 continue; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 52 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 53 erasesize =3D 1U << erasesize; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 54 opcode =3D (half >> 8) & 0xff; 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 55 erase_mask |=3D BIT(i); 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 56 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize, 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 57 opcode, i); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 58 } 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 59 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 60 /* 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 61 * Sort all the map's Erase Types in ascending order with the smallest 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 62 * erase size being the first member in the erase_type array. 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 63 */ 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 64 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]), 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 65 spi_nor_map_cmp_erase_type, NULL); 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 66 /* 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 67 * Sort the erase types in the uniform region in order to update the 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 68 * uniform_erase_type bitmask. The bitmask will be used later on when 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 69 * selecting the uniform erase. 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 70 */ 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 71 spi_nor_regions_sort_erase_types(map); 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 72 map->uniform_erase_type =3D map->uniform_region.offset & 5390a8df769ec9 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 34= 73 SNOR_ERASE_TYPE_MASK; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 74 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 75 /* Stop here if not JESD216 rev A or later. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 76 if (bfpt_header->length < BFPT_DWORD_MAX) 2aaa5f7e0c07a0 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 34= 77 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, 2aaa5f7e0c07a0 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 34= 78 params); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 79 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 80 /* Page size: this field specifies 'N' so the page size =3D 2^N bytes.= */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 81 params->page_size =3D bfpt.dwords[BFPT_DWORD(11)]; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 82 params->page_size &=3D BFPT_DWORD11_PAGE_SIZE_MASK; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 83 params->page_size >>=3D BFPT_DWORD11_PAGE_SIZE_SHIFT; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 84 params->page_size =3D 1U << params->page_size; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 85 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 86 /* Quad Enable Requirements. */ f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 87 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 88 case BFPT_DWORD15_QER_NONE: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 89 params->quad_enable =3D NULL; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 90 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 91 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 92 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 93 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 94 params->quad_enable =3D spansion_no_read_cr_quad_enable; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 95 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 96 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 97 case BFPT_DWORD15_QER_SR1_BIT6: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 98 params->quad_enable =3D macronix_quad_enable; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 34= 99 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 00 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 01 case BFPT_DWORD15_QER_SR2_BIT7: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 02 params->quad_enable =3D sr2_bit7_quad_enable; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 03 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 04 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 05 case BFPT_DWORD15_QER_SR2_BIT1: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 06 params->quad_enable =3D spansion_read_cr_quad_enable; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 07 break; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 08 = f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 09 default: f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 10 return -EINVAL; f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 11 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 12 = 2aaa5f7e0c07a0 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 35= 13 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params); f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 14 } f384b352cbf031 drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 35= 15 = :::::: The code at line 3383 was first introduced by commit :::::: f384b352cbf0310fd20c379c4710408c70e769b6 mtd: spi-nor: parse Serial = Flash Discoverable Parameters (SFDP) tables :::::: TO: Cyrille Pitchen :::::: CC: Cyrille Pitchen --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============0281071599722186569==--