From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org,
david@gibson.dropbear.id.au
Subject: [RFC v2 01/12] target/ppc: powerpc_excp: Set alternate SRRs directly
Date: Mon, 20 Dec 2021 15:18:52 -0300 [thread overview]
Message-ID: <20211220181903.3456898-2-farosas@linux.ibm.com> (raw)
In-Reply-To: <20211220181903.3456898-1-farosas@linux.ibm.com>
There are currently only two interrupts that use alternate SRRs, so
let them write to them directly during the setup code.
No functional change intented.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f90e616aac..8b9c6bc5a8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -298,7 +298,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, asrr0, asrr1, lev = -1;
+ int srr0, srr1, lev = -1;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code);
@@ -319,8 +319,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- asrr0 = -1;
- asrr1 = -1;
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
@@ -410,8 +408,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_MCSRR0;
srr1 = SPR_BOOKE_MCSRR1;
- asrr0 = SPR_BOOKE_CSRR0;
- asrr1 = SPR_BOOKE_CSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
break;
default:
break;
@@ -570,8 +569,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_DSRR0;
srr1 = SPR_BOOKE_DSRR1;
- asrr0 = SPR_BOOKE_CSRR0;
- asrr1 = SPR_BOOKE_CSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
/* DBSR already modified by caller */
} else {
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
@@ -838,14 +839,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
vector |= env->excp_prefix;
- /* If any alternate SRR register are defined, duplicate saved values */
- if (asrr0 != -1) {
- env->spr[asrr0] = env->nip;
- }
- if (asrr1 != -1) {
- env->spr[asrr1] = msr;
- }
-
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_BOOKE) {
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
--
2.33.1
next prev parent reply other threads:[~2021-12-20 19:43 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 18:18 [RFC v2 00/12] target/ppc: powerpc_excp improvements Fabiano Rosas
2021-12-20 18:18 ` Fabiano Rosas [this message]
2021-12-21 23:32 ` [RFC v2 01/12] target/ppc: powerpc_excp: Set alternate SRRs directly Richard Henderson
2021-12-22 6:46 ` Cédric Le Goater
2021-12-23 4:39 ` David Gibson
2021-12-20 18:18 ` [RFC v2 02/12] target/ppc: powerpc_excp: Set vector earlier Fabiano Rosas
2021-12-22 6:48 ` Cédric Le Goater
2021-12-25 10:45 ` Nicholas Piggin
2021-12-24 0:11 ` Richard Henderson
2021-12-24 11:14 ` Fabiano Rosas
2021-12-20 18:18 ` [RFC v2 03/12] target/ppc: powerpc_excp: Move system call vectored code together Fabiano Rosas
2021-12-22 6:48 ` Cédric Le Goater
2021-12-24 0:12 ` Richard Henderson
2021-12-20 18:18 ` [RFC v2 04/12] target/ppc: powerpc_excp: Stop passing excp_model around Fabiano Rosas
2021-12-22 6:48 ` Cédric Le Goater
2021-12-24 0:13 ` Richard Henderson
2021-12-25 6:33 ` David Gibson
2021-12-20 18:18 ` [RFC v2 05/12] target/ppc: powerpc_excp: Standardize arguments to interrupt code Fabiano Rosas
2021-12-25 6:35 ` David Gibson
2021-12-27 17:13 ` Fabiano Rosas
2021-12-20 18:18 ` [RFC v2 06/12] target/ppc: Extract interrupt routines into a new file Fabiano Rosas
2021-12-20 18:18 ` [RFC v2 07/12] target/ppc: Introduce PPCInterrupt Fabiano Rosas
2021-12-20 18:18 ` [RFC v2 08/12] target/ppc: Remove unimplemented interrupt code Fabiano Rosas
2021-12-20 18:19 ` [RFC v2 09/12] target/ppc: Use common code for Hypervisor interrupts Fabiano Rosas
2021-12-20 18:19 ` [RFC v2 10/12] target/ppc: Split powerpc_excp into book3s, booke and 32 bit Fabiano Rosas
2021-12-20 18:19 ` [RFC v2 11/12] target/ppc: Create new files for book3s, booke and ppc32 exception code Fabiano Rosas
2021-12-20 18:19 ` [RFC v2 12/12] target/ppc: Do not enable all interrupts when running KVM Fabiano Rosas
2021-12-26 16:48 ` [RFC v2 00/12] target/ppc: powerpc_excp improvements Cédric Le Goater
2021-12-29 14:18 ` Fabiano Rosas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211220181903.3456898-2-farosas@linux.ibm.com \
--to=farosas@linux.ibm.com \
--cc=clg@kaod.org \
--cc=danielhb413@gmail.com \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.