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linux-kernel@vger.kernel.org, Michael Trimarchi , Han Xu , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org Subject: Re: [RFC PATCH 4/4] mtd: rawnand: gpmi: validate controller clock rate Message-ID: <20211222172323.1bc565c0@xps13> In-Reply-To: <20211217155512.1877408-5-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> <20211217155512.1877408-5-dario.binacchi@amarulasolutions.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211222_082331_092615_6372CFBD X-CRM114-Status: GOOD ( 34.47 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgRGFyaW8sCgpkYXJpby5iaW5hY2NoaUBhbWFydWxhc29sdXRpb25zLmNvbSB3cm90ZSBvbiBG cmksIDE3IERlYyAyMDIxIDE2OjU1OjEyCiswMTAwOgoKPiBXaGF0IHRvIGRvIHdoZW4gdGhlIHJl YWwgcmF0ZSBvZiB0aGUgZ3BtaSBjbG9jayBpcyBub3QgZXF1YWwgdG8gdGhlCj4gcmVxdWlyZWQg b25lPyBUaGUgc29sdXRpb25zIHByb3Bvc2VkIGluIFsxXSBkaWQgbm90IGxlYWQgdG8gYSBjb25j bHVzaW9uCj4gb24gaG93IHRvIHZhbGlkYXRlIHRoZSBjbG9jayByYXRlLCBzbywgaW5zcGlyZWQg YnkgdGhlIGRvY3VtZW50IFsyXSwgSQo+IGNvbnNpZGVyIHRoZSByYXRlIGNvcnJlY3Qgb25seSBp ZiBub3QgZ3JlYXRlciB0aGFuIHRoZSByYXRlIG9mIHRoZQo+IHByZXZpb3VzIGVkby4KCk5vdCBn cmVhdGVyPyB3aGF0IGFyZSB5b3UgdGFsa2luZyBhYm91dCBoZXJlLCBpZiBpdCdzIGEgcmF0ZSwg YXJlIHlvdQpzdXJlICJub3QgZ3JlYXRlciIgaXMgd2hhdCB5b3UgbWVhbj8KCj4gSW4gZmFjdCwg aW4gY2hhcHRlciA0LjE2LjIgKE5WLUREUikgb2YgdGhlIGRvY3VtZW50IFsyXSwKPiBpdCBpcyB3 cml0dGVuIHRoYXQgIklmIHRoZSBob3N0IHNlbGVjdHMgdGltaW5nIG1vZGUgbiwgdGhlbiBpdHMg Y2xvY2sKPiBwZXJpb2Qgc2hhbGwgYmUgZmFzdGVyIHRoYW4gdGhlIGNsb2NrIHBlcmlvZCBvZiB0 aW1pbmcgbW9kZSBuLTEgYW5kCgpmYXN0ZXI/IGlzIHRoYXQgdGhlIHJlYWwgd29yZGluZyBpbiB0 aGUgZG9jdW1lbnQ/IHNlZW1zIGluYWNjdXJhdGUgd2hlbgpyZWZlcnJpbmcgdG8gYSBjbG9jayBw ZXJpb2QuCgo+IHNsb3dlciB0aGFuIG9yIGVxdWFsIHRvIHRoZSBjbG9jayBwZXJpb2Qgb2YgdGlt aW5nIG1vZGUgbi4iLiBJIHRob3VnaHQKPiB0aGF0IGl0IGNvdWxkIHRoZXJlZm9yZSBhbHNvIGJl IHVzZWQgaW4gdGhpcyBjYXNlLCB3aXRob3V0IHRoZXJlZm9yZQo+IGhhdmluZyB0byBkZWZpbmUg dGhlIHZhbGlkIHJhdGUgcmFuZ2VzIGVtcGlyaWNhbGx5LgoKQ2FuIHlvdSBnaXZlIGVtcGlyaWNh bCB2YWx1ZXMgaW4geW91ciBjYXNlIHNvIHRoYXQgd2UgdW5kZXJzdGFuZCBiZXR0ZXIKdGhlIHBy b2JsZW0gdGhhdCB5b3UgYXJlIHRyeWluZyB0byBzb2x2ZSBhbmQgaG93IHlvdSBzb2x2ZSBpdD8K CkFsc28sIEkgZG9uJ3Qga25vdyBpZiB0aGUgTlYtRERSIGxvZ2ljIGFwcGxpZXMgdG8gU0RSIEVE TyBtb2RlcywgYnV0IGlmCml0IHdvcmtzIGFuZCBpZiBIYW4gYWNrbm93bGVkZ2VzIGl0LCBpdCdz IGZpbmUgZm9yIG1lLgoKPiBbMV0gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvci8yMDIxMDcwMjA2 NTM1MC4yMDk2NDYtNS1lYmlnZ2Vyc0BrZXJuZWwub3JnCj4gWzJdIGh0dHA6Ly93d3cub25maS5v cmcvLS9tZWRpYS9jbGllbnQvb25maS9zcGVjcy9vbmZpXzNfMF9nb2xkLnBkZj9sYT1lbgo+IAo+ IFNpZ25lZC1vZmYtYnk6IERhcmlvIEJpbmFjY2hpIDxkYXJpby5iaW5hY2NoaUBhbWFydWxhc29s dXRpb25zLmNvbT4KPiBDby1kZXZlbG9wZWQtYnk6IE1pY2hhZWwgVHJpbWFyY2hpIDxtaWNoYWVs QGFtYXJ1bGFzb2x1dGlvbnMuY29tPgoKWW91IG5lZWQgTWljaGFlbCdzIFNpZ25lZC1vZmYtYnku Cgo+IAo+IC0tLQo+IAo+ICBkcml2ZXJzL210ZC9uYW5kL3Jhdy9ncG1pLW5hbmQvZ3BtaS1uYW5k LmMgfCA3MCArKysrKysrKysrKysrKysrKy0tLS0tCj4gIDEgZmlsZSBjaGFuZ2VkLCA1NCBpbnNl cnRpb25zKCspLCAxNiBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQv bmFuZC9yYXcvZ3BtaS1uYW5kL2dwbWktbmFuZC5jIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvZ3Bt aS1uYW5kL2dwbWktbmFuZC5jCj4gaW5kZXggMDUxN2I4MWJiMjRjLi4zZDM3Y2Q0OWFiZDUgMTAw NjQ0Cj4gLS0tIGEvZHJpdmVycy9tdGQvbmFuZC9yYXcvZ3BtaS1uYW5kL2dwbWktbmFuZC5jCj4g KysrIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvZ3BtaS1uYW5kL2dwbWktbmFuZC5jCj4gQEAgLTU3 MCw2ICs1NzAsMjcgQEAgc3RhdGljIGludCBiY2hfc2V0X2dlb21ldHJ5KHN0cnVjdCBncG1pX25h bmRfZGF0YSAqdGhpcykKPiAgCXJldHVybiByZXQ7Cj4gIH0KPiAgCj4gK3N0cnVjdCBlZG9fbW9k ZSB7Cj4gKwl1MzIgdFJDX21pbjsKPiArCWxvbmcgY2xrX3JhdGU7Cj4gKwl1OCB3cm5fZGx5X3Nl bDsKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZWRvX21vZGUgZWRvX21vZGVzW10g PSB7Cj4gKwl7LnRSQ19taW4gPSAzMDAwMCwgLmNsa19yYXRlID0gMjIwMDAwMDAsCgpEbyB5b3Ug cmVhbGx5IG5lZWQgdG8gcHJvdmlkZSBhIHRSQ19taW4gaGVyZT8gSXQgaXMgYWxyZWFkeSBwYXJ0 IG9mIHRoZQpuYW5kX3RpbWluZ3Mgc3RydWN0dXJlLgoKPiArCSAud3JuX2RseV9zZWwgPSBCVl9H UE1JX0NUUkwxX1dSTl9ETFlfU0VMXzRfVE9fOE5TfSwKPiArCXsudFJDX21pbiA9IDMwMDAwLCAu Y2xrX3JhdGUgPSAyMjAwMDAwMCwKPiArCSAud3JuX2RseV9zZWwgPSBCVl9HUE1JX0NUUkwxX1dS Tl9ETFlfU0VMXzRfVE9fOE5TfSwKPiArCXsudFJDX21pbiA9IDMwMDAwLCAuY2xrX3JhdGUgPSAy MjAwMDAwMCwKPiArCSAud3JuX2RseV9zZWwgPSBCVl9HUE1JX0NUUkwxX1dSTl9ETFlfU0VMXzRf VE9fOE5TfSwKPiArCXsudFJDX21pbiA9IDMwMDAwLCAuY2xrX3JhdGUgPSAyMjAwMDAwMCwKCk5v dCBzdXJlIHRvIGdldCB0aGUgZGlmZmVyZW5jZSBiZXR3ZWVuIHRoZXNlIHRocmVlIGZpcnN0IG1v ZGVzLgoKPiArCSAud3JuX2RseV9zZWwgPSBCVl9HUE1JX0NUUkwxX1dSTl9ETFlfU0VMXzRfVE9f OE5TfSwKPiArCXsudFJDX21pbiA9IDI1MDAwLCAuY2xrX3JhdGUgPSA4MDAwMDAwMCwKPiArCSAu d3JuX2RseV9zZWwgPSBCVl9HUE1JX0NUUkwxX1dSTl9ETFlfU0VMX05PX0RFTEFZfSwKPiArCXsu dFJDX21pbiA9IDIwMDAwLCAuY2xrX3JhdGUgPSAxMDAwMDAwMDAsCj4gKwkgLndybl9kbHlfc2Vs ID0gQlZfR1BNSV9DVFJMMV9XUk5fRExZX1NFTF9OT19ERUxBWX0sCgpJIGFtIGFsc28gdGVtcHRl ZCB0byBzYXkgdGhhdCBJIGRvbid0IHJlYWxseSB1bmRlcnN0YW5kIHdoYXQgdGhpcyBpcwphbGwg YWJvdXQsIG1heWJlIGFuIGV4cGxhbmF0aW9uIHdvdWxkIGJlIGdvb2QgaW4gYSBjb21tZW50Lgo+ ICt9Owo+ICsKPiAgLyoKPiAgICogPDE+IEZpcnN0bHksIHdlIHNob3VsZCBrbm93IHdoYXQncyB0 aGUgR1BNSS1jbG9jayBtZWFucy4KPiAgICogICAgIFRoZSBHUE1JLWNsb2NrIGlzIHRoZSBpbnRl cm5hbCBjbG9jayBpbiB0aGUgZ3BtaSBuYW5kIGNvbnRyb2xsZXIuCj4gQEAgLTY0NCw4ICs2NjUs OCBAQCBzdGF0aWMgaW50IGJjaF9zZXRfZ2VvbWV0cnkoc3RydWN0IGdwbWlfbmFuZF9kYXRhICp0 aGlzKQo+ICAgKiAgICAgICAgIFJETl9ERUxBWSA9IC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tICAg ICB7M30KPiAgICogICAgICAgICAgICAgICAgICAgICAgICAgICBSUAo+ICAgKi8KPiAtc3RhdGlj IHZvaWQgZ3BtaV9uZmNfY29tcHV0ZV90aW1pbmdzKHN0cnVjdCBncG1pX25hbmRfZGF0YSAqdGhp cywKPiAtCQkJCSAgICAgY29uc3Qgc3RydWN0IG5hbmRfc2RyX3RpbWluZ3MgKnNkcikKPiArc3Rh dGljIGludCBncG1pX25mY19jb21wdXRlX3RpbWluZ3Moc3RydWN0IGdwbWlfbmFuZF9kYXRhICp0 aGlzLAo+ICsJCQkJICAgIGNvbnN0IHN0cnVjdCBuYW5kX3Nkcl90aW1pbmdzICpzZHIpCj4gIHsK PiAgCXN0cnVjdCBncG1pX25mY19oYXJkd2FyZV90aW1pbmcgKmh3ID0gJnRoaXMtPmh3Owo+ICAJ c3RydWN0IHJlc291cmNlcyAqciA9ICZ0aGlzLT5yZXNvdXJjZXM7Cj4gQEAgLTY1NywyMiArNjc4 LDM1IEBAIHN0YXRpYyB2b2lkIGdwbWlfbmZjX2NvbXB1dGVfdGltaW5ncyhzdHJ1Y3QgZ3BtaV9u YW5kX2RhdGEgKnRoaXMsCj4gIAlpbnQgc2FtcGxlX2RlbGF5X3BzLCBzYW1wbGVfZGVsYXlfZmFj dG9yOwo+ICAJdTE2IGJ1c3lfdGltZW91dF9jeWNsZXM7Cj4gIAl1OCB3cm5fZGx5X3NlbDsKPiAr CWxvbmcgY2xrX3JhdGU7Cj4gKwlpbnQgaSwgZW1vZGUgPSAtMTsKPiAgCj4gLQlpZiAoc2RyLT50 UkNfbWluID49IDMwMDAwKSB7Cj4gLQkJLyogT05GSSBub24tRURPIG1vZGVzIFswLTNdICovCj4g LQkJaHctPmNsa19yYXRlID0gMjIwMDAwMDA7Cj4gLQkJd3JuX2RseV9zZWwgPSBCVl9HUE1JX0NU UkwxX1dSTl9ETFlfU0VMXzRfVE9fOE5TOwo+IC0JfSBlbHNlIGlmIChzZHItPnRSQ19taW4gPj0g MjUwMDApIHsKPiAtCQkvKiBPTkZJIEVETyBtb2RlIDQgKi8KPiAtCQlody0+Y2xrX3JhdGUgPSA4 MDAwMDAwMDsKPiAtCQl3cm5fZGx5X3NlbCA9IEJWX0dQTUlfQ1RSTDFfV1JOX0RMWV9TRUxfTk9f REVMQVk7Cj4gLQl9IGVsc2Ugewo+IC0JCS8qIE9ORkkgRURPIG1vZGUgNSAqLwo+IC0JCWh3LT5j bGtfcmF0ZSA9IDEwMDAwMDAwMDsKPiAtCQl3cm5fZGx5X3NlbCA9IEJWX0dQTUlfQ1RSTDFfV1JO X0RMWV9TRUxfTk9fREVMQVk7CgpJIHdvdWxkIHJhdGhlciBwcmVmZXIgYSBwcmVwYXJhdGlvbiBw YXRjaCB3aGljaCBjaGFuZ2VzIG5vdGhpbmcgaW4gdGhlCmJlaGF2aW9yLCBidXQgcHJlcGFyZXMg dGhlIGZvbGxvd2luZyBjaGFuZ2Ugd2hlcmUgeW91IGFjdHVhbGx5IGRvCnNvbWV0aGluZyBkaWZm ZXJlbnQgc28gdGhhdCB3ZSBkb24ndCBtaSB0aGUgd3JuX2RseV9zZWwgY2hhbmdlIHdpdGggdGhl CmNsb2NrIHJhdGUgYXBwcm94aW1hdGlvbi4KCkFsc28sIHBsZWFzZSBjb25zaWRlciB1c2luZyB0 aGUgT05GSSBtb2RlcyBub3cgcHJvdmlkZWQgaW4gdGhlIHRpbWluZ3MKc3RydWN0dXJlIGlmIGl0 IGhlbHBzLgoKPiArCS8qIFNlYXJjaCB0aGUgcmVxdWlyZWQgRURPIG1vZGUgKi8KPiArCWZvciAo aSA9IDA7IGkgPCBBUlJBWV9TSVpFKGVkb19tb2Rlcyk7IGkrKykgewo+ICsJCWlmIChzZHItPnRS Q19taW4gPj0gZWRvX21vZGVzW2ldLnRSQ19taW4pIHsKPiArCQkJZW1vZGUgPSBpOwo+ICsJCQli cmVhazsKPiArCQl9Cj4gKwl9Cj4gKwo+ICsJaWYgKGVtb2RlIDwgMCkgewo+ICsJCWRldl9lcnIo dGhpcy0+ZGV2LCAidFJDX21pbiAlZCBub3Qgc3VwcG9ydGVkXG4iLCBzZHItPnRSQ19taW4pOwo+ ICsJCXJldHVybiAtRU5PVFNVUFA7Cj4gKwl9Cj4gKwo+ICsJY2xrX3JhdGUgPSBjbGtfcm91bmRf cmF0ZShyLT5jbG9ja1swXSwgZWRvX21vZGVzW2Vtb2RlXS5jbGtfcmF0ZSk7Cj4gKwlpZiAoZW1v ZGUgPiAwICYmICEoY2xrX3JhdGUgPD0gZWRvX21vZGVzW2Vtb2RlXS5jbGtfcmF0ZSAmJgo+ICsJ CQkgICBjbGtfcmF0ZSA+IGVkb19tb2Rlc1tlbW9kZSAtIDFdLmNsa19yYXRlKSkgewo+ICsJCWRl dl9lcnIodGhpcy0+ZGV2LAo+ICsJCQkiZWRvIG1vZGUgJWQgY2xvY2sgc2V0dGluZzogZXhwZWN0 ZWQgJWxkLCBnb3QgJWxkXG4iLAo+ICsJCQllbW9kZSwgZWRvX21vZGVzW2Vtb2RlXS5jbGtfcmF0 ZSwgY2xrX3JhdGUpOwo+ICsJCXJldHVybiAtRU5PVFNVUFA7Cj4gIAl9Cj4gIAo+IC0JaHctPmNs a19yYXRlID0gY2xrX3JvdW5kX3JhdGUoci0+Y2xvY2tbMF0sIGh3LT5jbGtfcmF0ZSk7Cj4gKwlk ZXZfZGJnKHRoaXMtPmRldiwgImVkbyBtb2RlICVkIEAgJWxkIEh6XG4iLCBlbW9kZSwgY2xrX3Jh dGUpOwo+ICsKPiArCWh3LT5jbGtfcmF0ZSA9IGNsa19yYXRlOwo+ICsJd3JuX2RseV9zZWwgPSBl ZG9fbW9kZXNbZW1vZGVdLndybl9kbHlfc2VsOwo+ICAKPiAgCS8qIFNEUiBjb3JlIHRpbWluZ3Mg YXJlIGdpdmVuIGluIHBpY29zZWNvbmRzICovCj4gIAlwZXJpb2RfcHMgPSBkaXZfdTY0KCh1NjQp TlNFQ19QRVJfU0VDICogMTAwMCwgaHctPmNsa19yYXRlKTsKPiBAQCAtNzE0LDYgKzc0OCw3IEBA IHN0YXRpYyB2b2lkIGdwbWlfbmZjX2NvbXB1dGVfdGltaW5ncyhzdHJ1Y3QgZ3BtaV9uYW5kX2Rh dGEgKnRoaXMsCj4gIAkJaHctPmN0cmwxbiB8PSBCRl9HUE1JX0NUUkwxX1JETl9ERUxBWShzYW1w bGVfZGVsYXlfZmFjdG9yKSB8Cj4gIAkJCSAgICAgIEJNX0dQTUlfQ1RSTDFfRExMX0VOQUJMRSB8 Cj4gIAkJCSAgICAgICh1c2VfaGFsZl9wZXJpb2QgPyBCTV9HUE1JX0NUUkwxX0hBTEZfUEVSSU9E IDogMCk7CgpTcGFjZQoKPiArCXJldHVybiAwOwo+ICB9Cj4gIAo+ICBzdGF0aWMgaW50IGdwbWlf bmZjX2FwcGx5X3RpbWluZ3Moc3RydWN0IGdwbWlfbmFuZF9kYXRhICp0aGlzKQo+IEBAIC03Njks NiArODA0LDcgQEAgc3RhdGljIGludCBncG1pX3NldHVwX2ludGVyZmFjZShzdHJ1Y3QgbmFuZF9j aGlwICpjaGlwLCBpbnQgY2hpcG5yLAo+ICB7Cj4gIAlzdHJ1Y3QgZ3BtaV9uYW5kX2RhdGEgKnRo aXMgPSBuYW5kX2dldF9jb250cm9sbGVyX2RhdGEoY2hpcCk7Cj4gIAljb25zdCBzdHJ1Y3QgbmFu ZF9zZHJfdGltaW5ncyAqc2RyOwo+ICsJaW50IHJldDsKPiAgCj4gIAkvKiBSZXRyaWV2ZSByZXF1 aXJlZCBOQU5EIHRpbWluZ3MgKi8KPiAgCXNkciA9IG5hbmRfZ2V0X3Nkcl90aW1pbmdzKGNvbmYp Owo+IEBAIC03ODQsNyArODIwLDkgQEAgc3RhdGljIGludCBncG1pX3NldHVwX2ludGVyZmFjZShz dHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBpbnQgY2hpcG5yLAo+ICAJCXJldHVybiAwOwo+ICAKPiAg CS8qIERvIHRoZSBhY3R1YWwgZGVyaXZhdGlvbiBvZiB0aGUgY29udHJvbGxlciB0aW1pbmdzICov Cj4gLQlncG1pX25mY19jb21wdXRlX3RpbWluZ3ModGhpcywgc2RyKTsKPiArCXJldCA9IGdwbWlf bmZjX2NvbXB1dGVfdGltaW5ncyh0aGlzLCBzZHIpOwo+ICsJaWYgKHJldCkKPiArCQlyZXR1cm4g cmV0Owo+ICAKPiAgCXRoaXMtPmh3Lm11c3RfYXBwbHlfdGltaW5ncyA9IHRydWU7Cj4gIAoKClRo YW5rcywKTWlxdcOobAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCkxpbnV4IE1URCBkaXNjdXNzaW9uIG1haWxpbmcgbGlzdApodHRwOi8vbGlz dHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LW10ZC8K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DAEEC433EF for ; Wed, 22 Dec 2021 16:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241760AbhLVQXa convert rfc822-to-8bit (ORCPT ); Wed, 22 Dec 2021 11:23:30 -0500 Received: from relay12.mail.gandi.net ([217.70.178.232]:53741 "EHLO relay12.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236333AbhLVQX2 (ORCPT ); Wed, 22 Dec 2021 11:23:28 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay12.mail.gandi.net (Postfix) with ESMTPSA id 48046200005; Wed, 22 Dec 2021 16:23:25 +0000 (UTC) Date: Wed, 22 Dec 2021 17:23:23 +0100 From: Miquel Raynal To: Dario Binacchi Cc: linux-kernel@vger.kernel.org, Michael Trimarchi , Han Xu , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org Subject: Re: [RFC PATCH 4/4] mtd: rawnand: gpmi: validate controller clock rate Message-ID: <20211222172323.1bc565c0@xps13> In-Reply-To: <20211217155512.1877408-5-dario.binacchi@amarulasolutions.com> References: <20211217155512.1877408-1-dario.binacchi@amarulasolutions.com> <20211217155512.1877408-5-dario.binacchi@amarulasolutions.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Dario, dario.binacchi@amarulasolutions.com wrote on Fri, 17 Dec 2021 16:55:12 +0100: > What to do when the real rate of the gpmi clock is not equal to the > required one? The solutions proposed in [1] did not lead to a conclusion > on how to validate the clock rate, so, inspired by the document [2], I > consider the rate correct only if not greater than the rate of the > previous edo. Not greater? what are you talking about here, if it's a rate, are you sure "not greater" is what you mean? > In fact, in chapter 4.16.2 (NV-DDR) of the document [2], > it is written that "If the host selects timing mode n, then its clock > period shall be faster than the clock period of timing mode n-1 and faster? is that the real wording in the document? seems inaccurate when referring to a clock period. > slower than or equal to the clock period of timing mode n.". I thought > that it could therefore also be used in this case, without therefore > having to define the valid rate ranges empirically. Can you give empirical values in your case so that we understand better the problem that you are trying to solve and how you solve it? Also, I don't know if the NV-DDR logic applies to SDR EDO modes, but if it works and if Han acknowledges it, it's fine for me. > [1] https://lore.kernel.org/r/20210702065350.209646-5-ebiggers@kernel.org > [2] http://www.onfi.org/-/media/client/onfi/specs/onfi_3_0_gold.pdf?la=en > > Signed-off-by: Dario Binacchi > Co-developed-by: Michael Trimarchi You need Michael's Signed-off-by. > > --- > > drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 70 +++++++++++++++++----- > 1 file changed, 54 insertions(+), 16 deletions(-) > > diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c > index 0517b81bb24c..3d37cd49abd5 100644 > --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c > +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c > @@ -570,6 +570,27 @@ static int bch_set_geometry(struct gpmi_nand_data *this) > return ret; > } > > +struct edo_mode { > + u32 tRC_min; > + long clk_rate; > + u8 wrn_dly_sel; > +}; > + > +static const struct edo_mode edo_modes[] = { > + {.tRC_min = 30000, .clk_rate = 22000000, Do you really need to provide a tRC_min here? It is already part of the nand_timings structure. > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, > + {.tRC_min = 30000, .clk_rate = 22000000, > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, > + {.tRC_min = 30000, .clk_rate = 22000000, > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, > + {.tRC_min = 30000, .clk_rate = 22000000, Not sure to get the difference between these three first modes. > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS}, > + {.tRC_min = 25000, .clk_rate = 80000000, > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY}, > + {.tRC_min = 20000, .clk_rate = 100000000, > + .wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY}, I am also tempted to say that I don't really understand what this is all about, maybe an explanation would be good in a comment. > +}; > + > /* > * <1> Firstly, we should know what's the GPMI-clock means. > * The GPMI-clock is the internal clock in the gpmi nand controller. > @@ -644,8 +665,8 @@ static int bch_set_geometry(struct gpmi_nand_data *this) > * RDN_DELAY = ----------------------- {3} > * RP > */ > -static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, > - const struct nand_sdr_timings *sdr) > +static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this, > + const struct nand_sdr_timings *sdr) > { > struct gpmi_nfc_hardware_timing *hw = &this->hw; > struct resources *r = &this->resources; > @@ -657,22 +678,35 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, > int sample_delay_ps, sample_delay_factor; > u16 busy_timeout_cycles; > u8 wrn_dly_sel; > + long clk_rate; > + int i, emode = -1; > > - if (sdr->tRC_min >= 30000) { > - /* ONFI non-EDO modes [0-3] */ > - hw->clk_rate = 22000000; > - wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; > - } else if (sdr->tRC_min >= 25000) { > - /* ONFI EDO mode 4 */ > - hw->clk_rate = 80000000; > - wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; > - } else { > - /* ONFI EDO mode 5 */ > - hw->clk_rate = 100000000; > - wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; I would rather prefer a preparation patch which changes nothing in the behavior, but prepares the following change where you actually do something different so that we don't mi the wrn_dly_sel change with the clock rate approximation. Also, please consider using the ONFI modes now provided in the timings structure if it helps. > + /* Search the required EDO mode */ > + for (i = 0; i < ARRAY_SIZE(edo_modes); i++) { > + if (sdr->tRC_min >= edo_modes[i].tRC_min) { > + emode = i; > + break; > + } > + } > + > + if (emode < 0) { > + dev_err(this->dev, "tRC_min %d not supported\n", sdr->tRC_min); > + return -ENOTSUPP; > + } > + > + clk_rate = clk_round_rate(r->clock[0], edo_modes[emode].clk_rate); > + if (emode > 0 && !(clk_rate <= edo_modes[emode].clk_rate && > + clk_rate > edo_modes[emode - 1].clk_rate)) { > + dev_err(this->dev, > + "edo mode %d clock setting: expected %ld, got %ld\n", > + emode, edo_modes[emode].clk_rate, clk_rate); > + return -ENOTSUPP; > } > > - hw->clk_rate = clk_round_rate(r->clock[0], hw->clk_rate); > + dev_dbg(this->dev, "edo mode %d @ %ld Hz\n", emode, clk_rate); > + > + hw->clk_rate = clk_rate; > + wrn_dly_sel = edo_modes[emode].wrn_dly_sel; > > /* SDR core timings are given in picoseconds */ > period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); > @@ -714,6 +748,7 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, > hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) | > BM_GPMI_CTRL1_DLL_ENABLE | > (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0); Space > + return 0; > } > > static int gpmi_nfc_apply_timings(struct gpmi_nand_data *this) > @@ -769,6 +804,7 @@ static int gpmi_setup_interface(struct nand_chip *chip, int chipnr, > { > struct gpmi_nand_data *this = nand_get_controller_data(chip); > const struct nand_sdr_timings *sdr; > + int ret; > > /* Retrieve required NAND timings */ > sdr = nand_get_sdr_timings(conf); > @@ -784,7 +820,9 @@ static int gpmi_setup_interface(struct nand_chip *chip, int chipnr, > return 0; > > /* Do the actual derivation of the controller timings */ > - gpmi_nfc_compute_timings(this, sdr); > + ret = gpmi_nfc_compute_timings(this, sdr); > + if (ret) > + return ret; > > this->hw.must_apply_timings = true; > Thanks, Miquèl