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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id q14sm15496432edd.40.2022.01.04.18.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 18:15:39 -0800 (PST) From: Johan Jonker To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, marex@denx.de, u-boot@lists.denx.de Subject: [PATCH v2] rockchip: timer: add OF_PLATDATA support for dw-apb-timer Date: Wed, 5 Jan 2022 03:15:33 +0100 Message-Id: <20220105021533.21838-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean The Rockchip rk3066 SoC has 3 dw-apb-timer nodes. U-boot is compiled with OF_PLATDATA TPL/SPL options, so add OF_PLATDATA support for the dw-apb-timer. Also change driver name to be able to compile with U-boot scripts. No reset OF_PLATDATA support was added, because the rk3066 nodes don't need/have them. Signed-off-by: Johan Jonker --- Changed V2: replace if (IS_ENABLED(OF_REAL)) by #if CONFIG_IS_ENABLED(OF_REAL) --- drivers/timer/dw-apb-timer.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 9aed5dd2..9ba8695f 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,12 @@ struct dw_apb_timer_priv { struct reset_ctl_bulk resets; }; +struct dw_apb_timer_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_snps_dw_apb_timer dtplat; +#endif +}; + static u64 dw_apb_timer_get_count(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); @@ -43,7 +50,18 @@ static int dw_apb_timer_probe(struct udevice *dev) struct dw_apb_timer_priv *priv = dev_get_priv(dev); struct clk clk; int ret; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dw_apb_timer_plat *plat = dev_get_plat(dev); + struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat; + priv->regs = dtplat->reg[0]; + + ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk); + if (ret < 0) + return ret; + + uc_priv->clock_rate = dtplat->clock_frequency; +#else ret = reset_get_bulk(dev, &priv->resets); if (ret) dev_warn(dev, "Can't get reset: %d\n", ret); @@ -57,7 +75,7 @@ static int dw_apb_timer_probe(struct udevice *dev) uc_priv->clock_rate = clk_get_rate(&clk); clk_free(&clk); - +#endif /* init timer */ writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); writel(0xffffffff, priv->regs + DW_APB_CURR_VAL); @@ -68,10 +86,11 @@ static int dw_apb_timer_probe(struct udevice *dev) static int dw_apb_timer_of_to_plat(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_REAL) struct dw_apb_timer_priv *priv = dev_get_priv(dev); priv->regs = dev_read_addr(dev); - +#endif return 0; } @@ -91,13 +110,14 @@ static const struct udevice_id dw_apb_timer_ids[] = { {} }; -U_BOOT_DRIVER(dw_apb_timer) = { - .name = "dw_apb_timer", +U_BOOT_DRIVER(snps_dw_apb_timer) = { + .name = "snps_dw_apb_timer", .id = UCLASS_TIMER, .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, .of_match = dw_apb_timer_ids, - .of_to_plat = dw_apb_timer_of_to_plat, + .of_to_plat = dw_apb_timer_of_to_plat, .remove = dw_apb_timer_remove, .priv_auto = sizeof(struct dw_apb_timer_priv), + .plat_auto = sizeof(struct dw_apb_timer_plat), }; -- 2.20.1