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From: Bjorn Helgaas <helgaas@kernel.org>
To: Stefan Roese <sr@denx.de>
Cc: "Pali Rohár" <pali@kernel.org>,
	linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Keith Busch" <kbusch@kernel.org>,
	"Bharat Kumar Gogada" <bharatku@xilinx.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>
Subject: Re: PCIe AER generates no interrupts on host (ZynqMP)
Date: Thu, 13 Jan 2022 15:32:30 -0600	[thread overview]
Message-ID: <20220113213230.GA433650@bhelgaas> (raw)
In-Reply-To: <8aa08fac-369b-096c-8d49-eeb9dd15fa59@denx.de>

On Thu, Jan 13, 2022 at 08:13:55AM +0100, Stefan Roese wrote:
> On 1/12/22 18:49, Bjorn Helgaas wrote:

> > Ah.  I assume you have:
> > 
> >    00:00.0 Root Port to [bus 01-??]
> >    01:00.0 Switch Upstream Port to [bus 02-??]
> >    02:0?.0 Switch Downstream Port to [bus 04-??]
> 
> This is correct, yes.
> 
> > pcie_portdrv_probe() claims 00:00.0 and clears CERE NFERE FERE URRE.
> > 
> > aer_probe() claims 00:00.0 and enables CERE NFERE FERE URRE for all
> > downstream devices, including 01:00.0.
> > 
> > pcie_portdrv_probe() claims 01:00.0 and clears CERE NFERE FERE URRE
> > again.
> > 
> > aer_probe() declines to claim 01:00.0 because it's not a Root Port, so
> > CERE NFERE FERE URRE remain cleared.

> I'm baffled a bit, that this problem of AER reporting being disabled in
> the DevCtl regs of PCIe ports (all non root ports) was not noticed for
> this long time. As AER is practically disabled in such setups.

The more common configuration is a Root Port leading directly to an
Endpoint.  In that case, there would be no pcie_portdrv_probe() in the
middle to disable reporting after aer_probe() has enabled it.

The issue you're seeing happens because of the switch in the middle, 
which is becoming more common recently with Thunderbolt.

I poked around on my laptop (Dell 5520 running v5.4):

  00:01.0 Root Port       to [bus 01]          CorrErr-
  01:00.0 NVIDIA GPU                           CorrErr-

  00:1c.0 Root Port       to [bus 02]     AER  CorrErr+
  02:00.0 Intel NIC                       AER  CorrErr-  <-- iwlwifi

  00:1c.1 Root Port       to [bus 03]     AER  CorrErr+
  03:00.0 Realtek card reader             AER  CorrErr-  <-- rtsx_pci

  00:1d.0 Root Port       to [bus 04]     AER  CorrErr+
  04:00.0 NVMe                            AER  CorrErr+

  00:1d.6 Root Port       to [bus 06-3e]  AER  CorrErr+
  06:00.0 Thunderbolt USP to [bus 07-3e]  AER  CorrErr-
  07:00.0 Thunderbolt DSP to [bus 08]     AER  CorrErr-
  ...                                          CorrErr-

Everything in the Thunderbolt hierarchy has reporting disabled,
probably because of the issue you are pointing out.

I can't explain the iwlwifi and rtsx_pci cases.  Both devices have AER
and are directly below a Root Port that also has AER, so I would think
reporting should be enabled.

Bjorn

  reply	other threads:[~2022-01-13 21:32 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-04  9:02 PCIe AER generates no interrupts on host (ZynqMP) Stefan Roese
2022-01-07 10:04 ` Pali Rohár
2022-01-07 20:34   ` Bjorn Helgaas
2022-01-07 21:31     ` Pali Rohár
2022-01-08  3:13       ` Bjorn Helgaas
2022-01-10 11:12         ` Pali Rohár
2022-01-10 12:17     ` Stefan Roese
2022-01-10 12:16   ` Stefan Roese
2022-01-11  8:14     ` Stefan Roese
2022-01-12 17:49       ` Bjorn Helgaas
2022-01-13  7:13         ` Stefan Roese
2022-01-13 21:32           ` Bjorn Helgaas [this message]
2022-01-14  6:25             ` Stefan Roese
2022-01-14 18:30               ` Bjorn Helgaas
2022-01-14 18:38                 ` Pali Rohár
2022-01-17  6:24                 ` Stefan Roese

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