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Thu, 13 Jan 2022 19:37:54 -0600 From: Wayne Lin To: Subject: [PATCH 09/13] drm/amd/display: Fix black screen issue on memory clock switch en Date: Fri, 14 Jan 2022 09:36:53 +0800 Message-ID: <20220114013657.3119627-10-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220114013657.3119627-1-Wayne.Lin@amd.com> References: <20220114013657.3119627-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fbd05607-7043-4aab-f633-08d9d6fe7fb2 X-MS-TrafficTypeDiagnostic: DM6PR12MB4465:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6foPdT/uSLEL76uEy+psNoENSB1RRheA1rF/g0MKKENY1MCq7WUbddOioRpuACUrHEa3T61hP5xSX4orHgbWS9odfmJo3FBWBMCjXhNqf4c7XgNiVRX3oclPaJz8pENoTPslVIG9SavNwsjYjUtKkJY2vXSE/fpNhQD9zoB5I7wfg8b7nA4Qu6U6Ltv0K2ELDH9SaHTvbqbs2zXnAAZ3x116s4p+CljJwxXQbxJN46onncL0scPG18VFr2z5Wr3ZYOOzwtNmRPWxN29tRfAUdDVWMOLTyvFFt3+AwAOxRe7VG8oPXXmv95D+DHOfPWa1nReJvDV9csxWX0P+vA0F/YqqHEy1kQBZalb6zVzIk2VD213ASPfSlQxJ1DVH+/cANtPZMsyouvy8Ye7SqXwydVTW3bJrFFoRmEM1coJUQ4yF0PfBaNQxgN+J2/D6sfeCmsZDGu/62oEz7Z+cXOZwI7sgclGLP7E94db5A/ezdWFoxizBhJj4ITM5SdONyfTaI5L3tZDRLIXU2Dt6HfIvKpzt51fxpuTZA0lo2zD3oIlF1ylS/5H7zG9WZ9X16O1tbG5gSmAufQky8v3Qgr+SoGud7NNxCcgd2FWKiHuYJmAjuBqlqHkmRimOhm93weNfRUK9TZUUrut/NCgiToIMWnWoK+VbHiFkO+JHSAm8f9s/rPD3EPIgZ31zXlgeENKkel6v8eucNrAFtF581dStJUHXWoya68uls3eoJWjWKGvVWcxUa+q5zzIQn9MQmU1qXvoahex5XVS348BTvGNAmVQcao3GJnYHE17oODNUOGk= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(40470700002)(1076003)(8936002)(70206006)(356005)(4326008)(83380400001)(316002)(7696005)(47076005)(70586007)(336012)(426003)(86362001)(36860700001)(508600001)(6916009)(26005)(40460700001)(81166007)(82310400004)(2906002)(54906003)(186003)(5660300002)(2616005)(36756003)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2022 01:38:00.1326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbd05607-7043-4aab-f633-08d9d6fe7fb2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4465 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Aric Cyr , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Felipe Clark , Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, Felipe Clark , wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Felipe Clark [WHY] With some monitors when multi plane overlay is enabled the memory clock switching mechanism has to change and, due to an error in the initialization sequence, it may cause a black screen. [HOW] Change the firmware assisted memory clock switch initialization and tear-down sequence utilizing the prepare_bandwidth and optimize_bandwidth contexts. Reviewed-by: Aric Cyr Acked-by: Wayne Lin Signed-off-by: Felipe Clark --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 +++ drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index ed0a0e5fd805..dec8604a0612 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -355,6 +355,11 @@ void dcn30_prepare_bandwidth(struct dc *dc, dcn20_prepare_bandwidth(dc, context); } +void dcn30_optimize_bandwidth(struct dc *dc, struct dc_state *context) +{ + dcn20_optimize_bandwidth(dc, context); +} + void dcn30_disable_writeback( struct dc *dc, unsigned int dwb_pipe_inst) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h index 73e7b690e82c..357ee14711ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h @@ -50,6 +50,9 @@ void dcn30_disable_writeback( void dcn30_prepare_bandwidth(struct dc *dc, struct dc_state *context); +void dcn30_optimize_bandwidth(struct dc *dc, + struct dc_state *context); + bool dcn30_mmhubbub_warmup( struct dc *dc, unsigned int num_dwb, diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index bb347319de83..73a416cba563 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -60,7 +60,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .interdependent_update_lock = dcn10_lock_all_pipes, .cursor_lock = dcn10_cursor_lock, .prepare_bandwidth = dcn20_prepare_bandwidth, - .optimize_bandwidth = dcn20_optimize_bandwidth, + .optimize_bandwidth = dcn30_optimize_bandwidth, .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, .get_position = dcn10_get_position, -- 2.25.1