[PATCH v2 00/14] target/ppc: powerpc_excp improvements [40x] (3/n)

[Fabiano Rosas <farosas@linux.ibm.com>]

changes from v1:

- New patch that renames MSR_POW to MSR_WE for the 405.

- New patch that adds just MSR_ME to the msr_mask.

- New patches to cleanup exceptions I missed the first time around.

- Dropped the patch that added all the missing MSR bits. We have an
  issue when two different MSR bits share the same number in different
  CPUs. Described in v1 here:

  https://lists.nongnu.org/archive/html/qemu-ppc/2022-01/msg00503.html

- Dropped the patch that adds missing exception vectors because Linux
  clearly cannot handle them. And I don't have access to real hardware
  to confirm some of the questions raised, so let's keep things as they
  are.

- Kept the split in two patches. One that copies powerpc_excp_legacy
  and other that does the changes.

Based on legoater/ppc-7.0

With only the fixes from the above branch, the ref405ep machine boots
until the shell. This series doesn't change that.

v1:
https://lists.nongnu.org/archive/html/qemu-ppc/2022-01/msg00300.html

Fabiano Rosas (14):
  target/ppc: 405: Rename MSR_POW to MSR_WE
  target/ppc: 405: Add missing MSR_ME bit
  target/ppc: Introduce powerpc_excp_40x
  target/ppc: Simplify powerpc_excp_40x
  target/ppc: 405: Critical exceptions cleanup
  target/ppc: 405: Machine check exception cleanup
  target/ppc: 405: External exception cleanup
  target/ppc: 405: System call exception cleanup
  target/ppc: 405: Alignment exception cleanup
  target/ppc: 405: Debug exception cleanup
  target/ppc: 405: Data Storage exception cleanup
  target/ppc: 405: Instruction storage interrupt cleanup
  target/ppc: 405: Program exception cleanup
  target/ppc: 405: Watchdog timer exception cleanup

 target/ppc/cpu.h         |   1 +
 target/ppc/cpu_init.c    |   3 +-
 target/ppc/excp_helper.c | 159 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 161 insertions(+), 2 deletions(-)

-- 
2.33.1