diff for duplicates of <202201191446.e8ud7CAP-lkp@intel.com> diff --git a/a/1.txt b/N1/1.txt index 67df607..f374b59 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ tree: https://github.com/esmil/linux visionfive head: e46c3a7e373e6faa03399f1a41c29cf7546c37cb commit: 37af0be028777ba2227a48b8d94ff92f52f7aba7 [75/80] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs -config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp(a)intel.com/config) +config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross @@ -69,7 +69,7 @@ d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-0 d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 #endif d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 -:::::: The code@line 157 was first introduced by commit +:::::: The code at line 157 was first introduced by commit :::::: d21f24663c127ec288f925cd991a1d767e1dd609 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function :::::: TO: Tom <support@vamrs.com> @@ -77,4 +77,4 @@ d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-0 --- 0-DAY CI Kernel Test Service, Intel Corporation -https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org +https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org diff --git a/a/content_digest b/N1/content_digest index 0fdabc9..1c7ffc2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,15 @@ "From\0kernel test robot <lkp@intel.com>\0" "Subject\0[esmil:visionfive 75/80] drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'?\0" "Date\0Wed, 19 Jan 2022 14:27:34 +0800\0" - "To\0kbuild-all@lists.01.org\0" - "\01:1\0" + "To\0Emil Renner Berthing <kernel@esmil.dk>\0" + "Cc\0kbuild-all@lists.01.org" + " linux-kernel@vger.kernel.org\0" + "\00:1\0" "b\0" "tree: https://github.com/esmil/linux visionfive\n" "head: e46c3a7e373e6faa03399f1a41c29cf7546c37cb\n" "commit: 37af0be028777ba2227a48b8d94ff92f52f7aba7 [75/80] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs\n" - "config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp(a)intel.com/config)\n" + "config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp@intel.com/config)\n" "compiler: riscv32-linux-gcc (GCC) 11.2.0\n" "reproduce (this is a W=1 build):\n" " wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n" @@ -75,7 +77,7 @@ "d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 #endif\n" "d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 \n" "\n" - ":::::: The code@line 157 was first introduced by commit\n" + ":::::: The code at line 157 was first introduced by commit\n" ":::::: d21f24663c127ec288f925cd991a1d767e1dd609 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function\n" "\n" ":::::: TO: Tom <support@vamrs.com>\n" @@ -83,6 +85,6 @@ "\n" "---\n" "0-DAY CI Kernel Test Service, Intel Corporation\n" - https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org + https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org -1f013863631116d868eed6ec19e1d2582f82bc6c21c01099cb741e88d7e73b63 +8cec92e90350010a2ca47c9d4c30764ef1a116e7c667a379520518e4c0342a65
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