From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B241C433F5 for ; Fri, 21 Jan 2022 03:33:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=BNoc5xZkI9zuM7MUYr4U2emOyPmgnR1cWqrf2IaqTNI=; b=dcF/iBj72NOGHB 7qH3ohjDw3a2vu3eaNg57gNWKtLeBbdK3u8u7p+2R9LIbFxYfzImZfZatlV0jbpqz9u2jQWSXgmkv EwaU8Y7bph58Eg6rogMTVR+Vh2ehUJLXMa34Fh5CJplIXIHHWUrolCQFnJSrpxG+bT4w8Iqaa/MlD Bf8LhrPnDt5keETTdQ09oTp9H2Wf5UCqu+VnPAlWAd60s891Fs/jWxCUTaTAaDkGzAzqTGY4AzWYA JiRs2IXwIKie/v/Sz7qRQbZzcEOLeZv79bUWDMx9JiNRhNqGg66N7ukHt+bjukbuCjimICRXQ5buj 5YJLTfzP5oUxUuWHcukg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAkeJ-00DkCI-V3; Fri, 21 Jan 2022 03:31:40 +0000 Received: from mga04.intel.com ([192.55.52.120]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nAkeF-00DkBk-4U for linux-arm-kernel@lists.infradead.org; Fri, 21 Jan 2022 03:31:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642735895; x=1674271895; h=date:from:to:cc:subject:message-id:mime-version; bh=bKIhTcTZGKJeKBzevuD11S4oexZEOYExRSpEfCKCYR8=; b=gKNRZMFunolmATUZKO9GfbKb7J3gKGGo8uDKSOMCev2fH3EeRI842B9H nFDIvfoeuI5ln/CJUa7c1xgsS/Ge/N66t43mUKLxRngDV/mygO9suzN1C +jc2u3ARDjUUBm+YsgKa7QAOmjtKIsPkMDdoawRWWDDteo5+ZB8RCGdJg W6Bi+bdZS0CAuIzWG6E029HivE1BtOO4BAmyJY1jVXe0NxfK2P49oR2Ar EViiXFEYBvPbpcwekPqCmUNBfBmccKz+4Ut7fERfl29R+KbW9aab37atf ag8lB7GXAMKCdkxP/cuKfiDes48BhSGMXK44ityZOVapqtlG0BYWklfi8 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10233"; a="244376355" X-IronPort-AV: E=Sophos;i="5.88,304,1635231600"; d="scan'208";a="244376355" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2022 19:31:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,304,1635231600"; d="scan'208";a="518904941" Received: from lkp-server01.sh.intel.com (HELO 276f1b88eecb) ([10.239.97.150]) by orsmga007.jf.intel.com with ESMTP; 20 Jan 2022 19:31:27 -0800 Received: from kbuild by 276f1b88eecb with local (Exim 4.92) (envelope-from ) id 1nAke6-000Er1-Vc; Fri, 21 Jan 2022 03:31:26 +0000 Date: Fri, 21 Jan 2022 11:31:12 +0800 From: kernel test robot To: Shubhrajyoti Datta Cc: kbuild-all@lists.01.org, linux-arm-kernel@lists.infradead.org, Michal Simek Subject: [xilinx-xlnx:master 129/395] drivers/clk/clk-xlnx-clock-wizard-v.c:164:16: error: implicit declaration of function 'FIELD_GET'; did you mean 'FOLL_GET'? Message-ID: <202201211116.bvPrCZMH-lkp@intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220120_193135_227696_1317AE97 X-CRM114-Status: GOOD ( 15.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Shubhrajyoti, FYI, the error/warning still remains. tree: https://github.com/Xilinx/linux-xlnx master head: 6057b70444aa27680466a4b33d68b18f415d495b commit: c1e2db426dc728a5417024c9bd75c39ec81331d9 [129/395] clocking-wizard: Support higher frequency accuracy config: powerpc-allmodconfig (https://download.01.org/0day-ci/archive/20220121/202201211116.bvPrCZMH-lkp@intel.com/config) compiler: powerpc-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/Xilinx/linux-xlnx/commit/c1e2db426dc728a5417024c9bd75c39ec81331d9 git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx git fetch --no-tags xilinx-xlnx master git checkout c1e2db426dc728a5417024c9bd75c39ec81331d9 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/clk/ drivers/media/platform/xilinx/ drivers/phy/xilinx/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate_all': >> drivers/clk/clk-xlnx-clock-wizard-v.c:164:16: error: implicit declaration of function 'FIELD_GET'; did you mean 'FOLL_GET'? [-Werror=implicit-function-declaration] 164 | regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); | ^~~~~~~~~ | FOLL_GET drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_get_divisors': drivers/clk/clk-xlnx-clock-wizard-v.c:229:25: warning: this decimal constant is unsigned only in ISO C90 229 | if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) { | ^~ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_all_nolock': >> drivers/clk/clk-xlnx-clock-wizard-v.c:276:19: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 276 | regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged); | ^~~~~~~~~~ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate': drivers/clk/clk-xlnx-clock-wizard-v.c:342:42: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 342 | (void __iomem *)((u64)divider->base + divider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c:342:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 342 | (void __iomem *)((u64)divider->base + divider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_reconfig': drivers/clk/clk-xlnx-clock-wizard-v.c:375:42: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 375 | (void __iomem *)((u64)divider->base + divider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c:375:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 375 | (void __iomem *)((u64)divider->base + divider->offset); | ^ cc1: some warnings being treated as errors vim +164 drivers/clk/clk-xlnx-clock-wizard-v.c 154 155 static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw, 156 unsigned long parent_rate) 157 { 158 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 159 u32 edged, div, div2, p5en, edge, prediv2, all, regl, regh, mult, reg; 160 161 edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)) & WZRD_CLKFBOUT_EDGE); 162 163 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2)); > 164 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 165 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 166 167 mult = regl + regh + edge; 168 if (!mult) 169 mult = 1; 170 171 regl = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4)) & 172 WZRD_CLKFBOUT_FRAC_EN; 173 if (regl) { 174 regl = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_3)) & 175 WZRD_CLKFBOUT_FRAC_MASK; 176 mult = mult * WZRD_FRAC_GRADIENT + regl; 177 parent_rate = DIV_ROUND_CLOSEST((parent_rate * mult), WZRD_FRAC_GRADIENT); 178 } else { 179 parent_rate = parent_rate * mult; 180 } 181 182 /* O Calculation */ 183 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 184 edged = FIELD_GET(WZRD_CLKFBOUT_EDGE, reg); 185 p5en = FIELD_GET(WZRD_P5EN, reg); 186 prediv2 = FIELD_GET(WZRD_CLKOUT0_PREDIV2, reg); 187 188 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2)); 189 /* Low time */ 190 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 191 /* High time */ 192 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 193 all = regh + regl + edged; 194 if (!all) 195 all = 1; 196 197 if (prediv2) 198 div2 = PREDIV2_MULT * all + p5en; 199 else 200 div2 = all; 201 202 /* D calculation */ 203 edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2)) & 204 WZRD_DIVCLK_EDGE); 205 reg = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK)); 206 /* Low time */ 207 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 208 /* High time */ 209 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 210 div = regl + regh + edged; 211 if (!div) 212 div = 1; 213 214 div = div * div2; 215 return divider_recalc_rate(hw, parent_rate, div, divider->table, 216 divider->flags, divider->width); 217 } 218 219 static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate, 220 unsigned long parent_rate) 221 { 222 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 223 u64 vco_freq, freq, diff; 224 u32 m, d, o; 225 226 for (m = WZRD_M_MIN; m <= WZRD_M_MAX; m++) { 227 for (d = WZRD_D_MIN; d <= WZRD_D_MAX; d++) { 228 vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d); 229 if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) { 230 for (o = WZRD_O_MIN; o <= WZRD_O_MAX; o++) { 231 freq = DIV_ROUND_CLOSEST(vco_freq, o); 232 diff = abs(freq - rate); 233 234 if (diff < WZRD_MIN_ERR) { 235 divider->valuem = m; 236 divider->valued = d; 237 divider->valueo = o; 238 return 0; 239 } 240 } 241 } 242 } 243 } 244 return -EBUSY; 245 } 246 247 static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate, 248 unsigned long parent_rate) 249 { 250 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 251 u32 value, regh, edged, p5en, p5fedge, value2, m, regval, regval1; 252 int err; 253 254 err = clk_wzrd_get_divisors(hw, rate, parent_rate); 255 if (err) 256 return err; 257 258 writel(0, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4)); 259 260 m = divider->valuem; 261 edged = m % WZRD_DUTY_CYCLE; 262 regh = m / WZRD_DUTY_CYCLE; 263 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)); 264 regval1 |= WZRD_MULT_PREDIV2; 265 if (edged) 266 regval1 = regval1 | WZRD_CLKFBOUT_EDGE; 267 else 268 regval1 = regval1 & ~WZRD_CLKFBOUT_EDGE; 269 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)); 270 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT; 271 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2)); 272 273 value2 = divider->valued; 274 edged = value2 % WZRD_DUTY_CYCLE; 275 regh = (value2 / WZRD_DUTY_CYCLE); > 276 regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged); 277 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2)); 278 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT; 279 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK)); 280 281 value = divider->valueo; 282 regh = value / WZRD_O_DIV; 283 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 284 regval1 |= WZRD_CLKFBOUT_PREDIV2; 285 regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE); 286 if (value % WZRD_O_DIV > 1) { 287 edged = 1; 288 regval1 |= edged << WZRD_CLKFBOUT_H_SHIFT; 289 } 290 p5fedge = value % WZRD_DUTY_CYCLE; 291 p5en = value % WZRD_DUTY_CYCLE; 292 293 regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge); 294 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 295 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT; 296 writel(regval, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2)); 297 298 /* Check status register */ 299 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 300 value, value & WZRD_DR_LOCK_BIT_MASK, 301 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 302 if (err) 303 return err; 304 305 /* Initiate reconfiguration */ 306 writel(WZRD_DR_BEGIN_DYNA_RECONF, 307 divider->base + WZRD_DR_INIT_REG_OFFSET); 308 309 /* Check status register */ 310 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 311 value, value & WZRD_DR_LOCK_BIT_MASK, 312 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 313 } 314 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============1107661708835857168==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: [xilinx-xlnx:master 129/395] drivers/clk/clk-xlnx-clock-wizard-v.c:164:16: error: implicit declaration of function 'FIELD_GET'; did you mean 'FOLL_GET'? Date: Fri, 21 Jan 2022 11:31:12 +0800 Message-ID: <202201211116.bvPrCZMH-lkp@intel.com> List-Id: --===============1107661708835857168== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Shubhrajyoti, FYI, the error/warning still remains. tree: https://github.com/Xilinx/linux-xlnx master head: 6057b70444aa27680466a4b33d68b18f415d495b commit: c1e2db426dc728a5417024c9bd75c39ec81331d9 [129/395] clocking-wizard:= Support higher frequency accuracy config: powerpc-allmodconfig (https://download.01.org/0day-ci/archive/20220= 121/202201211116.bvPrCZMH-lkp(a)intel.com/config) compiler: powerpc-linux-gcc (GCC) 11.2.0 reproduce (this is a W=3D1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/= make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/Xilinx/linux-xlnx/commit/c1e2db426dc728a541702= 4c9bd75c39ec81331d9 git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx git fetch --no-tags xilinx-xlnx master git checkout c1e2db426dc728a5417024c9bd75c39ec81331d9 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=3D$HOME/0day COMPILER=3Dgcc-11.2.0 make.cross= O=3Dbuild_dir ARCH=3Dpowerpc SHELL=3D/bin/bash drivers/clk/ drivers/media/= platform/xilinx/ drivers/phy/xilinx/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate= _all': >> drivers/clk/clk-xlnx-clock-wizard-v.c:164:16: error: implicit declaratio= n of function 'FIELD_GET'; did you mean 'FOLL_GET'? [-Werror=3Dimplicit-fun= ction-declaration] 164 | regl =3D FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); | ^~~~~~~~~ | FOLL_GET drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_get_divisor= s': drivers/clk/clk-xlnx-clock-wizard-v.c:229:25: warning: this decimal cons= tant is unsigned only in ISO C90 229 | if (vco_freq >=3D WZRD_VCO_MIN && vco_fr= eq <=3D WZRD_VCO_MAX) { | ^~ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_all= _nolock': >> drivers/clk/clk-xlnx-clock-wizard-v.c:276:19: error: implicit declaratio= n of function 'FIELD_PREP' [-Werror=3Dimplicit-function-declaration] 276 | regval1 =3D FIELD_PREP(WZRD_DIVCLK_EDGE, edged); | ^~~~~~~~~~ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_recalc_rate= ': drivers/clk/clk-xlnx-clock-wizard-v.c:342:42: warning: cast from pointer= to integer of different size [-Wpointer-to-int-cast] 342 | (void __iomem *)((u64)divider->base + di= vider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c:342:25: warning: cast to pointer f= rom integer of different size [-Wint-to-pointer-cast] 342 | (void __iomem *)((u64)divider->base + di= vider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c: In function 'clk_wzrd_dynamic_rec= onfig': drivers/clk/clk-xlnx-clock-wizard-v.c:375:42: warning: cast from pointer= to integer of different size [-Wpointer-to-int-cast] 375 | (void __iomem *)((u64)divider->base + di= vider->offset); | ^ drivers/clk/clk-xlnx-clock-wizard-v.c:375:25: warning: cast to pointer f= rom integer of different size [-Wint-to-pointer-cast] 375 | (void __iomem *)((u64)divider->base + di= vider->offset); | ^ cc1: some warnings being treated as errors vim +164 drivers/clk/clk-xlnx-clock-wizard-v.c 154 = 155 static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw, 156 unsigned long parent_rate) 157 { 158 struct clk_wzrd_divider *divider =3D to_clk_wzrd_divider(hw); 159 u32 edged, div, div2, p5en, edge, prediv2, all, regl, regh, mult, r= eg; 160 = 161 edge =3D !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)= ) & WZRD_CLKFBOUT_EDGE); 162 = 163 reg =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2)); > 164 regl =3D FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 165 regh =3D FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 166 = 167 mult =3D regl + regh + edge; 168 if (!mult) 169 mult =3D 1; 170 = 171 regl =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4)) & 172 WZRD_CLKFBOUT_FRAC_EN; 173 if (regl) { 174 regl =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_3)) & 175 WZRD_CLKFBOUT_FRAC_MASK; 176 mult =3D mult * WZRD_FRAC_GRADIENT + regl; 177 parent_rate =3D DIV_ROUND_CLOSEST((parent_rate * mult), WZRD_FRAC_= GRADIENT); 178 } else { 179 parent_rate =3D parent_rate * mult; 180 } 181 = 182 /* O Calculation */ 183 reg =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 184 edged =3D FIELD_GET(WZRD_CLKFBOUT_EDGE, reg); 185 p5en =3D FIELD_GET(WZRD_P5EN, reg); 186 prediv2 =3D FIELD_GET(WZRD_CLKOUT0_PREDIV2, reg); 187 = 188 reg =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2)); 189 /* Low time */ 190 regl =3D FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 191 /* High time */ 192 regh =3D FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 193 all =3D regh + regl + edged; 194 if (!all) 195 all =3D 1; 196 = 197 if (prediv2) 198 div2 =3D PREDIV2_MULT * all + p5en; 199 else 200 div2 =3D all; 201 = 202 /* D calculation */ 203 edged =3D !!(readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2))= & 204 WZRD_DIVCLK_EDGE); 205 reg =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK)); 206 /* Low time */ 207 regl =3D FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg); 208 /* High time */ 209 regh =3D FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg); 210 div =3D regl + regh + edged; 211 if (!div) 212 div =3D 1; 213 = 214 div =3D div * div2; 215 return divider_recalc_rate(hw, parent_rate, div, divider->table, 216 divider->flags, divider->width); 217 } 218 = 219 static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long ra= te, 220 unsigned long parent_rate) 221 { 222 struct clk_wzrd_divider *divider =3D to_clk_wzrd_divider(hw); 223 u64 vco_freq, freq, diff; 224 u32 m, d, o; 225 = 226 for (m =3D WZRD_M_MIN; m <=3D WZRD_M_MAX; m++) { 227 for (d =3D WZRD_D_MIN; d <=3D WZRD_D_MAX; d++) { 228 vco_freq =3D DIV_ROUND_CLOSEST((parent_rate * m), d); 229 if (vco_freq >=3D WZRD_VCO_MIN && vco_freq <=3D WZRD_VCO_MAX) { 230 for (o =3D WZRD_O_MIN; o <=3D WZRD_O_MAX; o++) { 231 freq =3D DIV_ROUND_CLOSEST(vco_freq, o); 232 diff =3D abs(freq - rate); 233 = 234 if (diff < WZRD_MIN_ERR) { 235 divider->valuem =3D m; 236 divider->valued =3D d; 237 divider->valueo =3D o; 238 return 0; 239 } 240 } 241 } 242 } 243 } 244 return -EBUSY; 245 } 246 = 247 static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned l= ong rate, 248 unsigned long parent_rate) 249 { 250 struct clk_wzrd_divider *divider =3D to_clk_wzrd_divider(hw); 251 u32 value, regh, edged, p5en, p5fedge, value2, m, regval, regval1; 252 int err; 253 = 254 err =3D clk_wzrd_get_divisors(hw, rate, parent_rate); 255 if (err) 256 return err; 257 = 258 writel(0, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_4)); 259 = 260 m =3D divider->valuem; 261 edged =3D m % WZRD_DUTY_CYCLE; 262 regh =3D m / WZRD_DUTY_CYCLE; 263 regval1 =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)= ); 264 regval1 |=3D WZRD_MULT_PREDIV2; 265 if (edged) 266 regval1 =3D regval1 | WZRD_CLKFBOUT_EDGE; 267 else 268 regval1 =3D regval1 & ~WZRD_CLKFBOUT_EDGE; 269 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_1)); 270 regval1 =3D regh | regh << WZRD_CLKFBOUT_H_SHIFT; 271 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKFBOUT_2)); 272 = 273 value2 =3D divider->valued; 274 edged =3D value2 % WZRD_DUTY_CYCLE; 275 regh =3D (value2 / WZRD_DUTY_CYCLE); > 276 regval1 =3D FIELD_PREP(WZRD_DIVCLK_EDGE, edged); 277 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DESKEW_2)); 278 regval1 =3D regh | regh << WZRD_CLKFBOUT_H_SHIFT; 279 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_DIVCLK)); 280 = 281 value =3D divider->valueo; 282 regh =3D value / WZRD_O_DIV; 283 regval1 =3D readl(divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 284 regval1 |=3D WZRD_CLKFBOUT_PREDIV2; 285 regval1 =3D regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FED= GE); 286 if (value % WZRD_O_DIV > 1) { 287 edged =3D 1; 288 regval1 |=3D edged << WZRD_CLKFBOUT_H_SHIFT; 289 } 290 p5fedge =3D value % WZRD_DUTY_CYCLE; 291 p5en =3D value % WZRD_DUTY_CYCLE; 292 = 293 regval1 =3D regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD= _P5FEDGE, p5fedge); 294 writel(regval1, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_1)); 295 regval =3D regh | regh << WZRD_CLKFBOUT_H_SHIFT; 296 writel(regval, divider->base + WZRD_CLK_CFG_REG(WZRD_CLKOUT0_2)); 297 = 298 /* Check status register */ 299 err =3D readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSE= T, 300 value, value & WZRD_DR_LOCK_BIT_MASK, 301 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 302 if (err) 303 return err; 304 = 305 /* Initiate reconfiguration */ 306 writel(WZRD_DR_BEGIN_DYNA_RECONF, 307 divider->base + WZRD_DR_INIT_REG_OFFSET); 308 = 309 /* Check status register */ 310 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSE= T, 311 value, value & WZRD_DR_LOCK_BIT_MASK, 312 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 313 } 314 = --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============1107661708835857168==--